Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - system monitor Dual voltage detector VSSOP 8

RSL2RSL3

RSH2RSH3

TPS386596

SENSE1

SENSE3

SENSE2

VCC

GND

DSP

CPU

FPGA

RESET

____

RESET

____

DC-DC

LDO

DC-DC

LDO

DC-DC

LDO

VCC1 VCC3VCC2

VIN

DC-DC

LDO

3.3V

SENSE4

VCC4

RSL4

RSH4

Sub CPU

MSP430

TPS386596L33

www.ti.com

SLVSA75 –JULY 2010

Quad Reset Supervisor with Manual Reset Input

Check for Samples: TPS386596L33

FEATURES

DESCRIPTION

• 4 Voltage Monitors

• Threshold Accuracy: 0.25% (Typical)

The TPS386596L33 monitors four power rails and

asserts the RESET signal when any of the SENSE

• Fixed 50ms RESETdelay time

inputs drop below their respective thresholds. SVS-1

• Active Low Manual Reset Input

can be used to monitor a 3.3V nominal power supply

• Very Low Quiescent Current: 7µA typical

with no external components required. SVS-2, SVS-3,

and SVS-4 are adjustable using external resistors

• SVS-1: Fixed Threshold for monitoring 3.3V

and can be used to monitor any power supply voltage

• SVS-2/3/4 – Adjustable Threshold Down to

higher than 0.4V. All SENSE inputs have a threshold

0.4V

accuracy of 0.25% (typical). The TPS386596L33 also

• Open Drain RESET Output

has an active low Manual Reset (MR) that can be

used to assert the RESET signal as desired by the

• Space Saving 8-pin MSOP Package

application. The open drain, active low RESEToutput

de-asserts using a fixed 50ms delay.

APPLICATIONS

The TPS386596L33 has a low quiescent current of

• Notebook / Desktop Computers

7µA typical and is available in a space saving 8-pin

• Industrial Equipment

MSOP package.

• Telecom, Networking Infrastructure

• Server, Storage Equipment

• DSP and Microcontroller Applications

• FPGA/ASIC Applications

SPACER

Figure 1. TPS386596L33 Typical Application Circuit

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (15 pages)

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TPS386596L33 www.ti.com SLVSA75 – JULY 2010 Quad Reset Supervisor with Manual Reset Input Check for Samples: TPS386596L33 FEATURES 1 • • • • • • • • • DESCRIPTION 4 Voltage Monitors Threshold Accuracy: 0.25% (Typical) Fixed 50ms RESETdelay time Active Low Manual Reset Input Very Low Quiescent Current: 7µA typical SVS-1: Fixed Threshold for monitoring 3.3V SVS-2/3/4 – Adjustable Threshold Down to 0.
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TPS386596L33 SLVSA75 – JULY 2010 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. Custom threshold voltages from 0.80V to 4.6V, 4.8V to 6.
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TPS386596L33 www.ti.com SLVSA75 – JULY 2010 ELECTRICAL CHARACTERISTICS Over the operating temperature range of TJ = –40°C to +125°C. 1.8V < VCC < 6.5V, R/RESET = 100kΩ to VCC, C/RESET = 50pF to GND, unless otherwise noted. Typical values are at TJ = +25°C. PARAMETER TEST CONDITIONS VVCC Input supply range IVCC VCC Supply current (current into VCC pin) VCC = 3.3V, RESET not asserted VCC = 6.5V, RESET not asserted Power-up Reset Voltage (1) VOL(max) = 0.2V, IRESET = 15µA TYP 1.
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TPS386596L33 SLVSA75 – JULY 2010 www.ti.com FUNCTIONAL BLOCK DIAGRAM VCC RESET MR Delay 50ms 3.3V SENSE1 + _ 400mV SENSE2 + _ 400mV SENSE3 + _ 400mV SENSE4 + _ 400mV GND Figure 2.
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TPS386596L33 www.ti.com SLVSA75 – JULY 2010 DEVICE INFORMATION PIN CONFIGURATION SENSE4 1 8 VCC SENSE3 2 7 /MR SENSE2 3 6 /RESET SENSE1 4 5 GND MSOP-8 PIN FUNCTIONS PIN DESCRIPTION NAME NO. SENSE1 4 Monitor voltage input for Supply 1 When the voltage at this terminal drops below the threshold voltage (VIT1= 2.9V), RESET is asserted. SENSE2 3 Monitor voltage input for Supply 2 When the voltage at this terminal drops below the threshold voltage (VIT2= 0.4V), RESET is asserted.
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TPS386596L33 SLVSA75 – JULY 2010 www.ti.com VCC 0.9 V t SENSE1 VHYS VIT t MR t RESET td td t Figure 3. Timing Diagram SENSE INPUTS The SENSEn inputs provide terminals at which the system voltages can be monitored. If the voltage at any one of the SENSEn pins drops below their respective VITn, then the RESET output is asserted. The comparators have a built-in hysteresis to ensure smooth RESETtransitions.
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TPS386596L33 www.ti.com VIN SLVSA75 – JULY 2010 DC-DC LDO DC-DC LDO Sub CPU MSP430 DC-DC LDO VCC __ RSH4 RSH3 RP MR RSH2 DC-DC LDO 3.3V SENSE2 VCC1 ____ ____ TPS386596 RESET RESET SENSE1 SENSE3 VCC2 VCC3 VCC4 DSP CPU FPGA SENSE4 GND RSL4 RSL3 RSL2 Figure 4. Typical TPS386596L33 Application Diagram MANUAL RESET The manual reset MR input allows external logic signal from processors, other logic circuits, and/or discrete sensors to initiate a reset.
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TPS386596L33 SLVSA75 – JULY 2010 www.ti.com PARAMETRIC MEASUREMENT INFORMATION TEST CONDITION SENSE2,3,4 Voltage (V) X1 = (Z1/0.4) *100 (%) X2 = (Z2/0.4) *100 (%) Y1 Z1 Y2 Z2 X1 and X2 are overdrive (%) values calculated from actual SENSE2,3,4 voltage amplitudes measured as Z1 and Z2. YN is the minimum pulse width that gives / RESET transition. Greater ZN produces shorter YN TIME Figure 5.
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TPS386596L33 www.ti.com SLVSA75 – JULY 2010 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, and VCC = 3.3V, unless otherwise noted. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS386596L33DGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 TPS386596L33DGKT VSSOP DGK 8 250 180.0 12.4 5.3 3.3 1.3 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS386596L33DGKR VSSOP DGK 8 2500 370.0 355.0 55.0 TPS386596L33DGKT VSSOP DGK 8 250 195.0 200.0 45.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.