User’s Guide TPS40009-Based, 5-A Converter in Less Than One Square Inch User’s Guide
EVM IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not considered by TI to be fit for commercial use.
DYNAMIC WARNINGS AND RESTRICTIONS It is important to operate this EVM within the input voltage range of 0 V to 5.5 V. Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions concerning the input range, please contact a TI field representative prior to connecting the input power. Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM.
SLUU189 − July 2004 TPS40009-Based 5-A Converter in Less Than One Square Inch Mark Dennis Systems Power Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . .
SLUU189 − July 2004 Schematic + 3 Figure 1.
SLUU189 − July 2004 4 Design Procedure 4.1 Controller Selection The TPS40009 synchronous buck controller is selected for this small size application because the 600-kHz switching frequency enables the selection of minimally sized filter components. The TPS40007 is available for applications needing 300-kHz operation for designs where efficiency is to be optimized. 4.
SLUU189 − July 2004 4.4 Output Capacitor Selection Selection of the output capacitor is based on many application variables, including function, cost, size, and availability. The minimum allowable output capacitance is determined by the amount of inductor ripple current and the allowable output ripple in equation (3). C OUT(min) + I RIPPLE 8 f V RIPPLE + 1.25 A + 22 mF 600 kHz 12 mV 8 (3) In this design, COUT(min) is 22 µF with VRIPPLE = 12 mV to allow for some margin.
SLUU189 − July 2004 4.7 Compensation Design The TPS40009 uses voltage mode control in conjunction with a high frequency error amplifier. For the fastest transient response, the loop crossover frequency is set at 1/10 fS, or 60 kHz. The power circuit L-C double pole corner frequency fC is situated at 24 kHz, and the output capacitor ESR zero is far higher at approximately 1MHz. The feedback compensation network is implemented to provide two zeroes and three poles.
SLUU189 − July 2004 Figure 2 shows the plots for the closed loop gain and phase with VIN = 3.3 V and IOUT = 4.4 A. At the crossover frequency of 60 kHz the phase margin is approximately 51 degrees. GAIN AND PHASE MARGIN vs FREQUENCY 150 40 30 Phase 100 Gain − db 50 10 0 0 −10 Phase − degrees 20 −50 Gain −20 −30 −100 ILOAD = 4.4 A VI = 3.3 V −150 −40 100 1000 10000 100000 1000000 Frequency − Hz Figure 2. 4.
SLUU189 − July 2004 5 PowerPAD Packaging The TPS4000X family is available in the DGQ version of TI’s PowerPAD thermally enhanced package. In the PowerPAD, a thermally conductive epoxy is used to attach the integrated circuit die to the leadframe die pad, which is exposed on the bottom of the completed package. The leadframe die pad can be soldered to the PCB using standard solder flow techniques when maximum heat dissipation is required.
SLUU189 − July 2004 6 Test Results/Performance Data The test setup is shown in figure 4 DC Power Supply Input wires 18 gauge or larger short as feasible C IN DVM1 + CIN = 470 µF or larger, 6.3 V or higher, low ESR AIEA or OSCON capacitor. Place within 2 inches of J1. (−) (+) J1 TP2 TP1 GND VIN TP3 SCOPE TP5 HPA069 GND TP6 VOUT J2 DVM2 TP4 (+) (−) Output wires 18 gauge or larger short as feasible Resistive load: 0.5 Ω, ≥ 5 W Active Load: set for 2.4 A (−) LOAD (+) Figure 4.
SLUU189 − July 2004 Typical efficiency curves are shown in Figure 5 for an input of 3.3 V. EFFICIENCY vs OUTPUT CURRENT 100 95 Efficiency − % 90 85 80 75 70 65 60 55 50 0 1 2 3 4 5 6 IOUT − Output Current − A Figure 5. Figure 6 shows the switch node during typical operation at full load. Note that there is very minimal body diode conduction in the bottom MOSFET. This is a result of using the predictive delay control implementation.
SLUU189 − July 2004 Circuit operation with an output short circuit is shown in Figure 7. After each restart into a short circuit the pulses terminate for a period of approximately 6 ms. This causes the input power to collapse to minuscule levels, and the circuit is protected. SHORT CIRCUIT OPERATION 2 V/div t − Time − 1 ms/div Figure 7. Figure 8 shows the output voltage ripple which is approximately half the 24-mV limit. OUTPUT VOLTAGE RIPPLE 10 mV/div t − Time − 500 ns/div Figure 8.
SLUU189 − July 2004 Figure 9 shows the startup waveforms with an input voltage of 3.3 V and a load of 0.3 Ω. Note that the output is held low until VSS (pin 4) goes above 0.12 V, and then the output comes up smoothly under closed loop softstart control. STARTUP WAVEFORM 1 V/div 500 mV/div 500 mV/div t − Time − 200 µs/div Figure 9. Figure 10 shows the transient response for a fast load step from 1 A to 2 A. TRANSIENT RESPONSE 50 mV/div t − Time − 20 µs/div Figure 10.
SLUU189 − July 2004 7 PCB Layout Figures 11 through13 show the top copper layer, the bottom copper layer, and top assembly layer, of HPA069.
SLUU189 − July 2004 8 List of Material Table 1 lists the components used in this design. With minor component tweaks this design could be modified to meet a wide range of applications. Reference Capacitor Terminal Block 16 Qty Description Manufacturer Part Number C1, C2, C5, C6 4 Ceramic, 22 µF, 6.3 V, X5R, 20%, 1210 Panasonic ECJ−4YB0J226M C10 1 Ceramic, 0.001 µF, 10 V, X5R, 10%, 805 Panasonic ECJ−2YB1A105K C11 1 Ceramic, 0.
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