Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - voltage regulators - DC DC switch controllers HTSSOP 16

KFF

BP5

SGND

VIN

HDRV

BP10

SYNC

ILIM

TPS4005xPWP

SS/SD

VFB

COMP

14BOOST

LDRV

PGND 9

–

UDG-03179

TPS40054

TPS40055

TPS40057

www.ti.com

SLUS593H –DECEMBER 2003–REVISED JULY 2012

WIDE-INPUT SYNCHRONOUS BUCK CONTROLLER

Check for Samples: TPS40054, TPS40055, TPS40057

FEATURES

CONTENTS

• Operating Input Voltage 8 V to 40 V

Device Ratings 2

• Input Voltage Feed-Forward Compensation

Electrical Characteristics 3

• < 1 % Internal 0.7-V Reference

Pin Descriptions 5

• Programmable Fixed-Frequency Up to 1-MHz

Voltage Mode Controller

Application Information 7

• Internal Gate Drive Outputs for High-Side and

Design Examples 22

Synchronous N-Channel MOSFETs

Additional References 27

• 16-Pin PowerPAD™ Package (θ

= 2°C/W)

• Thermal Shutdown

DESCRIPTION

The TPS4005x is a family of high-voltage, wide input

• Externally Synchronizable

(8 V to 40 V), synchronous, step-down controllers.

• Programmable High-Side Sense Short-Circuit

The TPS4005x family offers design flexibility with a

Protection

variety of user-programmable functions, including

• Programmable Closed-Loop Soft-Start

soft-start, UVLO, operating frequency, voltage feed-

forward, high-side current limit, and loop

• TPS40054 Source Only

compensation.

• TPS40055 Source/Sink

The TPS4005x uses voltage feed-forward control

• TPS40057 Source/Sink With V

Prebias

techniques to provide good line regulation over the

wide (4:1) input voltage range, and fast response to

APPLICATIONS

input line transients. Near-constant modulator gain

• Power Modules

with input variation eases loop compensation. The

externally programmable current limit provides pulse-

• Networking/Telecom

by-pulse current limit, as well as hiccup mode

• Industrial/Servers

operation utilizing an internal fault counter for longer

duration overloads.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (36 pages)

PAGE 1
TPS40054 TPS40055 TPS40057 8 www.ti.com SLUS593H – DECEMBER 2003 – REVISED JULY 2012 WIDE-INPUT SYNCHRONOUS BUCK CONTROLLER Check for Samples: TPS40054, TPS40055, TPS40057 FEATURES CONTENTS 1 • • • • 2 • • • • • • • • • Operating Input Voltage 8 V to 40 V Input Voltage Feed-Forward Compensation < 1 % Internal 0.
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TPS40054 TPS40055 TPS40057 SLUS593H – DECEMBER 2003 – REVISED JULY 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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TPS40054 TPS40055 TPS40057 www.ti.com SLUS593H – DECEMBER 2003 – REVISED JULY 2012 ELECTRICAL CHARACTERISTICS TA = –40°C to 85°C, VIN = 24 Vdc, RT = 90.9 kΩ, IKFF = 150 µA, fSW = 500 kHz, all parameters at zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT SUPPLY VIN Input voltage range, VIN 8 40 V 1.5 3.0 mA OPERATING CURRENT IDD Quiescent current Output drivers not switching, VFB ≥ 0.75 V Output voltage IO ≤ 1 mA 4.7 5.0 5.
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TPS40054 TPS40055 TPS40057 SLUS593H – DECEMBER 2003 – REVISED JULY 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) TA = –40°C to 85°C, VIN = 24 Vdc, RT = 90.9 kΩ, IKFF = 150 µA, fSW = 500 kHz, all parameters at zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 8.5 10.0 11.5 µA CURRENT LIMIT ISINK Current limit sink current VILIM = 23.7 V, VSW = (VILIM – 0.5 V) Propagation delay to output VILIM = 23.
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TPS40054 TPS40055 TPS40057 www.ti.com SLUS593H – DECEMBER 2003 – REVISED JULY 2012 Table 1. PIN DESCRIPTIONS TERMINAL I/O DESCRIPTION NAME NO. BOOST 14 O Gate drive voltage for the high side N-channel MOSFET. The BOOST voltage is 9 V greater than the SW voltage. A 0.1-µF ceramic capacitor should be connected from this pin to the drain of the lower MOSFET. BP5 3 O 5-V reference. This pin should be bypassed to ground with a 0.1-µF ceramic capacitor.
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TPS40054 TPS40055 TPS40057 SLUS593H – DECEMBER 2003 – REVISED JULY 2012 www.ti.
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TPS40054 TPS40055 TPS40057 www.ti.com SLUS593H – DECEMBER 2003 – REVISED JULY 2012 APPLICATION INFORMATION The TPS40054/55/57 family of devices allows the user to optimize the PWM controller to the specific application. The TPS40057 is safe for pre-biased outputs, not turning on the synchronous rectifier until the high-side FET has already started switching.
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TPS40054 TPS40055 TPS40057 SLUS593H – DECEMBER 2003 – REVISED JULY 2012 • www.ti.com VKFF is the voltage at the KFF pin (typical value is 3.48 V) (2) The curve showing the RKFF required for a given switching frequency, fSW, and VUVLO is shown in Figure 3. For low-input voltage and high duty-cycle applications, the voltage feed-forward may limit the duty cycle prematurely. This does not occur for most applications. The voltage control loop controls the duty cycle and regulates the output voltage.
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TPS40054 TPS40055 TPS40057 www.ti.com SLUS593H – DECEMBER 2003 – REVISED JULY 2012 UVLO Threshold VIN Clock PWM RAMP 1 2 3 4 5 6 7 1 2 1 2 3 4 5 6 7 PowerGood UDG-02132 Figure 4. Undervoltage Lockout Operation The tolerance on the UVLO set point also affects the maximum duty cycle achievable. If the UVLO starts the device at 10% below the nominal start-up voltage, the maximum duty cycle is reduced approximately 10% at the nominal start-up voltage.
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TPS40054 TPS40055 TPS40057 SLUS593H – DECEMBER 2003 – REVISED JULY 2012 www.ti.com Some applications may require an additional circuit to prevent false restarts at the UVLO voltage level. This applies to applications which have high impedance on the input voltage line or which have excessive ringing on the VIN line. The input voltage impedance can cause the input voltage to sag enough at start up to cause a UVLO shutdown and subsequent restart.
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TPS40054 TPS40055 TPS40057 www.ti.com SLUS593H – DECEMBER 2003 – REVISED JULY 2012 BP5 AND BP10 INTERNAL VOLTAGE REGULATORS Start-up characteristics of the BP5 and BP10 regulators over different temperature ranges are shown in Figure 7 and Figure 8. Slight variations in the BP5 occurs dependent upon the switching frequency. Variation in the BP10 regulation characteristics is also based on the load presented by switching the external MOSFETs.
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TPS40054 TPS40055 TPS40057 SLUS593H – DECEMBER 2003 – REVISED JULY 2012 www.ti.com CALCULATING THE OUTPUT CAPACITANCE The output capacitance depends on the output ripple voltage requirement, output ripple current, as well as any output voltage deviation requirement during a load transient. The output ripple voltage is a function of both the output capacitance and capacitor ESR. The worst-case output ripple is described in Equation 6.
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TPS40054 TPS40055 TPS40057 www.ti.com SLUS593H – DECEMBER 2003 – REVISED JULY 2012 PROGRAMMING SOFT START The TPS4005x uses a closed-loop soft-start system to ensure a controlled ramp of the output during startup. The reference voltage used for the startup is derived in the following manner. A capacitor (CSS/SD) is connected to the SS/SD pin. There is a ramped voltage generated at this pin by charging CSS/SD with a current source. A value of 0.
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TPS40054 TPS40055 TPS40057 SLUS593H – DECEMBER 2003 – REVISED JULY 2012 www.ti.com PROGRAMMING CURRENT LIMIT The TPS4005x uses a two-tier approach for overcurrent protection. The first tier is a pulse-by-pulse protection scheme. Current limit is implemented on the high-side MOSFET by sensing the voltage drop across the MOSFET when the gate is driven high. The MOSFET voltage is compared to the voltage dropped across a resistor connected from VIN pin to the ILIM pin when driven by a constant current sink.
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TPS40054 TPS40055 TPS40057 www.ti.com SLUS593H – DECEMBER 2003 – REVISED JULY 2012 The current limit programming resistor (RILIM) is calculated using Equation 15. Care must be taken in choosing the values used for VOS and ISINK in the equation. In order to ensure the output current at the overcurrent level, the minimum value of ISINK and the maximum value of VOS must be used. The main purpose is hard fault protection of the power switches. RILIM = IOC ´ RDS(on )émax ù + VOS ë û 1.12 ´ ISINK + 42.
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TPS40054 TPS40055 TPS40057 SLUS593H – DECEMBER 2003 – REVISED JULY 2012 www.ti.com For the TPS4005x, with VIN(min) being the minimum input voltage required to cause the ramp excursion to reach the maximum ramp amplitude of VRAMP, the modulator dc gain is shown in Equation 19. æ VIN(min ) ö æ VIN(min ) ö ÷ or AMOD dB = 20 ´ log ç ÷ AMOD = ç ( ) ç VRAMP ÷ ç VRAMP ÷ è ø è ø (19) Calculate the Poles and Zeros For a buck converter using voltage mode control there is a double pole due to the output L-CO.
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TPS40054 TPS40055 TPS40057 www.ti.com SLUS593H – DECEMBER 2003 – REVISED JULY 2012 A Type III topology, shown in Figure 12, has two zero-pole pairs in addition to a pole at the origin. The gain and phase boost of a Type III topology is shown in Figure 13. The two zeros are used to compensate the L-CO double pole and provide phase boost. The double pole is used to compensate for the ESR zero and provide controlled gain roll-off.
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TPS40054 TPS40055 TPS40057 SLUS593H – DECEMBER 2003 – REVISED JULY 2012 www.ti.com Minimum Load Resistance Care must be taken not to load down the output of the error amplifier with the feedback resistor, R2, that is too small. The error amplifier has a finite output source and sink current which must be considered when sizing R2. Too small a value does not allow the output to swing over its full range. VC (max) R2 (MIN) + + 3.
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TPS40054 TPS40055 TPS40057 www.ti.com SLUS593H – DECEMBER 2003 – REVISED JULY 2012 HIGH-SIDE MOSFET POWER DISSIPATION The power dissipated in the external high-side MOSFET is comprised of conduction and switching losses. The conduction losses are a function of the IRMS current through the MOSFET and the RDS(on) of the MOSFET. The high-side MOSFET conduction losses are defined by Equation 33.
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TPS40054 TPS40055 TPS40057 SLUS593H – DECEMBER 2003 – REVISED JULY 2012 www.ti.com SYNCHRONOUS RECTIFIER MOSFET POWER DISSIPATION The power dissipated in the synchronous rectifier MOSFET is comprised of three components: RDS(on) conduction losses, body diode conduction losses, and reverse recovery losses. RDS(on) conduction losses can be defined using Equation 31 and the RMS current through the synchronous rectifier MOSFET is described in Equation 37.
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TPS40054 TPS40055 TPS40057 www.ti.com æ æ (T - TA ) ö çç J ÷ - IQ ç çè qJA ´ VIN ÷ø fSW = ç 2 ´ Qg ç ç è SLUS593H – DECEMBER 2003 – REVISED JULY 2012 ö ÷ ÷ ÷ ÷ ÷ ø (Hz ) (46) LAYOUT CONSIDERATIONS MOSFET PACKAGING MOSFET package selection depends on MOSFET power dissipation and the projected operating conditions. In general, for a surface-mount applications, the DPAK style package provides the lowest thermal impedance (θJA) and, therefore, the highest power dissipation capability.
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TPS40054 TPS40055 TPS40057 SLUS593H – DECEMBER 2003 – REVISED JULY 2012 www.ti.com DESIGN EXAMPLE • • • • • • • Input voltage: 10 Vdc to 24 Vdc Output voltage: 3.3 V ±2% (3.234 ≤ VO ≤ 3.366) Output current: 8 A (maximum, steady state), 10 A (surge, 10 ms duration, 10% duty cycle maximum) Output ripple: 33 mVPP at 8 A Output load response: 0.3 V ≥ 10% to 90% step load change, from 1 A to 7 A Operating temperature: -40°C to 85°C fSW = 300 kHz 1.
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TPS40054 TPS40055 TPS40057 www.ti.com SLUS593H – DECEMBER 2003 – REVISED JULY 2012 5. Calculate synchronous rectifier losses The synchronous rectifier MOSFET has two (2) loss components, conduction, and diode reverse recovery losses. The conduction losses are due to IRMS losses as well as body diode conduction losses during the dead time associated with the anti-cross conduction delay. The IRMS current through the synchronous rectifier from Equation 37: Ǹ1 * d + 8 Ǹ1 * 0.135 + 7.
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TPS40054 TPS40055 TPS40057 SLUS593H – DECEMBER 2003 – REVISED JULY 2012 www.ti.com Using Equation 6 calculate the ESR required to meet the output ripple requirements. æ æ öö 1 33mV = 3.2 A ç ESR + ç ÷ ÷÷ ç è 8 ´ 97 mF ´ 300kHz ø ø è (65) ESR = 10.3mW - 4.3mW = 6.0mW (66) For this design example two (2) Panasonic SP EEFUEOJ1B1R capacitors, (6.3 V, 180 µF, 12 mΩ) are used. 10. Calculate the soft-start capacitor (CSS/SD) This design requires a soft-start time (tSTART) of 1 ms.
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TPS40054 TPS40055 TPS40057 www.ti.com SLUS593H – DECEMBER 2003 – REVISED JULY 2012 Choose R1 = 100 kΩ The poles and zeros for a type III network are described in Equation 24 through Equation 28. 1 1 f Z2 + N C3 + + 323 pF, choose 330 pF 2p R1 C3 2p 100 kW 4.93 kHz 1 1 f P2 + N R3 + + 6.55 kW, choose 6.49 kW 2p R3 C3 2p 330 pF 73.3 kHz 1 1 fC + N C2 + + 24.2 pF, choose 22 pF 2p R1 C2 G 2p 100 kW 3.29 20 kHz 1 1 f P1 + N R2 + + 98.2 kW, choose 97.6 kW 2p R2 C2 2p 22 pF 73.
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TPS40054 TPS40055 TPS40057 SLUS593H – DECEMBER 2003 – REVISED JULY 2012 www.ti.com + 330 mF 330 mF VIN RKFF 71.5 kW TPS4005xPWP – 18.7 kW 1 KFF ILIM 16 2 RT VIN 15 3 BP5 4 SYNC RT 169 kW 0.1 mF 100 pF 1.0 mF BOOST 14 22 mF 50 V 22 mF 50 V 1.0 mF 1.0 kW HDRV 13 Si7860 CSS/SD 3300 pF C1 330 pF R2 97.6 kW 5 SGND SW 12 6 SS/SD BP10 11 7 VFB LDRV 10 8 COMP C2 22 pF PGND 9 2.9 mH + R3 6.49 kW 180 mF R1 100 kW *optional Si7860 180 mF VO C3 330 pF – 1.
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TPS40054 TPS40055 TPS40057 www.ti.com SLUS593H – DECEMBER 2003 – REVISED JULY 2012 ADDITIONAL REFERENCES RELATED DEVICES The following devices have characteristics similar to the TPS40054/5/7 and may be of interest. Table 2. RELATED DEVICES DEVICE TPS40055-EP DESCRIPTION Enhanced performance TPS40055. TPS40054-Q1 TPS40057-Q1 Automotive qualified versions of the TPS5005x series. TPS40055-Q1 TPS40192 TPS40193 TPS40200 4.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) TPS40054PWPR HTSSOP PWP 16 2000 330.0 12.4 TPS40055PWPR HTSSOP PWP 16 2000 330.0 TPS40057PWPR HTSSOP PWP 16 2000 330.0 6.9 5.6 1.6 8.0 12.0 Q1 12.4 6.9 5.6 1.6 8.0 12.0 Q1 12.4 6.9 5.6 1.6 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS40054PWPR HTSSOP PWP 16 2000 367.0 367.0 35.0 TPS40055PWPR HTSSOP PWP 16 2000 367.0 367.0 35.0 TPS40057PWPR HTSSOP PWP 16 2000 367.0 367.0 35.
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