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SLVS612 − APRIL 2006

  

 

www.ti.com

FEATURES

Operating Input Voltage 10 V to 40 V

D Output Voltage Tracks External Reference

D Programmable Fixed-Frequency Up to

100 kHz to 1 MHz Voltage Mode Controller

D Internal Gate Drive Outputs for High-Side

and Synchronous N-Channel MOSFETs

D Externally Synchronizable

D Programmable Short-Circuit Protection

D Thermal Shutdown

D 16-Pin PowerPADt Package (θ

= 2°C/W)

D Programmable Closed-Loop Soft-Start

APPLICATIONS

DDR Tracking Regulators

D Power Modules

D Networking Equipment

D Industrial Servers

CONTENTS

Device Ratings 2

Electrical Characteristics 3

Terminal Information 5

Application Information 7

Design Example 22

Additional References 29

DESCRIPTION

The TPS40056 is part of a family of high-voltage,

wide input, synchronous, step-down converters.

The TPS40056 offers design flexibility with a

variety of user programmable functions, including

soft-start, operating frequency, high-side current

limit, and loop compensation. The TPS40056 is

also synchronizable to an external supply. It

incorporates MOSFET gate drivers for external

N-channel high-side and synchronous rectifier

(SR) MOSFETs. Gate drive logic incorporates

anti-cross conduction circuitry to prevent

simultaneous high-side and synchronous rectifier

conduction. The externally programmable short

circuit protection provides pulse-by-pulse current

limit, as well as hiccup mode operation utilizing an

internal fault counter for longer duration

overloads.

SIMPLIFIED APPLICATION DIAGRAM

TRKIN

UDG−03080

SYNC

BP5

SGND

VIN

HDRV

BP10

4 EA_REF

ILIM

TPS40056PWP

6SS

7 VFB

8 COMP

14BOOST

LDRV

PGND

−

PAD

−

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Summary of content (33 pages)

PAGE 1
8 SLVS612 − APRIL 2006 FEATURES D Operating Input Voltage 10 V to 40 V D Output Voltage Tracks External Reference D Programmable Fixed-Frequency Up to D D D D D D CONTENTS Device Ratings Electrical Characteristics Terminal Information Application Information Design Example Additional References 100 kHz to 1 MHz Voltage Mode Controller Internal Gate Drive Outputs for High-Side and Synchronous N-Channel MOSFETs Externally Synchronizable Programmable Sh
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SLVS612 − APRIL 2006 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION TA −40°C to 85°C PACKAGE PART NUMBER Plastic HTSSOP(PWP)(1) TPS40056PWP (1) The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS40056PWPR).
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SLVS612 − APRIL 2006 ELECTRICAL CHARACTERISTICS TA = −40°C to 85°C, VIN = 12 Vdc, RT = 90.9 kΩ, fSW = 500 kHz, VEA_REF = 1.25 V, all parameters at zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT SUPPLY VIN Input voltage range, VIN OPERATING CURRENT IDD Quiescent current 10 Output drivers not switching, VFB = 1.3 V 40 V 1.5 3.0 mA BP5 VBP5 Ouput voltage OSCILLATOR/RAMP GENERATOR ILOAD = 1 mA 4.5 5.0 5.
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SLVS612 − APRIL 2006 ELECTRICAL CHARACTERISTICS TA = −40°C to 85°C, VIN = 12 Vdc, RT = 90.9 kΩ, fSW = 500 kHz, VEA_REF = 1.25 V all parameters at zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 10 12 UNIT CURRENT LIMIT ISINK Current limit sink current Propagation delay to output tON tOFF VOS 8 VILIM = 11.7 V, VSW = (VILIM − 0.5 V) VILIM = 11.
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SLVS612 − APRIL 2006 TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION BOOST 14 O Gate drive voltage for the high side N-channel MOSFET. The BOOST voltage is 9 V greater than the input voltage. A 0.1-µF ceramic capacitor should be connected from this pin to the SW pin. BP5 3 O 5-V reference. This pin should be bypassed to ground with a 0.1-µF ceramic capacitor. This pin may be used with an external dc load of 1 mA or less.
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SLVS612 − APRIL 2006 FUNCTIONAL BLOCK DIAGRAM ILIM 16 BP10 VIN 15 RT 2 SYNC 1 RAMP 10 V Regulator BP5 7 Reference Voltages COMP 8 0.7 VREF 7 1.5 VREF 7 7 CL 3−Bit Up/Down Fault Counter N−channel Driver Restart Fault 12 SW + + + 0.7 V 7 Fault 7 SS/SD 6 7 7 13 HDRV 7 3.5 VREF 7 BP5 7 CLK 7 7 EA_REF 4 VFB 7 BP10 14 BOOST + Clock Oscillator 1.5 VREF 7 BP5 3 11 S BP10 7 Q CL R Q + 0.7 VREF N−channel Driver CLK 7 10 LDRV 9 PGND Restart 5 SGND 6 www.ti.
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SLVS612 − APRIL 2006 APPLICATION INFORMATION The TPS40056 allows the user to optimize the PWM controller to the specific application. The TPS40056 is the controller of choice for synchronous buck designs, the output of which is required to track another voltage. It has two quadrant operation and can source or sink output current, providing the best transient response.
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SLVS612 − APRIL 2006 TPS40056PWP R4 4 EA_REF VTRKIN R5 5 SGND HDRV 13 + VOUT SW 12 R3 6 SS BP10 11 7 VFB LDRV 10 8 COMP PGND 9 R1 − R6 UDG−06020 Figure 1.
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SLVS612 − APRIL 2006 APPLICATION INFORMATION BP5 AND BP10 INTERNAL VOLTAGE REGULATORS Start-up characteristics of the BP5 and BP10 regulators are shown in Figure 2. Slight variations in the BP5 occurs dependent upon the switching frequency. Variation in the BP10 regulation characteristics is also based on the load presented by switching the external MOSFETs.
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SLVS612 − APRIL 2006 APPLICATION INFORMATION Stepping the load from a heavy load to a light load results in an output overshoot. Excess energy stored in the inductor must be absorbed by the output capacitance. The energy stored in the inductor is described in equation (5).
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SLVS612 − APRIL 2006 APPLICATION INFORMATION PROGRAMMING SOFT START TPS40056 uses a closed-loop approach to ensure a controlled ramp on the output during start-up. Soft-start is programmed by charging an external capacitor (CSS) via an internally generated current source. The voltage on CSS is fed into a separate non-inverting input to the error amplifier (in addition to FB and EA_REF). The loop is closed on the lower of the CSS voltage or the the external reference voltage EA_REF.
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SLVS612 − APRIL 2006 APPLICATION INFORMATION The current limit programming resistor (RILIM) is calculated using equation (13). Care must be taken in choosing the values used for VOS and ISINK in the equation. In order to ensure the output current at the overcurrent level, the minimum value of ISINK and the maximum value of VOS must be used. R ILIM + I OC R DS(on)[max] I SINK ) V OS I SINK (W) (13) where: D ISINK is the current into the ILIM pin and is 8.
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SLVS612 − APRIL 2006 APPLICATION INFORMATION LOOP COMPENSATION Voltage-mode buck-type converters are typically compensated using Type III networks. Since the TPS40056 includes no voltage feedforward control, the gain of the PWM modulator must be included. The modulator gain is described in Figure 5. A MOD + V IN VS A MOD(dB) + 20 or log ǒ Ǔ V IN VS (14) Duty dycle, D, varies from 0 to 1 as the control voltage, VC, varies from the minimum ramp voltage to the maximum ramp voltage, VS.
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SLVS612 − APRIL 2006 APPLICATION INFORMATION MODULATOR GAIN vs SWITCHING FREQUENCY PWM MODULATOR RELATIONSHIPS ESR Zero, + 1 Modulator Gain − dB AMOD = VIN / VS VS VC Resultant, − 1 D = VC / VS LC Filter, − 2 100 1k 10 k 100 k fSW − Switching Frequency − Hz Figure 6 Figure 5 A Type III topology, shown in Figure 7, has two zero-pole pairs in addition to a pole at the origin. The gain and phase boost of a Type III topology is shown in Figure 8.
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SLVS612 − APRIL 2006 APPLICATION INFORMATION The poles and zeros for a type III network are described in equations (20). f Z1 + 2p 1 R2 C1 f P1 + 2p 1 R2 C2 (Hertz) f Z2 + 2p 1 R1 C3 (Hertz) f P2 + 2p 1 R3 C3 (Hertz) (20) (Hertz) The value of R1 is somewhat arbitraty, but influences other component values. A value between 50 kΩ and 100 kΩ usually yields reasonable values.
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SLVS612 − APRIL 2006 APPLICATION INFORMATION dv/dt Induced Turn−On MOSFETs are susceptible to dv/dt turn-on particularly in high-voltage (VDS) applications. The turn-on is caused by the capacitor divider that is formed by CGD and CGS. High dv/dt conditions and drain-to-source voltage, on the MOSFET causes current flow through CGD and causes the gate-to-source voltage to rise.
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SLVS612 − APRIL 2006 APPLICATION INFORMATION ID2 IO ID1 d } ∆I 1−d BODY DIODE CONDUCTION BODY DIODE CONDUCTION SW 0 ANTI−CROSS CONDUCTION SYNCHRONOUS RECTIFIER ON HIGH SIDE ON UDG−02139 Figure 9. Inductor Current and SW Node Waveforms The maximum allowable power dissipation in the MOSFET is determined by equation (29). PT + ǒT J * T AǓ q JA (Watts) (29) where: P T + P COND ) P SW(fsw) (Watts) (30) and θJA is the package thermal impedance.
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SLVS612 − APRIL 2006 APPLICATION INFORMATION The 2-multiplier is used because the body-diode conducts twice each cycle (once on the rising edge and once on the falling edge). The reverse recovery losses are due to the time it takes for the body diode to recovery from a forward bias to a reverse blocking state. The reverse recovery losses are described in equation (33). P RR + 0.
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SLVS612 − APRIL 2006 LAYOUT CONSIDERATIONS The PowerPADt package The PowerPAD package provides low thermal impedance for heat removal from the device. The PowerPAD derives its name and low thermal impedance from the large bonding pad on the bottom of the device. For maximum thermal performance, the circuit board must have an area of solder-tinned-copper underneath the package. The dimensions of this area depends on the size of the PowerPAD package.
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SLVS612 − APRIL 2006 LAYOUT CONSIDERATIONS Grounding and Circuit Layout Considerations The TPS4005x provides separate signal ground (SGND) and power ground (PGND) pins. It is important that circuit grounds are properly separated. Each ground should consist of a plane to minimize its impedance if possible.
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SLVS612 − APRIL 2006 DESIGN EXAMPLE D D D D D D D Input Voltage: 10 Vdc to 14.4 Vdc Output voltage: 1.25 V ±1% (1.2375 ≤ VO ≤1.2625) Output current: 8 A (maximum, steady state), 10 A (surge, 10ms duration, 10% duty cycle maximum) Output ripple: 33 mVP-P at 8 A Output load response: 0.1 V => 10% to 90% step load change, from 1 A to 7 A Operating temperature: −40°C to 85°C fSW=170 kHz 1. Calculate maximum and minimum duty cycles d MIN + V O(min) + 1.2375 + 0.086 14.
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SLVS612 − APRIL 2006 DESIGN EXAMPLE 4. Calculate the power losses Power losses in the high-side MOSFET (Si7860DP) at 14.4-VIN where switching losses dominate can be calculated from equation (27). I RMS + I O Ǹd + 8 Ǹ0.086 + 2.35 A (44) substituting (27) into (26) yields P COND + 2.35 2 (1 ) 0.007 0.008 (150 * 25)) + 0.083 W (45) and from equation (28), the switching losses can be determined. P SW(fsw) + ǒV IN t SWǓ IO f SW + 14.4 V 8A 20 ns 170 kHz + 0.
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SLVS612 − APRIL 2006 DESIGN EXAMPLE 6. Calculate the inductor value The inductor value is calculated from equation (3). L+ (14.4 * 1.25 V) 1.25 V + 2.1 mH 14.4 V 3.2 A 170 kHz (54) A 2.9-µH Coev DXM1306−2R9 or 2.6-µH Panasonic ETQ−P6F2R9LFA can be used. 7. Setting the switching frequency The clock frequency is set with a resistor (RT) from the RT pin to ground. The value of RT can be found from equation (1), with fSW in kHz. RT + ǒ f SW 1 17.
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SLVS612 − APRIL 2006 DESIGN EXAMPLE 10. Calculate the current limit resistor (RILIM) The current limit set point depends on tSTART, VO,CO and ILOAD at start-up as shown in equation (12). For this design, I LIM u 940 mF 1.25 V ) 8.0 A + 9.2 A 1 ms (60) For this design, set ILIM for 11.0 ADC minimum. From equation (13), with IOC equal to the DC output surge current plus one-half the ripple current of 3.2 A and RDS(on) is increased 30% (1.3 * 0.008) to allow for MOSFET heating. (0.03) R ILIM + 12.
PAGE 25
SLVS612 − APRIL 2006 DESIGN EXAMPLE The poles and zeros for a type III network are described in equations (20) and (21). f Z2 + 2p 1 R1 C3 f P2 + 2p 1 R3 C3 fC + 2p R1 C2 f P1 + 2p 1 R2 C2 f Z1 + 2p 1 R2 C1 N C3 + 2p 1 100 kW 3.05 kHz + 522 pF, choose 560 pF N R3 + 2p 1 560 pF 28.2 kHz + 10.08 kW, choose 10 kW 1 G N C2 + 1 2p 100 kW N R2 + 2p 1 10 pF N C1 + 2p 1 562 kW 7.14 28.2 kHz 20 kHz + 11.1 pF, choose 10 pF + 564 kW, choose 562 kW 3.05 kHz + 92.
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+ www.ti.com C1 10 pF 562 kΩ R2 C2 3300 pF PWP PGND COMP 8 9 LDRV 10 BP10 11 VFB SS 6 SW 12 HDRV 13 BOOST 14 VIN 15 ILIM 16 7 SGND 5 EA_REF BP5 3 4 RT SYNC TPS40056PWP 2 1 330 µF CSS 1.0 µF 165 kΩ RT 330 µF 100 pF R5 10 kΩ R4 10 kΩ VTRKIN − VIN D2 0.1 µF 1.0 µF 50 V 100 pF Si7860DP 3.3 Ω RSW Si7860DP 1.0 µF 11.8 kΩ D1 2.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS40056PWPR Package Package Pins Type Drawing SPQ HTSSOP 2000 PWP 16 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 12.4 Pack Materials-Page 1 6.9 B0 (mm) K0 (mm) P1 (mm) 5.6 1.6 8.0 W Pin1 (mm) Quadrant 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS40056PWPR HTSSOP PWP 16 2000 367.0 367.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.