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FEATURES APPLICATIONS

DESCRIPTION

TYPICAL APPLICATION

TPS40100

24 2223 21 20 19

7 98 10 11 12

COMP

TRKOUT

TRKIN

UVLO

ILIM

MGU

MGD

SYNC

ISNS

BIAS

GND

PGND

VDD

HDRV

BST

5VBP

LDRV

UDG−04137

TRKIN

TPS40100

SLUS601–MAY 2005

MIDRANGE INPUT SYNCHRONOUS BUCK CONTROLLER

WITH ADVANCED SEQUENCING AND OUTPUT MARGINING

• Servers

• Operation over 4.5 V to 18 V Input Range

• Networking Equipment

• Adjustable Frequency (Between 100 kHz and

• Cable Modems and Routers

600 kHz) Current Feedback Control

• XDSL Modems and Routers

• Output Voltage Range From 0.7 V to 5.5 V

• Set-Top Boxes

• Simultaneous, Ratiometric and Sequential

• Telecommunications Equipment

Startup Sequencing

• Power Supply Modules

• Adaptive Gate Drive

• Remote Sensing (Via Separate GND/PGND)

• Internal Gate Drivers for N-channel MOSFETs

The TPS40100 is a mid voltage, wide-input (between

• Internal 5-V Regulator

4.5 V and 18 V), synchronous, step-down controller.

• 24-Pin QFN Package

The TPS40100 offers programmable closed loop

soft-start, programmable UVLO (with programmable

• Thermal Shutdown

hysteresis), programmable inductor sensed current

• Programmable Overcurrent Protection

limit and can be synchronized to other timebases.

• Power Good Indicator

The TPS40100 incorporates MOSFET gate drivers

• 1%, 690-mV Reference

for external N-channel high-side and synchronous

rectifier (SR) MOSFET. Gate drive logic incorporates

• Output Margining, 3% and 5%

adaptive anti-cross conduction circuitry for improved

• Programmable UVLO (with Programmable

efficiency, reducing both cross conduction and diode

Hysteresis)

conduction in the rectifier MOSFET. The externally

• Frequency Synchronization

programmable current limit provides a hiccup

overcurrent recovery characteristic.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (39 pages)

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TPS40100 www.ti.com SLUS601 – MAY 2005 MIDRANGE INPUT SYNCHRONOUS BUCK CONTROLLER WITH ADVANCED SEQUENCING AND OUTPUT MARGINING FEATURES • • • • • • • • • • • • • • • • APPLICATIONS Operation over 4.5 V to 18 V Input Range Adjustable Frequency (Between 100 kHz and 600 kHz) Current Feedback Control Output Voltage Range From 0.7 V to 5.
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TPS40100 www.ti.com SLUS601 – MAY 2005 ORDERING INFORMATION (1) TA PACKAGE -40°C to 85°C QFN PART NUMBER (1) TPS40100RGER TPS40100RGET The QFN package (RGE) is available taped and reeled only. Use large reel device type R (TPS40100RGER) to order quantities of 3,000 per reel. Use small reel device type T (TPS40100RGET) to order quantities of 250 per reel. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) TPS40100 VIN Input voltage range VDD -0.
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TPS40100 www.ti.com SLUS601 – MAY 2005 ELECTRICAL CHARACTERISTICS -40°C ≤ TA = TJ≤ 85°C, VVDD = 12 V, RRT = 182 kΩ, RGM = 232 kΩ, RILIM = 121 kΩ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 18.0 V 2.5 mA INPUT VOLTAGE VVDD Operating range 4.5 OPERATING CURRENT IDD Quiescent current VFB > 0.8 V, 0% duty cycle ISD Shutdown current VUVLO < 1 V 1.3 1.8 500 µA 5VPB Internal regulator 7 V ≤ VVDD≤ 18 V, 0 mA ≤ ILOAD≤ 30 mA 4.7 5.0 5.3 4.
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TPS40100 www.ti.com SLUS601 – MAY 2005 ELECTRICAL CHARACTERISTICS (continued) -40°C ≤ TA = TJ≤ 85°C, VVDD = 12 V, RRT = 182 kΩ, RGM = 232 kΩ, RILIM = 121 kΩ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 7 25 40 -5 25 40 UNIT TRACKING AMPLIFIER VTRKOS Tracking amplifier input offset voltage VTRKCM Input common mode, active range VTRK VTRKOS = VTRKIN - VO ; VVO≤ 2 V VTRKOS = VTRKIN - VO ; 2 V < VVO≤ 6 V 4.5 V ≤ VVDD ≤ 5.
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TPS40100 www.ti.com SLUS601 – MAY 2005 DEVICE INFORMATION (continued) TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION 14 O Output of an internal 5-V regulator. A 1-µF bypass capacitor should be connected from this pin to PGND. Power for external circuitry may be drawn from this pin. The total gate drive current and external current draw should not cause the device to exceed thermal capabilities BIAS 8 O The bypassed supply for internal device circuitry. Connect a 0.
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TPS40100 www.ti.com SLUS601 – MAY 2005 FUNCTIONAL BLOCK DIAGRAM RT SYNC UVLO 7 22 5 TPS40100 Oscillator COMP 1 FB 2 1.33 V CLK MGD 23 16 HDRV 10 µA PWM 20 kΩ SS + + OC 0.725 V MGU 24 15 BST UVLO + Reference Select FAULT 0.711 V 0.690 V Adaptive Gate Drive and Prebias Control 17 SW 14 5VBP CLK 13 LDRV 0.669 V 0.655 V 12 PGND + + ISNS 19 OC 1.48 V + VO 20 Current Mirror 21 PG THERMSD + 1.
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TPS40100 www.ti.com SLUS601 – MAY 2005 APPLICATION INFORMATION Introduction The TPS40100 is a synchronous buck controller targeted at applications that require sequencing and output voltage margining features. This controller uses a current feedback mechanism to make loop compensation easier for loads that can have wide capacitance variations.
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TPS40100 www.ti.com SLUS601 – MAY 2005 APPLICATION INFORMATION (continued) TIMING RESISTOR vs SWITCHING FREQUENCY (250 kHz to 600 kHz) TIMING RESISTOR vs SWITCHING FREQUENCY (100 kHz to 350 kHz) 225 550 500 200 RT − Timing Resistance − kΩ RT − Timing Resistance − kΩ 450 175 150 125 100 75 400 350 300 250 200 150 50 250 300 350 400 450 500 550 600 100 100 fSW − Switching Frequency − kHz Figure 1. 150 200 250 300 350 f − Switching Frequency − kHz Figure 2.
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TPS40100 www.ti.com SLUS601 – MAY 2005 APPLICATION INFORMATION (continued) Calculating the Current Sense Filter Network The TPS 40100 gets current feedback information by sensing the voltage across the inductor resistance, RLDC. In order to do this, a filter must be constructed that allows the sensed voltage to be representative of the actual current in the inductor. This filter is a series R-C network connected across the inductor as shown in Figure 3.
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TPS40100 www.ti.com SLUS601 – MAY 2005 APPLICATION INFORMATION (continued) The relative resistance change in the inductor is given by: R REL(L) + 1 ) TC L ǒT L * T BASEǓ (dimensionless) (7) where • • • • RREL(L) is the relative resistance of the inductor at TL compared to the resistance at TBASE TCL is the temperature coefficient of copper, 4000 ppm/°C or 0.
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TPS40100 www.ti.com SLUS601 – MAY 2005 APPLICATION INFORMATION (continued) VO 20 ILIM 6 RILIM ISNS + −2000 ppm/°C 19 RTHE RF3 RF2 RNTC VIN CFLT RF1 L RLDG VOUT COUT UDG−04148 Figure 4. Compensation for Temperature Coefficient of the Inductor Resistance The first step is to determine an attenuation ratio α. This ratio should be near to 1 but not too close. If it is too close to 1, the circuit requires large impedances and thermistor values too high.
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TPS40100 www.ti.com SLUS601 – MAY 2005 APPLICATION INFORMATION (continued) RGM − Gain Setting Resistance − kΩ CURRENT SENSE AMPLIFIER GAIN SETTING RESISTANCE vs CURRENT SENSE AMPLIFIER GAIN 325 275 225 175 125 75 25 250 400 550 700 850 1000 gm − Sense Amplifier Transconductance − µS Figure 5. Control to Output Gain of the Converter A model that gives a good first order approximation to the control to output gain of a converter based on the TPS40100 controller is shown in Figure 6.
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TPS40100 www.ti.com SLUS601 – MAY 2005 APPLICATION INFORMATION (continued) Using either the analytical model or the simulated model, determine the control to output gain at the chosen loop crossover frequency.
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TPS40100 www.ti.com SLUS601 – MAY 2005 APPLICATION INFORMATION (continued) f P + fC fZ + 10 + fC + 10 2p 2p 1 R2 1 R2 C2 C1 (Hz) (32) (Hz) (33) Compensating the Loop (Type III) If the output capacitor does not have sufficient ESR to use the phase shift from the ESR zero, a Type III compensator is required. This is the case for most designs with ceramic output capacitors only. A series R-C circuit is added in parallel to R1 as shown in Figure 8.
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TPS40100 www.ti.
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TPS40100 www.ti.com SLUS601 – MAY 2005 APPLICATION INFORMATION (continued) Establishing Tracking and Designing a Tracking Control Loop The tracking startup feature of the TPS40100 is a separate control loop that controls the output voltage to a reference applied to the TRKIN pin. This reference voltage is typically a ramp generated by an external R-C circuit.
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TPS40100 www.ti.com SLUS601 – MAY 2005 APPLICATION INFORMATION (continued) Knowing the gain of the voltage loop looking into R4 and the desired tracking loop crossover frequency, R5 and C4 can be found: R4 R5 C4 + (s) 2 p R 1 f cTRK (44) where • fCTRK is the desired tracking loop crossover frequency The actual values of R5 and C4 are a balance between impedance level and component size. Any of a range of values is applicable. In general, R5 should be no more than 20% of R6, and less than 10 kΩ.
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TPS40100 www.ti.com SLUS601 – MAY 2005 APPLICATION INFORMATION (continued) + VIN X2 gmCSA L RLDC RSFLT CSFLT VOUT COUT RLOAD ISNS + RCESR C1 R2 R3 C2 REA 20 kΩ C3 R1 + RBIAS + + R4 C4 VX R5 + UDG−04147 Figure 13. AC Behavioral Model for Tracking Control Loop To use the model, the AC voltage source is swept over the frequency range of interest. The open loop ac response is VX/VOUT.
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TPS40100 www.ti.com SLUS601 – MAY 2005 APPLICATION INFORMATION (continued) COMP 1 FB 2 350 mV + + + COMP Error Amplifier 690 mV 20 µA SS 10 CSS CHARGE From UVLO circuits, Fault controller 5 µA UDG−04138 Figure 14. Error Amplifier and Soft-Start Functional Diagram UVLO (Internal Logic State) 4.8 V 3.5 V 1.04 V 0.35 V SS Tss Tss Delay VOUT PDG Figure 15.
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TPS40100 www.ti.com SLUS601 – MAY 2005 APPLICATION INFORMATION (continued) • • Disconnect the tracking amplifier output from the FB node (this is the recommended solution. The tracking amplifier can then be used for other system purposes if desired) Maintain the tracking amplifier output connection to the FB circuit - the reference to the tracking amplifier should be tied to VDD pin in this case.
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TPS40100 www.ti.com SLUS601 – MAY 2005 APPLICATION INFORMATION (continued) t RESTART + 3.3 C SS I SSDIS (s) (49) where • • • tRESTART is the initial restart time (s) CSS is soft start capacitance (F) ISSDIS is the soft start discharge current – 5 µA If the output fault is persistent, and an overcurrent is declared on the restart, both of the MOSFETs are turned off and the soft-start capacitor continues to charge to 3.5 V and then discharge to 200 mV before another restart is attempted.
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TPS40100 www.ti.com SLUS601 – MAY 2005 APPLICATION INFORMATION (continued) Voltage Margining The TPS40100 allows the user to make the output voltage temporarily be 3% above or below the nominal output, or 5% above or below the nominal output. This is accomplished by connecting the MGU or MGD pins to GND directly or through a resistance. See Table 1. Table 1.
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TPS40100 www.ti.com SLUS601 – MAY 2005 POWERGOOD VOLTAGE vs POWERGOOD CURRENT 2.5 VVDD = 0 V VPGD − Powergood Voltage − V 2.0 1.5 1.0 0.5 0 0 1 2 3 4 5 IPGD − Powergood Current − mA Figure 17. Pre-Bias Operation Some applications require that the converter not sink current during startup if a pre-existing voltage exists at the output. Since synchronous buck converters inherently sink current some method of overcoming this characteristic must be employed.
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TPS40100 www.ti.com SLUS601 – MAY 2005 Application Schematics Margin down 3% Power Good Indication 3.3 V to 5 V logic supply or 5VBP pin 27 kΩ Margin up 3% 2N7002 27 kΩ 2N7002 12 V 10 kΩ 1 COMP 2 FB 12 V ISNS PG 19 VDD 18 Si73444DP SW 17 TRKOUT MMBD1501A 200 kΩ 20 HDRV 16 TPS40100 47 nF 4 100 nF BST 15 TRKIN 4.99 kΩ BAT54 5 UVLO 5VBP 14 6 ILIM LDRV 13 VOUT 470 µF 1.2 V Panasonic 15 A EEF−SEOD471R 100 pF GND SS GM PGND 13.7 kΩ BIAS 1 µF 40.
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TPS40100 www.ti.com SLUS601 – MAY 2005 Margin down 5% Power Good Indication 3.3 V to 5 V logic supply or 5VBP pin Margin up 5% 2N7002 3.32 kΩ 12 V 330 pF 10 kΩ 1 COMP 2 FB 21 20 VO 22 19 12 V ISNS 6.2 kΩ 23 PG MGU 3.9 nF 24 SYNC 47 pF VOUT Connect at load MGD 2N7002 VDD 18 Si7344DP 5.9 kΩ 100 nF SW 17 1.0 µH COEV 15 kΩ 3 MMBD1501A 100 kΩ 200 kΩ TRKOUT TPS40100 47 nF VOUT 3.3 V 15 A DXM1306−1R0 HDRV 16 1.
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TPS40100 www.ti.com SLUS601 – MAY 2005 12 V 22 21 14.3 kΩ 1 COMP 2 FB 20 19 12 V ISNS 23 VO 24 PG NC SYNC NC MGU 300 pF NC MGD 47 pF 10 kΩ NC VDD 18 5.9 kΩ Si73444DP SW 17 200 kΩ NC 3 TRKOUT NC 4 TRKIN BST 15 5 UVLO 5VBP 14 1 µH COEV DXM1306−1R0 1.7 mΩ (typ) HDRV 16 TPS40100 100 nF 100 nF BAT54 470 µF Panasonic EEF−SEOD471R Si7868DP 100 pF GND SS GM PGND 13.7 kΩ BIAS 40.2 kΩ LDRV 13 ILIM RT 6 7 8 9 10 11 12 158 kΩ 1 1 µF VOUT 1.
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TPS40100 www.ti.com SLUS601 – MAY 2005 NC 22 21 1 COMP 2 FB 3 TRKOUT 20 19 VO PG 23 12 V ISNS 14.3 kΩ 12 V NC 24 SYNC 300 pF NC MGD 47 pF MGU 10 kΩ VDD 18 SW 17 1 µH COEV DXM1306−1R0 1.7 mΩ (typ) HDRV 16 TPS40100 NC 5.
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TPS40100 www.ti.com SLUS601 – MAY 2005 200 kΩ 22 21 20 1 COMP 2 FB 3 TRKOUT 19 External 5V 12 V ISNS 14.3 kΩ 23 PG 300 pF NC 24 VO 12 V NC SYNC 47 pF MGD 10 kΩ MGU 10 kΩ VDD 18 5.9 kΩ Si73444DP 100 nF SW 17 30 kΩ MMBD1501A 4.99 kΩ HDRV 16 TPS40100 47 nF 100 nF 4 TRKIN BST 15 5 UVLO 5VBP 14 BAT54 VOUT 1.2 V 15 A Si7868DP ILIM BIAS GND SS GM PGND 7 8 9 10 11 12 40.2 kΩ 13.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS40100RGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 TPS40100RGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 TPS40100RGER VQFN RGE 24 3000 330.0 12.4 4.3 4.3 1.1 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS40100RGER VQFN RGE 24 3000 367.0 367.0 35.0 TPS40100RGER VQFN RGE 24 3000 367.0 367.0 35.0 TPS40100RGER VQFN RGE 24 3000 370.0 355.0 55.0 TPS40100RGET VQFN RGE 24 250 210.0 185.0 35.0 TPS40100RGET VQFN RGE 24 250 195.0 200.0 45.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.