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TPS40170

www.ti.com

SLUS970A –MARCH 2011–REVISED NOVEMBER 2013

4.5-V TO 60-V WIDE-INPUT SYNCHRONOUS PWM BUCK CONTROLLER

Check for Samples: TPS40170

FEATURES

DESCRIPTION

TPS40170 is a full-featured, synchronous PWM buck

• Wide-Input Voltage Range from 4.5 V to 60 V

controller that operates at an input voltage between

• 600-mV Reference Voltage with 1% Accuracy

4.5 V and 60 V and is optimized for high- power-

• Programmable UVLO and Hysteresis

density, high-reliability DC/DC converter applications.

The controller implements voltage-mode control with

• Voltage Mode Control With Voltage Feed

input-voltage feed-forward compensation that enables

Forward

instant response to input voltage change. The

• Programmable Frequency Between 100 kHz

switching frequency is programmable from 100 kHz to

and 600 kHz

600 kHz.

• Bi-directional -Frequency Synchronization

The TPS40170 has a complete set of system

With Master/Slave Option

protection and monitoring features such as

• Low-side FET Sensing Overcurrent Protection

programmable UVLO, programmable overcurrent

and High-Side FET Sensing Short-Circuit

protection (OCP) by sensing the low-side FET,

selectable short-circuit protection (SCP) by sensing

Protection With Integrated Thermal

the high-side FET and thermal shutdown. The

Compensation

ENABLE pin allows for system shutdown in a low-

• Programmable Closed Loop Soft-Start

current (1-µA typical) mode. The controller supports

• Supports Pre-Biased Outputs

pre-biased output, provides an open-drain PGOOD

signal, and has closed loop soft-start, output voltage

• Thermal Shutdown at 165°C with Hysteresis

tracking and adaptive dead-time control.

• Voltage Tracking

TPS40170 provides accurate output voltage

• Power Good

regulation via 1% ensured accuracy. Additionally, the

• ENABLE with 1-µA Low-Current Shutdown

controller implements a novel scheme of bi-directional

• 8.0-V and 3.3-V LDO Output

synchronization with one controller acting as the

master and other downstream controllers acting as

• Integrated Bootstrap Diode

slaves synchronized to the master in-phase or 180°

• 20-Pin 3.5 mm × 4.5 mm QFN (RGY) Package

out-of-phase. Slave controllers can be synchronized

to an external clock within ±30% of the free running

APPLICATIONS

switching frequency.

• POL Modules

• Wide Input Voltage, High-Power Density

DC/DC Converters for Industrial, Networking

and Telecomm Equipment

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (50 pages)

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TPS40170 www.ti.com SLUS970A – MARCH 2011 – REVISED NOVEMBER 2013 4.5-V TO 60-V WIDE-INPUT SYNCHRONOUS PWM BUCK CONTROLLER Check for Samples: TPS40170 FEATURES DESCRIPTION • • • • TPS40170 is a full-featured, synchronous PWM buck controller that operates at an input voltage between 4.5 V and 60 V and is optimized for high- powerdensity, high-reliability DC/DC converter applications.
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TPS40170 SLUS970A – MARCH 2011 – REVISED NOVEMBER 2013 www.ti.com SIMPLIFIED APPLICATION VIN 1 20 ENABLE UVLO 2 SYNC 3 M/S BOOT 18 4 RT HDRV 17 5 SS SW 16 VIN 19 VOUT TPS40170 6 TRK 7 FB 8 COMP 9 AGND VBP 15 LDRV 14 PGND 13 ILIM 12 VDD PGOOD 10 11 UDG-09219 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions.
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TPS40170 www.ti.com SLUS970A – MARCH 2011 – REVISED NOVEMBER 2013 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) VALUE Input voltage MIN MAX VIN –0.3 62 M/S –0.3 VIN UVLO –0.3 16 SW –5 VVIN SW (for duration less than 200 ns), -10 BOOT Output voltage Electrostatic discharge (ESD) UNIT V VVIN VSW + 8.8 HDRV VSW BOOT BOOT-SW, HDRV-SW (differential from BOOT or HDRV to SW) –0.3 8.8 VBP, LDRV, COMP, RT, ENABLE, PGOOD, SYNC –0.3 8.
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TPS40170 SLUS970A – MARCH 2011 – REVISED NOVEMBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for -40ºC ≤ TJ ≤ 125ºC, VVIN=12 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 60 V 1 2.5 µA 4.5 mA 100 mV INPUT SUPPLY VVIN Input voltage range ISD Shutdown current VENABLE < 100 mV 4.
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TPS40170 www.ti.
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TPS40170 SLUS970A – MARCH 2011 – REVISED NOVEMBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Unless otherwise stated, these specifications apply for -40ºC ≤ TJ ≤ 125ºC, VVIN=12 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 155 165 175 °C 125 135 145 °C THERMAL SHUTDOWN TSD,set (3) Thermal shutdown set threshold TSD,reset (3) Thermal shutdown reset threshold Thyst (3) Thermal shutdown hysteresis 4.
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TPS40170 www.ti.com SLUS970A – MARCH 2011 – REVISED NOVEMBER 2013 DEVICE INFORMATION RGY PACKAGE QFN-20 (Top View) ENABLE UVLO 1 20 19 SYNC 2 M/S 3 18 BOOT RT 4 17 HDRV SS 5 16 SW VIN TPS40170 TRK 6 15 VBP FB 7 14 LDRV COMP 8 13 PGND AGND 9 10 VDD 11 12 ILIM PGOOD PIN FUNCTIONS PIN I/O DESCRIPTION NAME NO. AGND 9 — Analog signal ground. This pin must be electrically connected to power ground PGND externally.
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TPS40170 SLUS970A – MARCH 2011 – REVISED NOVEMBER 2013 www.ti.com PIN FUNCTIONS (continued) PIN NAME NO. I/O DESCRIPTION VBP 15 O 8-V regulated output for gate driver. A ceramic capacitor with a value between 1 µF and 10 µF must be connected from this pin to PGND VDD 10 O 3.3-V regulated output. A ceramic by-pass capacitor with a value between 0.1 µF and 1 µF must be connected between this pin and the AGND pin and placed closely to this pin.
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TPS40170 www.ti.com SLUS970A – MARCH 2011 – REVISED NOVEMBER 2013 TYPICAL CHARACTERISTICS 600.0 100.0 VIN = 4.5 V VIN = 24 V VIN = 60 V 99.5 Switching Frequency (kHz) Reference Voltage (mV) 599.8 599.5 599.2 599.0 598.8 99.0 98.5 98.0 97.5 97.0 96.5 96.0 95.5 598.5 −40 −25 −10 5 20 35 50 65 Temperature (°C) 80 95 fSW= 100 kHz 95.0 −40 −25 −10 5 20 35 50 65 80 Junction Temperature (°C) 110 125 Figure 1. Reference Voltage vs.
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TPS40170 SLUS970A – MARCH 2011 – REVISED NOVEMBER 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) 898.0 5.16 5.14 UVLO Hysteresis Current (µA) UVLO On Voltage (mV) 897.5 897.0 896.5 896.0 895.5 5.12 5.10 5.08 5.06 5.04 5.02 5.00 895.0 −40 −25 −10 5 20 35 50 65 80 Junction Temperature (°C) 95 4.98 −40 −25 −10 110 125 Figure 7. UVLO On Voltage vs. Junction Temperature VBP UVLO Hysteresis Voltage (mV) VBP Turn−On Voltage (V) 110 125 330 4.14 4.13 4.12 4.11 4.10 4.09 4.
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TPS40170 www.ti.com SLUS970A – MARCH 2011 – REVISED NOVEMBER 2013 680 10.8 674 Soft−Start Initial Offset Voltage (mV) ILIM Source Current (µA) TYPICAL CHARACTERISTICS (continued) 11.1 10.5 10.2 9.9 9.6 9.3 9.0 8.7 8.4 −40 −25 −10 5 20 35 50 65 80 Junction Temperature (°C) 95 110 125 Figure 13. ILIM Source Current vs. Junction Temperature 668 662 656 650 644 638 632 626 620 614 −40 −25 −10 5 20 35 50 65 80 Junction Temperature (°C) 95 110 125 Figure 14. Soft-Start Initial Offset Voltage vs.
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TPS40170 SLUS970A – MARCH 2011 – REVISED NOVEMBER 2013 www.ti.com APPLICATION INFORMATION FUNCTIONAL DESCRIPTION The TPS40170 is a synchronous PWM buck controller that accepts a wide range of input voltage from 4.5 V to 60 V and features voltage-mode control with input-voltage, feed-forward compensation. The switching frequency is programmable from 100 kHz to 600 kHz.
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TPS40170 www.ti.com SLUS970A – MARCH 2011 – REVISED NOVEMBER 2013 NOTE To avoid potential erroneous behavior of the enable function, the ENABLE signal applied must have a minimum slew rate of 20 V/s. Input Undervoltage Lockout (UVLO) The TPS40170 has both fixed and programmable input undervoltage lockout (UVLO).
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TPS40170 SLUS970A – MARCH 2011 – REVISED NOVEMBER 2013 www.ti.com Equations for Programming the Input UVLO: Components R1 and R2 represent external resistors for programming UVLO and hysteresis and can be calculated in Equation 1 and Equation 2 respectively. V - VOFF R1 = ON IUVLO (1) VUVLO R2 = R1 ´ (VON - VUVLO ) where • • • • VON is the desired turn-on voltage of the converter VOFF is the desired turn-off voltage for the converter IUVLO is the hysteresis current generated by the device, 5.
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TPS40170 www.ti.com SLUS970A – MARCH 2011 – REVISED NOVEMBER 2013 VIN Minimum OFF Time RAMP VCOMP VCLK PWM t – Time UDG-09200 Figure 18. Feed-Forward Oscillator Timing Diagram Calculating the Timing Resistance (RRT) æ 104 ö RRT = ç ÷ - 2 (kW ) ç fSW ÷ è ø where • • fSW is the switching frequency in kHz RRT is the resistor connected from RT pin to GND in kΩ (4) NOTE The switching frequency can be adjusted between 100 kHz and 600 kHz.
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TPS40170 SLUS970A – MARCH 2011 – REVISED NOVEMBER 2013 www.ti.com Overcurrent Protection and Short-Circuit Protection (OCP and SCP) The TPS40170 has the capability to set a two-level overcurrent protection. The first level of overcurrent protection (OCP) is the normal overload setting based on low-side MOSFET voltage sensing. The second level of protection is the heavy overload setting such as short-circuit based on the high-side MOSFET voltage sensing. This protection takes effect immediately.
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TPS40170 www.ti.com SLUS970A – MARCH 2011 – REVISED NOVEMBER 2013 NOTE Both OCP and SCP are based on low-side and high-side MOSFET voltage sensing at the SW node. Excessive ringing on the SW node can have negative impact on the accuracy of OCP and SCP. Adding an R-C snubber from the SW node to GND helps minimize the potential impact. Soft-Start and Fault-Logic A capacitor from the SS pin to GND defines the SS time, tSS.
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TPS40170 SLUS970A – MARCH 2011 – REVISED NOVEMBER 2013 www.ti.
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TPS40170 www.ti.com SLUS970A – MARCH 2011 – REVISED NOVEMBER 2013 Soft-Start During Overcurrent Fault The soft-start block also has a role to controls the fault-logic timing. If an overcurrent fault (OC_FAULT) is declared, the soft-start capacitor is discharged internally through the device by a small current ISS(sink) (1.05 µA, typ.). Once the SS pin capacitor is discharged to below VSS(flt,low) (300 mV, typ.), the soft-start capacitor begins charging again.
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TPS40170 SLUS970A – MARCH 2011 – REVISED NOVEMBER 2013 www.ti.com Over-Temperature Fault Figure 23 shows the over-temperature protection scheme. If the junction temperature of the device reaches the thermal shutdown limit of tSD(set) (165°C, typ) and SS charging is completed, an over-temperature FAULT is declared. The soft-start capacitor begins to be discharged. During soft-start discharging period, the PWM switching is terminated; therefore both HDRV and LDRV are driven low, turning off both MOSFETs.
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TPS40170 www.ti.com SLUS970A – MARCH 2011 – REVISED NOVEMBER 2013 Frequency Synchronization The TPS40170 has three modes. • Master mode: In this mode the master/slave selector pin, (M/S) is connected to VIN. The SYNC pin emits a stream of pulses at the same frequency as the PWM switching frequency. The pulse stream at the SYNC pin is of 50% duty cycle and the same amplitude as VVBP. Also, the falling edge of the voltage on SYNC pin is synchronized with the rising edge of the HDRV.
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TPS40170 SLUS970A – MARCH 2011 – REVISED NOVEMBER 2013 www.ti.com TPS40170 provides a smooth transition for the SYNC clock signal loss at slave mode. In slave mode, a synchronization clock signal is provided externally through the SYNC pin to the device. The switching frequency is synchronized to the external SYNC clock signal. If for some reason the external clock signal is missing, the device switching frequency is automatically overridden by a transition frequency which is 0.
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TPS40170 www.ti.com SLUS970A – MARCH 2011 – REVISED NOVEMBER 2013 Tracking The TRK pin is used for output voltage tracking. The output voltage is regulated so that the FB pin equals the lowest of the internal reference voltage (VREF) or the level-shifted SS pin voltage (SSEAMP) or the TRK pin voltage. Once the TRK pin goes above the reference voltage, then the output voltage is no longer governed by the TRK pin, but it is governed by the reference voltage.
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TPS40170 SLUS970A – MARCH 2011 – REVISED NOVEMBER 2013 www.ti.com The tracking function configurations and waveforms are shown in Figure 27, Figure 29, and Figure 31 respectively. In simultaneous voltage tracking shown in Figure 27, tracking signals, VTRK1 and VTRK2, of two modules, POL1 and POL2, start up at the same time and their output voltages VOUT1initial and VOUT2initial are approximately the same during initial startup. Since VTRK1 and VTRK2 are less than VREF (0.6 V, typ), Equation 12 is used.
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TPS40170 www.ti.com SLUS970A – MARCH 2011 – REVISED NOVEMBER 2013 In ratiometric voltage tracking shown in Figure 29, the two tracking voltages, VTRK1 and VTRK2, for two modules, POL1 and POL2, are the same. Their output voltage, VOUT1 and VOUT2, are different with different voltage divider R2/R1 and R4/R3. VOUT1 and VOUT2 increase proportionally and reach their output voltage set points at about the same time. VIN VTRK2 VOUT1 VTRK1 VTRK1 POL1 External Tracking Input 0.
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TPS40170 SLUS970A – MARCH 2011 – REVISED NOVEMBER 2013 www.ti.com Sequential startup is shown in Figure 31. During start-up of the first module, POL1, its PGOOD1 is pulled to low. Since PGOOD1 is connected to soft-start SS2 of the second module, POL2, is not able to charge its soft-start capacitor. After output voltage VOUT1 of POL1 reaches its setting point, PGOOD1 is released. POL2 starts charging its soft-start capacitor. Finally, output voltage VOUT2 of POL2 reaches its setting point.
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TPS40170 www.ti.com SLUS970A – MARCH 2011 – REVISED NOVEMBER 2013 Adaptive Drivers The drivers for the external high-side and low-side MOSFETs are capable of driving a gate-to-source voltage, VVBP. The LDRV driver for the low-side MOSFET switches between VBP and PGND, while the HDRV driver for the high-side MOSFET is referenced to SW and switches between BOOT and SW.
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TPS40170 SLUS970A – MARCH 2011 – REVISED NOVEMBER 2013 www.ti.com NOTE When output is pre-biased at VPREBIAS, that voltage also applies to the SW node during start-up. When the pre-bias circuitry commands the first few high-side pulses before the first low-side pulse is initiated, the gate voltage for the high-side MOSFET is as described in Equation 18.
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TPS40170 www.ti.com SLUS970A – MARCH 2011 – REVISED NOVEMBER 2013 Power Good (PGOOD) The TPS40170 provides an indication that the output voltage of the converter is within the specified limits of the regulation as measured at the FB pin. The PGOOD pin is an open-drain signal and pulls low when any condition exists that would indicate that the output of the supply might be out of regulation. These conditions include: • VVFB is not within the PGOOD threshold limits. • Soft-start is active, i.e.
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TPS40170 SLUS970A – MARCH 2011 – REVISED NOVEMBER 2013 www.ti.com Bypass and Filtering In an integrated circuit, supply bypassing is important for jitter-free operation. To decrease noise in the converter, ceramic bypass capacitors must be placed as close to the package as possible. 1. VIN to GND: use 0.1 µF ceramic capacitor. 2. BP to GND: use 1 µF to 10 µF ceramic capacitor. It should be 10 times higher than bootstrap capacitance 3. VDD to GND: use 0.
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TPS40170 www.ti.com SLUS970A – MARCH 2011 – REVISED NOVEMBER 2013 DESIGN EXAMPLE Introduction The wide input TPS40170 controller can function in a very wide range of applications. This example describes the design process for a very wide input (10 V to 60 V) to regulated 5-V output at a load current of 6 A. The schematic shown in Figure 38 is configured for the design parameters provided in Table 1. Table 1.
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TPS40170 SLUS970A – MARCH 2011 – REVISED NOVEMBER 2013 www.ti.com 2 (ITRAN ) ´ L I I I ´L VUNDER < TRAN ´ DT = TRAN ´ TRAN = COUT COUT (VIN - VOUT ) (VIN - VOUT )´ COUT (22) If VIN(min) > 2 x VOUT, use overshoot to calculate minimum output capacitance. If VIN(min) < 2 x VOUT, use undershoot to calculate minimum output capacitance. 2 COUT(min ) ITRAN(max) ) ´ L (3 )2 ´ 8.
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TPS40170 www.ti.com SLUS970A – MARCH 2011 – REVISED NOVEMBER 2013 MOSFET Switch Selection (Q1, Q2) Using the J/K method for MOSFET optimization, apply Equation 30 through Equation 33.
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TPS40170 SLUS970A – MARCH 2011 – REVISED NOVEMBER 2013 www.ti.com SS Timing Capacitor (C15) The soft-start capacitor provides smooth ramp of the error amplifier reference voltage for controlled start-up. The soft-start capacitor is selected by using Equation 38. t 4ms CSS = SS = = 44nF » 47nF 0.09 0.09 (38) ILIM Resistor (R9, C17) The TPS40170 use the negative drop across the low-side FET at the end of the "OFF" time to measure the inductor current.
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TPS40170 www.ti.com SLUS970A – MARCH 2011 – REVISED NOVEMBER 2013 Typical Performance Characteristics Figure 35 shows a 10 V to 60 V to 5.0 V @ 6 A efficiency graph for this design. Figure 36 shows a 24-V to 5.0-V @ 6 A loop response where VIN = 24V and IOUT = 6A, yielding 58 kHz bandwidth, 51° phase margin. Figure 37 shows the output ripple 20 mV/div, 2 µs/div, 20 MHz bandwidth.
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TPS40170 SLUS970A – MARCH 2011 – REVISED NOVEMBER 2013 www.ti.com + Schematic Figure 38.
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TPS40170 www.ti.com SLUS970A – MARCH 2011 – REVISED NOVEMBER 2013 List of Materials Table 3. Design Example List of Materials REFERENCE DESIGNATOR QTY VALUE DESCRIPTION SIZE PART NUMBER C1 4 2.2 µF Capacitor, Ceramic, 100 V, X7R, 15% 1210 C6 1 120 µF Capacitor, Aluminum, 63 V, 20%, KZE Series 0.315" KZE63VB121M10X16LL Chemi-con C7 1 0.
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TPS40170 SLUS970A – MARCH 2011 – REVISED NOVEMBER 2013 www.ti.com Layout Recommendations Figure 39 illustrates an example layout. For the controller, it is important to carefully connect noise sensitive signals such as RT, SS, FB, and comp as close to the IC as possible and connect to AGND as shown. The PowerPad should be connected to any internal PCB ground planes using multiple vias directly under the IC. The AGND and PGND should be connected at a single point.
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TPS40170 www.ti.com SLUS970A – MARCH 2011 – REVISED NOVEMBER 2013 Figure 40.
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TPS40170 SLUS970A – MARCH 2011 – REVISED NOVEMBER 2013 www.ti.com Figure 41.
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TPS40170 www.ti.com SLUS970A – MARCH 2011 – REVISED NOVEMBER 2013 Figure 42.
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TPS40170 SLUS970A – MARCH 2011 – REVISED NOVEMBER 2013 www.ti.com ADDITIONAL REFERENCES 1. Steve Mappus, DV/DT Immunity Improved in Synchronous Buck Converters. July, 2005, Power Electronics Technology. RELATED DEVICES The following devices have characteristics similar to the TPS40170 and may be of interest.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS40170RGYR VQFN RGY 20 3000 330.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1 TPS40170RGYT VQFN RGY 20 250 180.0 12.4 3.8 4.8 1.6 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS40170RGYR VQFN RGY 20 3000 367.0 367.0 35.0 TPS40170RGYT VQFN RGY 20 250 210.0 185.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.