Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - voltage regulators - DC DC switch controllers VSON 10

HDRV

BOOT

LDRV

ENABLE

COMP

VDD

TPS40192/3

5 6BP5PGD

GND

UDG−06063

OUT

ON/OFF

External Logic

Supply

5V or Less,

or BP5

OUT

TPS40192, TPS40193

www.ti.com

SLUS719E –MARCH 2007–REVISED MAY 2013

4.5-V TO 18-V INPUT 10-PIN SYNCHRONOUS BUCK CONTROLLER WITH POWER GOOD

Check for Samples: TPS40192, TPS40193

FEATURES

CONTENTS

• Input Operating Voltage Range: 4.5 V to 18 V

Device Ratings 3

• Up to 20-A Output Currents

Electrical Characteristics 4

• Supports Pre-Biased Outputs

Typical Characteristics 6

• 0.5%, 591-mV Reference

Terminal Information 9

• 600 kHz (TPS40192) and 300 kHz (TPS40193)

Switching Frequencies

Application Information 11

• Three Selectable Thermally Compensated

Design Example 19

Short-Circuit Protection Levels

Additional References 29

• Hiccup Restart from Faults

• Internal 5-V Regulator

DESCRIPTION

• High-Side and Low-Side FET R

DS(on)

Current

TPS40192 and TPS40193 are cost-optimized

Sensing

synchronous buck controllers that operate from 4.5 V

• 10-Pin 3 mm × 3 mm SON Package

to 18 V input. These controllers implement a voltage-

mode control architecture with the switching

• Internal 4-ms Soft-Start Time

frequency fixed at either 600 kHz (TPS40192) or 300

• Thermal Shutdown Protection at 145°C

kHz (TPS40193). The higher switching frequency

facilitates the use of smaller inductor and output

APPLICATIONS

capacitors, thereby providing a compact power-

• Cable Modem CPE supply solution. An adaptive anti-cross conduction

scheme is used to prevent shoot through current in

• Digital Set Top Box

the power FETs.

• Graphics/Audio Cards

• Entry Level and Mid-Range Servers

SIMPLIFIED APPLICATION DIAGRAM

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (38 pages)

PAGE 1
TPS40192, TPS40193 www.ti.com SLUS719E – MARCH 2007 – REVISED MAY 2013 4.5-V TO 18-V INPUT 10-PIN SYNCHRONOUS BUCK CONTROLLER WITH POWER GOOD Check for Samples: TPS40192, TPS40193 FEATURES CONTENTS 1 • • • • • • • • • • • • Input Operating Voltage Range: 4.5 V to 18 V Up to 20-A Output Currents Supports Pre-Biased Outputs 0.
PAGE 2
TPS40192, TPS40193 SLUS719E – MARCH 2007 – REVISED MAY 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (continued) Short circuit detection is done by sensing the voltage drop across the low-side MOSFET when it is on and comparing it with a user selected threshold of 100 mV, 200 mV or 280 mV.
PAGE 3
TPS40192, TPS40193 www.ti.com SLUS719E – MARCH 2007 – REVISED MAY 2013 DEVICE RATINGS ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) TPS40192/TPS40193 VDD, ENABLE SW Input voltage range –5 to 25 BOOT, HDRV –0.3 to 30 BOOT-SW, HDRV-SW (differential from BOOT or HDRV to SW) -0.3 to 6 COMP, FB, BP5, LDRV, PGD –0.3 to 6 TJ Operating junction temperature range –40 to 150 Tstg Storage temperature –55 to 150 (1) UNIT –0.
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TPS40192, TPS40193 SLUS719E – MARCH 2007 – REVISED MAY 2013 www.ti.com ELECTRICAL CHARACTERISTICS TJ = –40°C to 85°C, VVDD= 12 Vdc, all parameters at zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 0°C ≤ TJ ≤ 85°C 588 591 594 -40°C ≤ TJ ≤ 85°C 585 591 594 UNIT REFERENCE VFB Feedback voltage range mV INPUT SUPPLY VVDD Input voltage range IVDD 4.5 Operating current 18.0 V VENABLE = 3 V 2.5 4.0 mA VENABLE = 0.
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TPS40192, TPS40193 www.ti.com SLUS719E – MARCH 2007 – REVISED MAY 2013 ELECTRICAL CHARACTERISTICS (continued) TJ = –40°C to 85°C, VVDD= 12 Vdc, all parameters at zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OUTPUT DRIVERS RHDHI High-side driver pull-up resistance VBOOT - VSW = 4.5 V, IHDRV = -100 mA 3 6 RHDLO High-side driver pull-down resistance VBOOT - VSW = 4.5 V, IHDRV = 100 mA 1.5 3.
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TPS40192, TPS40193 SLUS719E – MARCH 2007 – REVISED MAY 2013 www.ti.com TYPICAL CHARACTERISTICS RELATIVE REFERENCE FEEDBACK VOLTAGE vs JUNCTION TEMPERATURE RELATIVE OSCILLATOR FREQUENCY CHANGE vs JUNCTION TEMPERATURE 0.5 fSW − Relative Oscillator Frequency Change − % VFB− Relative Reverefnce Voltage Change − % 0.50 0.00 −0.05 −0.10 −0.15 −0.20 −0.25 −0.30 −0.35 −0.40 −0.45 0.0 −0.5 −1.0 −1.5 −2.0 −2.5 −3.0 −3.5 −4.0 −4.5 −40 −25 −10 −0.
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TPS40192, TPS40193 www.ti.com SLUS719E – MARCH 2007 – REVISED MAY 2013 TYPICAL CHARACTERISTICS (continued) SOFT START TIME vs JUNCTION TEMPERATURE LOW-SIDE MOSFET CURRENT LIMIT THRESHOLD vs JUNCTION TEMPERATURE 4.05 400 350 VILIM − Current Limit Threshold − mV tSS − Soft start Time − ms 4.00 3.95 3.90 3.85 3.80 3.
PAGE 8
TPS40192, TPS40193 SLUS719E – MARCH 2007 – REVISED MAY 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) POWERGOOD THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE SHUTDOWN CURRENT vs INPUT VOLTAGE 100 VENABLE < 0.
PAGE 9
TPS40192, TPS40193 www.ti.com SLUS719E – MARCH 2007 – REVISED MAY 2013 DEVICE INFORMATION Table 1. TERMINAL FUNCTIONS TERMINAL NAME NO. BOOT 8 I/O DESCRIPTION I Gate drive voltage for the high-side N-channel MOSFET. A capacitor 100 nF typical must be connected between this pin and SW. BP5 6 O Output bypass for the internal regulator. Connect at least 1μF capacitor from this pin to GND. Larger capacitors, up to 4.
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TPS40192, TPS40193 SLUS719E – MARCH 2007 – REVISED MAY 2013 www.ti.com VDD SC + OCL FAULT Fault Controller CLK ENABLE SD 1 + SD UVLO OCH Soft Start Ramp Generator (VVDD – 0.5 V) VDD 5V Regulator 4 BP5 6 COMP 3 4.
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TPS40192, TPS40193 www.ti.com SLUS719E – MARCH 2007 – REVISED MAY 2013 APPLICATION INFORMATION Introduction The TPS40192 and TPS40193 are cost optimized controllers providing all the necessary features to construct a high performance DC/DC converter while keeping costs to a minimum. Support for pre-biased outputs eliminates concerns about damaging sensitive loads during startup. Strong gate drivers for the high side and rectifier Nchannel MOSFETs decrease switching losses for increased efficiency.
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TPS40192, TPS40193 SLUS719E – MARCH 2007 – REVISED MAY 2013 www.ti.com Enable Functionality The TPS40192 and TPS40193 have a dedicated ENABLE pin. This simplifies user level interface design since no multiplexed functions exist. Another benefit is a true low power shutdown mode of operation. When the ENABLE pin is pulled to GND, all unnecessary functions, including the BP5 regulator, are turned off, reducing the device IDD current to 45-µA.
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TPS40192, TPS40193 www.ti.com SLUS719E – MARCH 2007 – REVISED MAY 2013 Startup Sequence and Timing The TPS40192/3 startup sequence is as follows. After input power is applied, the 5-V onboard regulator comes up. Once this regulator comes up, the device goes through a period where it samples the impedance at the COMP pin and determines the short circuit protection threshold voltage, by placing 400 mV on the COMP pin for approximately 1 ms.
PAGE 14
TPS40192, TPS40193 SLUS719E – MARCH 2007 – REVISED MAY 2013 www.ti.com Selecting the Short Circuit Current A short circuit in the TPS40192/3 is detected by sensing the voltage drop across the low-side FET when it is on, and across the high-side FET when it is on. If the voltage drop across either FET exceeds the short circuit threshold in any given switching cycle, a counter increments one count.
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TPS40192, TPS40193 www.ti.com SLUS719E – MARCH 2007 – REVISED MAY 2013 The range of short circuit current thresholds that can be expected is shown in Equation 2 and Equation 3.
PAGE 16
TPS40192, TPS40193 SLUS719E – MARCH 2007 – REVISED MAY 2013 www.ti.com 5-V Regulator These devices have an on board 5-V regulator that allows the parts to operate from a single voltage feed. No separate 5-V feed to the part is required. This regulator needs to have a minimum of 1-μF of capacitance on the BP5 pin for stability. A ceramic capacitor is suggested for this purpose. This regulator can also be used to supply power to nearby circuitry, eliminating the need for a separate LDO in some cases.
PAGE 17
TPS40192, TPS40193 www.ti.com SLUS719E – MARCH 2007 – REVISED MAY 2013 Pre-Bias Startup The TPS40192/3 contains a unique circuit to prevent current from being pulled from the output during startup in the condition the output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft-start becomes greater than feedback voltage [VFB]), the controller slowly activates synchronous rectification by starting the first LDRV pulses with a narrow on-time.
PAGE 18
TPS40192, TPS40193 SLUS719E – MARCH 2007 – REVISED MAY 2013 www.ti.com Layout Recommendations and Sample Layout Layout Recommendations: • PowerPad™ is the only GND connection to the device (U1). PowerPad™ must be connected to ground. • PowerPad™ should be directly connected to SYNC FET (Q3) source with short, wide trace. • Locate 3-5 vias in PowerPad™ land to remove heat from the device.
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TPS40192, TPS40193 www.ti.com SLUS719E – MARCH 2007 – REVISED MAY 2013 DESIGN EXAMPLE Introduction This example illustrates the design process and component selection for a 12 V to 1.8 V point-of-load synchronous buck regulator using the TPS40192. A definition of symbols used can be found in Table 8 of this datasheet. Table 3.
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TPS40192, TPS40193 SLUS719E – MARCH 2007 – REVISED MAY 2013 • • • • www.ti.com Connect signal ground island to PowerPad with a single 10-mil wide trace. Connect power ground to the source of the synchronous rectifier. The PowerPad serves as the only ground for the controller. PowerPAD must be connected to signal ground and power ground. Design Procedure Selecting the Switching Frequency For this design the TPS40192, with fSW = 600 kHz, is selected to reduce inductor and capacitor sizes.
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TPS40192, TPS40193 www.ti.com ESR MAX t SLUS719E – MARCH 2007 – REVISED MAY 2013 VRIPPLE(tot) * VRIPPLE(cap) C OUT V RIPPLE(tot) * + ǒ Ǔ I RIPPLE C OUT f SW I RIPPLE (11) Based on 178 μF of capacitance, 2.6-A ripple current, 600-kHz switching frequency and 36-mV ripple voltage, calculate a capacitive ripple of 24.3 mV and a maximum ESR of 4.4 mΩ. Two 1206 100-μF, 6.3-V X5R ceramic capacitors are selected to provide more than 178-μF of minimum capacitance and less than 4.4 mΩ of ESR (2.5 mΩ each).
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TPS40192, TPS40193 SLUS719E – MARCH 2007 – REVISED MAY 2013 P G1_SW + 1 VIN 2 I OUT www.ti.com T SW f SW + 1 VIN 2 I OUT Q GD1 VDD*V TH RDRV f SW (17) For this design switching losses will be highest at high-line Designing for 1 W of total losses in each MOSFETS and 60% of the total high-side FET losses in switching losses, we can estimate our maximum gate-drain charge for the design by using Equation 18.
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TPS40192, TPS40193 www.ti.com SLUS719E – MARCH 2007 – REVISED MAY 2013 Boot Strap Capacitor To ensure proper charging of the high-side FET gate, limit the ripple voltage on the boost capacitor to less than 50 mV. C BOOST + 20 Q G1 (22) Based on the IRF7466 MOSFET with a gate charge of 23 nC, we calculate minimum of 460 nF of capacitance. The next higher standard value of 470 nF is selected for the bootstrap capacitor.
PAGE 24
TPS40192, TPS40193 SLUS719E – MARCH 2007 – REVISED MAY 2013 www.ti.com Feedback Compensation Modeling the Power Stage The DC gain of the modulator is given by Equation 26. dV OUT dt 1 A MOD + + dD V IN + dVCOMP V COMP dV RAMP T SW V IN (26) Since the peak-to-peak ramp voltage given in the Electrical Characteristics Table is projected from the ramp slope over a full switching period, the modulator gain can be calculated as Equation 27.
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TPS40192, TPS40193 www.ti.com SLUS719E – MARCH 2007 – REVISED MAY 2013 C3 3 R6 C1 R8 VOUT 2 C2 + To PWM R10 + VFB R7 11 Power Pad UDG−06068 Figure 19. Type-III Compensator Used with TPS40040/41 Feedback Divider (R7, R8) Select R8 to be between 10 kΩ and 100 kΩ. For this design, select 20 kΩ. R7 is then selected to produce the desired output voltage when VFB = 0.591 V using Equation 30. V FB R8 R7 + V OUT * V FB (30) VFB = 0.591 V and R8 = 20 kΩ for VOUT = 1.8 V, R7 = 9.78 kΩ, so the value of 9.
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TPS40192, TPS40193 SLUS719E – MARCH 2007 – REVISED MAY 2013 www.ti.com Table 6. Error Amplifier Design Parameters PARAMETER SYMBOL VALUE FZ1 5.8 Second zero frequency FZ2 11.0 First pole frequency FP1 60 First zero frequency Second pole frequency Midband gain FP2 500 AMID(band) 1.86 UNITS kHz V/V Approximate C2 with the formula described in Equation 32.
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TPS40192, TPS40193 www.ti.com SLUS719E – MARCH 2007 – REVISED MAY 2013 List of Materials Table 7. List of Materials REF DES QTY Value Description Size Part Number MFR 1 C1 100 pF Capacitor, Ceramic, 10V, C0G, 10% 0603 STD STD 1 C2 1000 pF Capacitor, Ceramic, 10V, C0G, 10% 0603 STD STD 1 C3 10 nF Capacitor, Ceramic, 10V, C0G, 10% 0603 STD STD 1 C4 1.0 μF Capacitor, Ceramic, 25V, X5R, 20% 0805 STD STD 1 C5 4.
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TPS40192, TPS40193 SLUS719E – MARCH 2007 – REVISED MAY 2013 www.ti.com DEFINITION OF SYMBOLS Table 8.
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TPS40192, TPS40193 www.ti.com SLUS719E – MARCH 2007 – REVISED MAY 2013 ADDITIONAL REFERENCES Related Parts The following parts have characteristics similar to the TPS40192/3 and may be of interest. Table 9.
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TPS40192, TPS40193 SLUS719E – MARCH 2007 – REVISED MAY 2013 www.ti.com REVISION HISTORY Changes from Revision B (SEPTEMBER 2007) to Revision C Page • Changed corrected label for pin 8 ...................................................................................................................................... 10 • Changed corrected waveform .............................................................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 13-May-2013 (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
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PACKAGE MATERIALS INFORMATION www.ti.com 9-Apr-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing TPS40192DRCR SON DRC 10 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3000 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2 TPS40192DRCT SON DRC 10 250 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2 TPS40193DRCR SON DRC 10 3000 330.0 12.4 3.3 3.3 1.0 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 9-Apr-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS40192DRCR SON DRC 10 3000 370.0 355.0 55.0 TPS40192DRCT SON DRC 10 250 195.0 200.0 45.0 TPS40193DRCR SON DRC 10 3000 370.0 355.0 55.0 TPS40193DRCT SON DRC 10 250 210.0 185.0 35.0 TPS40193DRCT SON DRC 10 250 195.0 200.0 45.
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