Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - voltage regulators - DC DC switch controllers SOIC 8

1.0

100

0.5 1.5 2.0 2.5

Load Current (A)

Efficiency (%)

OUT

= 5 V

(V)

VDD

ISNS

GDRV

GND

COMP

TPS40200

OUT

UDG-11201

TPS40200

www.ti.com

SLUS659F –FEBRUARY 2006–REVISED MARCH 2012

WIDE INPUT RANGE NON-SYNCHRONOUS VOLTAGE MODE CONTROLLER

Check for Samples: TPS40200

FEATURES

DESCRIPTION

• Input Voltage Range 4.5 V to 52 V

The TPS40200 is a flexible non-synchronous

• Output Voltage (700 mV to 90% V

)

controller with a built in 200-mA driver for P-channel

• 200 mA Internal P-channel FET Driver

FETs. The circuit operates with inputs up to 52 V with

a power-saving feature that turns off driver current

• Voltage Feed-Forward Compensation

once the external FET has been fully turned on. This

• Undervoltage Lockout

feature extends the flexibility of the device, allowing it

• Programmable Fixed-Frequency (between 35

to operate with an input voltage up to 52 V without

kHz and 500 kHz) Operation

dissipating excessive power. The circuit operates with

voltage-mode feedback and has feed-forward input-

• Programmable Short-Circuit Protection

voltage compensation that responds instantly to input

• Hiccup Overcurrent Fault Recovery

voltage change. The integral 700-mV reference is

• Programmable Closed Loop Soft Start

trimmed to 2%, providing the means to accurately

control low voltages. The TPS40200 is available in

• 700 mV 1% Reference Voltage

and 8-pin SOIC and an 8-pin QFN package and

• External Synchronization

supports many of the features of more complex

• Small 8-Pin SOIC (D) and QFN (DRB) Packages

controllers. Clock frequency, soft-start, and

overcurrent limit are each easily programmed by a

APPLICATIONS

single, external component. The part has

undervoltage lockout, and can be easily synchronized

• Industrial Control

to other controllers or a system clock to satisfy

• Distributed Power Systems

sequencing and/or noise-reduction requirements.

• DSL/Cable Modems

• Scanners

• Telecom

TYPICAL APPLICATION

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (47 pages)

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TPS40200 www.ti.com SLUS659F – FEBRUARY 2006 – REVISED MARCH 2012 WIDE INPUT RANGE NON-SYNCHRONOUS VOLTAGE MODE CONTROLLER Check for Samples: TPS40200 FEATURES 1 • • • • • • • • • • • • Input Voltage Range 4.
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TPS40200 SLUS659F – FEBRUARY 2006 – REVISED MARCH 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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TPS40200 www.ti.
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TPS40200 SLUS659F – FEBRUARY 2006 – REVISED MARCH 2012 www.ti.com Table 1.
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TPS40200 www.ti.com SLUS659F – FEBRUARY 2006 – REVISED MARCH 2012 Table 2. TERMINAL I/O DESCRIPTION 3 O Error amplifier output. Connect control loop compensation network from COMP to FB. 4 I Error amplifier inverting input. Connect feedback resistor network center tap to this pin. NAME NO. COMP FB GND 5 GDRV 6 O Driver output for external P-channel MOSFET ISNS 7 I Current-sense comparator input.
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TPS40200 SLUS659F – FEBRUARY 2006 – REVISED MARCH 2012 www.ti.com TYPICAL CHARACTERISTICS QUIESCENT CURRENT vs TEMPERATURE QUIESCENT CURRENT vs INPUT VOLTAGE 3 1.66 1.65 2.5 1.64 2 1.62 IDD - mA IDD - mA 1.63 1.61 1.6 1.5 1 1.59 1.58 VDD = 12 V 0.5 1.57 1.56 -50 0 -25 0 25 50 75 100 5 125 10 15 20 30 35 VDD - V 40 45 50 Figure 2. SOFT START THRESHOLD vs TEMPERATURE UVLO TURN ON AND TURN OFF vs TEMPERATURE 156.5 4.3 156 4.25 155.5 155 154.5 154 VDD = 12 V 153.
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TPS40200 www.ti.com SLUS659F – FEBRUARY 2006 – REVISED MARCH 2012 TYPICAL CHARACTERISTICS (continued) OSCILLATOR FREQUENCY vs TEMPERATURE CURRENT LIMIT THRESHOLD vs TEMPERATURE 103 98 96 102.5 VDD = 4.5 V 102 R = 202 kW C = 470 pF 92 ILIM threshold - mV Frequency (kHz) 94 90 88 VDD = 12 V 86 84 80 -50 -25 0 25 50 75 100 101 VDD = 12 V 100.5 100 VDD = 52 V 82 101.5 99.5 -50 125 -25 0 Temp (°C) 50 75 100 125 Temp - °C Figure 5. Figure 6.
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TPS40200 SLUS659F – FEBRUARY 2006 – REVISED MARCH 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) POWER STAGE GAIN vs TEMPERATURE POWER STAGE GAIN vs TEMPERATURE 20.50 20.50 20.30 20.45 VDD = 24 V VDD = 4.5 V 20.40 VDD = 12 V 19.90 Gain - dB Gain - dB 20.10 19.70 20.35 VDD = 52 V 20.30 19.50 20.25 -50 -25 0 25 50 75 100 125 -50 -25 0 Temp - °C MODULATOR RAMP AMPLITUDE vs TEMPERATURE MODULATOR RAMP AMPLITUDE vs TEMPERATURE VDD = 24 V Vramp - V Vramp - V 2.2 2 1.8 1.
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TPS40200 www.ti.com SLUS659F – FEBRUARY 2006 – REVISED MARCH 2012 TYPICAL CHARACTERISTICS (continued) MODULATOR RAMP AMPLITUDE vs VDD FEEDBACK AMPLIFIER INPUT BIAS CURRENT vs TEMPERATURE 160 6 TJ = 25°C 140 5 120 100 IIB - nA VRAMP - V 4 3 80 60 2 40 1 20 0 0 5 10 15 20 25 30 35 VDD - V 40 45 50 55 -50 0 25 50 75 100 125 100 125 Temp - °C Figure 13. Figure 14. COMP SOURCE CURRENT vs TEMPERATURE COMP SINK CURRENT vs TEMPERATURE 3.
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TPS40200 SLUS659F – FEBRUARY 2006 – REVISED MARCH 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) GATE DRIVE VOLTAGE vs TEMPERATURE GATE DRIVE VOLTAGE vs VIN 8.4 8 VDD = 12 V 7.8 7.6 VGATE - V VJ = 25°C 8.2 8 7.4 7.8 7.2 7.6 7 7.4 6.8 7.2 6.6 7 6.4 Temp - °C 30 35 VDD - V Figure 17. Figure 18.
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TPS40200 www.ti.com SLUS659F – FEBRUARY 2006 – REVISED MARCH 2012 TYPICAL CHARACTERISTICS (continued) MINIMUM CONTROLLABLE PULSE WIDTH vs FREQUENCY MAXIMUM DUTY CYCLE vs INPUT VOLTAGE 700 100 600 95 Maximum Duty Cycle (%) VDD = 4.5 V Pulse Width - ns 500 400 300 VDD = 24 V VDD = 12 V 200 100 VDD = 36 V 0 100 85 80 75 fOSC (kHz) 500 200 100 50 70 65 VDD = 52 V 0 90 60 200 300 400 500 0 10 20 30 40 50 Input Voltage (V) Frequency - kHz Figure 21. Figure 22.
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TPS40200 SLUS659F – FEBRUARY 2006 – REVISED MARCH 2012 www.ti.com APPLICATION INFORMATION Overview The TPS40200 is a non-synchronous controller with a built in 200-mA driver designed to drive high speed Pchannel FETS up to 500 kHz. Small size combined with complete functionality makes the part both versatile and easy to use. The controller uses a low-value current-sensing resistor in series with the input voltage and the power FET’s source connection to detect switching current.
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TPS40200 www.ti.com SLUS659F – FEBRUARY 2006 – REVISED MARCH 2012 TPS40200 VDD 8 VIN + S Q R Q CLK RRC External Frequency Synchronization (optional) RC + 1 + CRC 150 mV GND 5 UDG-05070 Figure 23. Oscillator Functional Diagram TPS40200 VDD 8 VIN + Amplitude > VIN 10 Q R Q CLK RC RRC RC + 1 Frequency > Controller Frequency S + CRC 150 mV GND 5 UDG-10076 Figure 24.
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TPS40200 SLUS659F – FEBRUARY 2006 – REVISED MARCH 2012 www.ti.com Current Limit Resistor Selection As shown in Figure 27, a resistor in series with the power MOSFET sets the overcurrent protection level. Use a low-inductance resistor to avoid ringing signals and nuisance tripping. When the FET is on and the controller senses 100mV or more drop from the VDD pin to the ISNS pin, an overcurrent condition is declared.
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TPS40200 www.ti.com SLUS659F – FEBRUARY 2006 – REVISED MARCH 2012 If necessary, a small R-C filter can be added to the current sensing network to reduce nuisance tripping due to noise pickup. This filter can also be used to trim the overcurrent trip point to a higher level with the addition of a single resistor. See Figure 27. The nominal overcurrent trip point using the circuit of Figure 27 is described in Equation 3.
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TPS40200 SLUS659F – FEBRUARY 2006 – REVISED MARCH 2012 www.ti.com MOSFET Gate Drive The output driver sinking current is approximately 200 mA and is designed to drive P-channel power FETs. When the driver pulls the gate charge of the FET it is controlling to –8 V, the drive current folds back to a low level so that high-power dissipation only occurs during the turn-on period of the FET.
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TPS40200 www.ti.com SLUS659F – FEBRUARY 2006 – REVISED MARCH 2012 Programming the Soft-Start Time An external capacitor CSS, connected from the SS pin to ground controls the soft-start interval. An internal charging resistor connected to VDD produces a rising reference voltage which is connected though a 700-mV offset to the reference input of the TPS40200 error amplifier. When the soft-start capacitor voltage (VCSS) is below 150 mV, there is no switching activity.
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TPS40200 SLUS659F – FEBRUARY 2006 – REVISED MARCH 2012 www.ti.com Voltage Setting and Modulator Gain Since the input current to the error amplifier is negligible, the feedback impedance can be selected over a wide range. Knowing that the reference voltage is 696 mV, choose a convenient value for R1 and then calculate the value of R2 from Equation 2. æ R2 ö VOUT = 0.696 ´ ç 1 + R1 ÷ø è (7) Vg L VOUT d KPWM COUT RLOAD VC R2 + VREF R1 UDG-10220 Figure 30.
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TPS40200 www.ti.com SLUS659F – FEBRUARY 2006 – REVISED MARCH 2012 DESIGN EXAMPLES Application 1: Buck Regulator, 8-to-12 V Input, 3.3 V or 5.0 V at 2.5 A Output Overview The buck regulator design shown in Figure 31 shows the use of the TPS40200. It delivers 2.5 A at either 3.3 or 5.0 V as selected by a single feedback resistor. It achieves approximately 90 % efficiency at 3.3 V and 94% at 5.0 V.
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TPS40200 SLUS659F – FEBRUARY 2006 – REVISED MARCH 2012 www.ti.com Component Selection Table 3. Design Parameters PARAMETER TEST CONDITION VIN Input Voltage VOUT Output Voltage IOUT = 2.5 A Line Regulation VOUT MAX UNIT 8 12 16 V 3.3 3.4 (1) V ± 0.2 % VOUT 3.293 3.300 3.307 V Load Regulation ± 0.2% VOUT 3.293 3.300 3.307 V Output Voltage IOUT at 2.5 A 4.85 5.0 5.150 (1) V Line Regulation ± 0.2% × VOUT 4.99 5.00 5.01 V 4.99 5.00 5.01 Load Regulation ± 0.
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TPS40200 www.ti.com SLUS659F – FEBRUARY 2006 – REVISED MARCH 2012 Using the values in this example, the dc power loss is 129 mW. The remaining FET losses are as follows: • PSW is the power dissipated while switching the FET on and off • Pgate is the power dissipated driving the FET gate capacitance • PCOSS is the power switching the FET output capacitance The total power dissipated by the FET is the sum of these contributions.
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TPS40200 SLUS659F – FEBRUARY 2006 – REVISED MARCH 2012 www.ti.com Rectifier Selection Criteria 1. Rectifier Breakdown Voltage The rectifier has to withstand the maximum input voltage which in this case is 16 V. To allow for switching transients which can approach the switching voltage a 30 V rectifier was selected. 2. Diode Size The importance of power losses from the Schottky rectifier D2 is determined by the duty cycle.
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TPS40200 www.ti.com SLUS659F – FEBRUARY 2006 – REVISED MARCH 2012 Inductor Selection Criteria The P-channel FET driver facilitates switching the power FET at a high frequency. This, in turn, enables the use of smaller, less-expensive inductors as illustrated in this 300-kHz application. Ferrite, with its good high frequency properties, is the material of choice.
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TPS40200 SLUS659F – FEBRUARY 2006 – REVISED MARCH 2012 www.ti.com Output Capacitance In order to satisfy the output voltage over and under shoot specifications there must be enough output capacitance to keep the output voltage within the specified voltage limits during load current steps. In a situation where a full load of 2.5 A within the specified voltage limits is suddenly removed, the output capacitor must absorb energy stored in the output inductor.
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TPS40200 www.ti.com SLUS659F – FEBRUARY 2006 – REVISED MARCH 2012 At a worst case of 16 V, the timing resistor draws about 250 μA which is well below the 750 μA maximum which the circuit can pull down. Programming the Overcurrent Threshold Level The current limit in the TSP40200 is triggered by a comparator with a 100-mV offset whose inputs are connected across a current-sense resistor between VCC and the source of the high-side switching FET.
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TPS40200 SLUS659F – FEBRUARY 2006 – REVISED MARCH 2012 www.ti.com Soft Start Capacitor The soft start interval is given (in pF) by the following equation: C SS = t SS æ VSST ö ÷ R ´ ln çç ÷ è VSST - 1.4 ø ´ 10 3 where • R is an internal 105-kΩ charging resistor • VCC is the input voltage up to 8 V where the charging voltage is internally clamped. to 8 V maximum • VOS = 700 mV, and because the input voltage is 12 V, VSST = 8 V.
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TPS40200 www.ti.com SLUS659F – FEBRUARY 2006 – REVISED MARCH 2012 Frequency Compensation The four elements that determine the system overall response are discussed below The gain of the error amplifier (KEA) is the first of there elements. Its output develops a control voltage which is the input to the PWM. The TPS40200 has a unique modulator that scales the peak to peak amplitude of the PWM ramp to be 0.1 times the value of the input voltage.
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TPS40200 SLUS659F – FEBRUARY 2006 – REVISED MARCH 2012 www.ti.com Figure 37 shows the feedback network used in this application. This is a Type II compensation network which gives a combination of good transient response and phase boost for good stability. This type of compensation has a pole at the origin causing a -20dB/decade (-1) slope followed by a zero that causes a region of flat gain followed by a final pole that returns the gain slope to -1 .
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TPS40200 www.ti.com SLUS659F – FEBRUARY 2006 – REVISED MARCH 2012 In order to properly compensate this system, it is necessary to know the frequencies of its poles and zeros. Step 1 The break frequency of the output capacitor is given by: fESR = 1 2p ´ RESR ´ COUT where • C = the output capacitor, 221 μF • RESR = the ESR of the capacitors Because of the ESR of the output capacitor, the output LC filter has a single-pole response above the 1.8-kHz break frequency of the output capacitor and its ESR.
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TPS40200 SLUS659F – FEBRUARY 2006 – REVISED MARCH 2012 www.ti.com Step 5 Calculate the gain elements in the system to determine the gain required by the error amplifier to make the over all gain 0 dB at 35 kHz.
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TPS40200 www.ti.com VOUT (S ) = VIN SLUS659F – FEBRUARY 2006 – REVISED MARCH 2012 A VOL R10 R10 1+ + ´ (1 + A VOL ) R 8 ZFS where • Zfs is the parallel combination of C7 in parallel with the sum of R8 and the impedance of C8. • AVOLis the open-loop gain of the error amplifier at 35 kHz, which is 44.6, or 33 db. Figure 40 shows the result of the compensation. The crossover frequency is 35 kHz and the phase margin is 45 degrees.
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TPS40200 SLUS659F – FEBRUARY 2006 – REVISED MARCH 2012 www.ti.com Table 4. List of Materials, Buck Regulator, 12 V to 3.3 V and 5.0 V Ref. Des. Value Description Size Mfr. Part Number C1 100 μF Capacitor, Aluminum, SM, 25-V, 0.3 Ω 8 x 10 mm Sanyo 20SVP100M C12 220 μF Capacitor, Aluminum, SM, 6.3-V, 0.4 Ω 8 x 6.2 mm Panasonic EEVFC0J221P C13 100 pF Capacitor, Ceramic, 50V, [COG], [20%] 603 muRata Std. C3 0.1 pF Capacitor, Ceramic, 50V, [X7R], [20%] 603 muRata Std.
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TPS40200 www.ti.com SLUS659F – FEBRUARY 2006 – REVISED MARCH 2012 Figure 41. TPS40200EVM-001 Component Placement (Viewed from Top) Figure 42. TPS40200EVM001 Top Copper (Viewed from Top) Figure 43.
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TPS40200 SLUS659F – FEBRUARY 2006 – REVISED MARCH 2012 www.ti.com Application 2: 18 - 50 V Input, 16 V at 1 A Output This is an example of using the TPS40200 in a higher voltage application. The output voltage is 16 V at 1 A with an 18 to 50 V input. Module boards built to this schematic and a test report are available from the factory. Some of the test results are shown below. Test Results The following two curves demonstrate some of the performance obtained from this application.
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TPS40200 www.ti.com SLUS659F – FEBRUARY 2006 – REVISED MARCH 2012 Application 3: Wide Input Voltage LED Constant Current Driver This application uses the TPS40200 as a buck controller that drives a string of LED diodes. The feedback point for this circuit is a sense resistor in series with this string. The low 0.7-V reference minimizes power wasted in this resistor, and maintains the LED current at a value given by 0.7/RSENSE.
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TPS40200 SLUS659F – FEBRUARY 2006 – REVISED MARCH 2012 www.ti.
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TPS40200 www.ti.com SLUS659F – FEBRUARY 2006 – REVISED MARCH 2012 Layout Hints • Keep the ac current loops as short as possible. For the maximum effectiveness from C3, place it near the VDD pin of the controller and design the input ac loop consisting of C1-RSENSE-Q1-D1 to be as short as possible. Excessive high frequency noise on VDD during switching degrades overall regulation as the load increases. • Keep the output loop A (D1-L1-C2) as small as possible.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS40200DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TPS40200DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS40200DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS40200DR TPS40200DRBR SOIC D 8 2500 340.5 338.1 20.6 SON DRB 8 3000 367.0 367.0 35.0 TPS40200DRBT SON DRB 8 250 210.0 185.0 35.0 TPS40200GDR SOIC D 8 2500 340.5 338.1 20.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.