TPS40210-Q1, TPS40211-Q1 www.ti.com SLVS861D – AUGUST 2008 – REVISED APRIL 2010 4.
TPS40210-Q1, TPS40211-Q1 SLVS861D – AUGUST 2008 – REVISED APRIL 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
TPS40210-Q1, TPS40211-Q1 www.ti.com SLVS861D – AUGUST 2008 – REVISED APRIL 2010 ELECTRICAL CHARACTERISTICS TJ = –40°C to 125°C, VVDD= 12 Vdc, all parameters at zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Voltage Reference VFB TPS40210 COMP = FB, 4.5 ≤ VVDD ≤ 52 V TJ = 25°C 693 700 707 –40°C ≤ TJ ≤ 125°C 686 700 714 TPS40211 COMP = FB, 4.5 ≤ VVDD ≤ 52 V TJ = 25°C 254 260 266 –40°C ≤ TJ ≤ 125°C 250 260 270 52 V 4.
TPS40210-Q1, TPS40211-Q1 SLVS861D – AUGUST 2008 – REVISED APRIL 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) TJ = –40°C to 125°C, VVDD= 12 Vdc, all parameters at zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 4.2 5.6 7.
TPS40210-Q1, TPS40211-Q1 www.ti.com SLVS861D – AUGUST 2008 – REVISED APRIL 2010 TYPICAL CHARACTERISTICS FREQUENCY vs TIMING RESISTANCE SWITCHING FREQUENCY vs DUTY CYCLE 68 pF CT(pF) 33pF 470 220 100 68 33 fSW - Frequency - kHz 1000 800 100pF 600 220 pF 400 1200 1000 fSW - Frequency - kHz 1200 200 800 600 400 200 470 pF 0 100 200 300 400 500 600 700 800 RT - Timing Resistance - kW 0 900 1000 0 0.2 0.4 0.6 0.8 D - Duty Cycle Figure 1. Figure 2.
TPS40210-Q1, TPS40211-Q1 SLVS861D – AUGUST 2008 – REVISED APRIL 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) REFERENCE VOLTAGE CHANGE vs JUNCTION TEMPERATURE REFERENCE VOLTAGE CHANGE vs INPUT VOLTAGE 0.4 0.5 0.4 0.2 0.0 -0.2 -0.4 -0.6 4.5 V VVDD 12 V 4.5 V 52 V 12 V VFB – Reference Voltage Change – % VFB – Reference Voltage Change – % 52 V 0.2 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.8 -40 -25 -10 5 20 35 50 65 80 95 110 125 TJ – Junction Temperature – ° C -0.
TPS40210-Q1, TPS40211-Q1 www.ti.com SLVS861D – AUGUST 2008 – REVISED APRIL 2010 TYPICAL CHARACTERISTICS (continued) SWITCHING FREQUENCY CHANGE vs JUNCTION TEMPERATURE 155 5 154 4 fOSC – Switching Frequency Change – % VISNS(OC) – Overcurrent Threshold – mV OVERCURRENT THRESHOLD vs INPUT VOLTAGE 153 152 151 150 149 148 147 146 145 5 10 15 20 25 30 35 VVDD – Input Voltage – V 40 Slope Compensation Ratio (VVDD/VSLP) 4.5 V 1 12 V 0 -1 30 V -2 VVDD (V) 4.5 V 12 V 30 V -3 -4 Figure 9.
TPS40210-Q1, TPS40211-Q1 SLVS861D – AUGUST 2008 – REVISED APRIL 2010 www.ti.
TPS40210-Q1, TPS40211-Q1 www.ti.com SLVS861D – AUGUST 2008 – REVISED APRIL 2010 TYPICAL CHARACTERISTICS (continued) REGULATOR VOLTAGE vs JUNCTION TEMPERATURE DIS/EN TURN-ON THRESHOLD vs JUNCTION TEMPERATURE 1.10 8.8 VDIS(EN) – DIS/EN Turn-On Threshold – mV 1.09 VBP – Regulator Voltage – V 8.6 1.08 ILOAD = 0 mA 8.4 1.07 1.06 8.2 1.05 8.0 7.8 1.06 1.03 ILOAD = 5 mA 1.02 7.6 1.01 7.4 -40 -25 -10 5 20 35 50 65 80 95 110 125 TJ – Junction Temperature – ° C 1.
TPS40210-Q1, TPS40211-Q1 SLVS861D – AUGUST 2008 – REVISED APRIL 2010 www.ti.com DEVICE INFORMATION TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION BP 9 O Regulator output. Connect a 1.0-mF bypass capacitor from this pin to GND. COMP 4 O Error amplifier output. Connect control loop compensation network between COMP pin and FB pin. DIS/EN 3 I Disable/enable. Pulling this pin high places the part into a shutdown mode. Shutdown mode is characterized by a very low quiescent current.
TPS40210-Q1, TPS40211-Q1 www.ti.
TPS40210-Q1, TPS40211-Q1 SLVS861D – AUGUST 2008 – REVISED APRIL 2010 www.ti.com APPLICATION INFORMATION Minimum On-Time and Off-Time Considerations The TPS40210 has a minimum off time of approximately 200 ns and a minimum on time of 300 ns. These two constraints place limitations on the operating frequency that can be used for a given input-to-output conversion ratio. See Figure 2 for the maximum frequency that can be used for a given duty cycle.
TPS40210-Q1, TPS40211-Q1 www.ti.com SLVS861D – AUGUST 2008 – REVISED APRIL 2010 Setting the Oscillator Frequency The oscillator frequency is determined by a resistor and capacitor connected to the RC pin of the TPS40210. The capacitor is charged to a level of approximately VVDD/20 by current flowing through the resistor and is then discharged by a transistor internal to the TPS40210. The required resistor for a given oscillator frequency is found from either Figure 1 or Equation 5. RT = 1 5.
TPS40210-Q1, TPS40211-Q1 SLVS861D – AUGUST 2008 – REVISED APRIL 2010 www.ti.com VDD Amplitude > VIN 8 VIN + 20 RRC Duty Cycle < 50% RC Q R Q CLK + 1 Frequency > Controller Frequency + CRC S 150 mV GND 5 TPS40210/11 UDG-08064 Figure 21.
TPS40210-Q1, TPS40211-Q1 www.ti.com SLVS861D – AUGUST 2008 – REVISED APRIL 2010 The load current overcurrent threshold is set by proper choice of RISNS. If the converter is operating in discontinuous mode the current sense resistor is found in Equation 6. RISNS = fSW ´ L ´ VISNS(oc) 2 ´ L ´ fSW ´ IOUT(oc) ´ (VOUT + VD - VIN ) (6) If the converter is operating in continuous conduction mode RISNS can be found in Equation 7.
TPS40210-Q1, TPS40211-Q1 SLVS861D – AUGUST 2008 – REVISED APRIL 2010 www.ti.com Since the slope compensation ramp must be at least half, and preferably equal to the down slope of the current sense waveform seen at the pulse-width modulator, a maximum value is placed on the current sense resistor when operating in continuous mode at 50% duty cycle or greater. For design purposes, some margin should be applied to the actual value of the current sense resistor.
TPS40210-Q1, TPS40211-Q1 www.ti.com SLVS861D – AUGUST 2008 – REVISED APRIL 2010 point of zero volts. It cannot do this, due to the converter architecture. The output voltage starts from the input voltage less the drop across the diode (VIN – VD) and rises from there. The point at which the output voltage starts to rise (t2) is when the VSSE ramp passes the point where it is commanding more output voltage than (VIN – VD). This voltage level is labeled VSSE(1).
TPS40210-Q1, TPS40211-Q1 SLVS861D – AUGUST 2008 – REVISED APRIL 2010 www.ti.com The required capacitance for a given soft start time t3 – t1 in Figure 24 is calculated in Equation 13.
TPS40210-Q1, TPS40211-Q1 www.ti.com SLVS861D – AUGUST 2008 – REVISED APRIL 2010 The capacitor on the SS pin (CSS) also plays a role in overcurrent functionality. It is used as the timer between restart attempts. The SS pin is connected to GND through a resistor, RSS(dchg), when the controller senses an overcurrent condition. Switching stops and nothing else happens until the SS pin discharges to the soft-start reset threshold, VSS(rst).
TPS40210-Q1, TPS40211-Q1 SLVS861D – AUGUST 2008 – REVISED APRIL 2010 www.ti.com BP Regulator The TPS40210 and TPS40211 have an on-board linear regulator that supplies power for the internal circuitry of the controller, including the gate driver. This regulator has a nominal output voltage of 8 V and must be bypassed with a 1-mF capacitor. If the voltage at the VDD pin is less than 8 V, the voltage on the BP pin is also less, and the gate drive voltage to the external FET is reduced from the nominal 8 V.
TPS40210-Q1, TPS40211-Q1 www.ti.com SLVS861D – AUGUST 2008 – REVISED APRIL 2010 Control Loop Considerations There are two methods to design a suitable control loop for the TPS4021x. The first (and preferred, if equipment is available) is to use a frequency-response analyzer to measure the open-loop modulator and power stage gain and to then design compensation to fit that. The usage of these tools for this purpose is well documented with the literature that accompanies the tool and is not discussed here.
TPS40210-Q1, TPS40211-Q1 SLVS861D – AUGUST 2008 – REVISED APRIL 2010 www.ti.
TPS40210-Q1, TPS40211-Q1 www.ti.com SLVS861D – AUGUST 2008 – REVISED APRIL 2010 The error amplifier GBWP will usually be higher, but is ensured by design to be at least 1.5 MHz. If the gain required in Equation 25 multiplied by 10 times the desired control loop crossover frequency, the high-frequency pole introduced by CHF is overridden by the error amplifier capability and the effective pole is lower in frequency.
TPS40210-Q1, TPS40211-Q1 SLVS861D – AUGUST 2008 – REVISED APRIL 2010 www.ti.com VIN IOUT TPS40210/11 1 RC 2 SS 3 DIS/EN L VDD 10 BP 9 GDRV 8 4 COMP ISNS 7 5 FB GND RIFB 6 UDG-07197 Figure 29. Typical LED Drive Schematic The current in the LED string is set by the choice of the resistor RISNS as shown in Equation 31. RIFB = VFB IOUT where • • • 24 RIFB is the value of the current sense resistor for the LED string in Ω. VFB is the reference voltage for the TPS40211 in V (0.260 V typ).
TPS40210-Q1, TPS40211-Q1 www.ti.com SLVS861D – AUGUST 2008 – REVISED APRIL 2010 ADDITIONAL REFERENCES References These references may be found on the web at www.power.ti.com under Technical Documents. Many design tools and links to additional references, may also be found at www.power.ti.com 1. Design and Application Guide for High Speed MOSFET Gate Drive Circuits, SEM 1400, 2001 Seminar Series 2. Designing Stable Control Loops, SEM 1400, 2001 Seminar Series 3.
TPS40210-Q1, TPS40211-Q1 SLVS861D – AUGUST 2008 – REVISED APRIL 2010 www.ti.com DESIGN EXAMPLE 1 12-V to 24-V Non-Synchronous Boost Regulator The following example illustrates the design process and component selection for a 12-V to 24-V non-synchronous boost regulator using the TPS40210 controller. + + Figure 30. TPS40210 Design Example – 8-V to 24-V at 2-A Table 1.
TPS40210-Q1, TPS40211-Q1 www.ti.com SLVS861D – AUGUST 2008 – REVISED APRIL 2010 Table 1. TPS40210 Design Example Specifications (continued) PARAMETER CONDITIONS MIN NOM MAX UNIT 600 kHz SYSTEM CHARACTERISTICS fSW Switching frequency hPK Peak efficiency VIN = 12 V, 0.2 A ≤ IOUT ≤ 2 A 95% h Full load efficiency VIN = 12 V, IOUT = 2 A 94% TOP Operating temperature range 10 V ≤ VIN ≤ 14 V, 0.2 A ≤ IOUT ≤ 2 A 25 °C MECHANICAL DIMENSIONS W Width 1.5 L Length 1.5 h Height 0.
TPS40210-Q1, TPS40211-Q1 SLVS861D – AUGUST 2008 – REVISED APRIL 2010 ILpeak » IOUT(max) 1 - DMAX + (12 )IRIPPLE(Vinmin) = www.ti.com 2 + (12 )0.718 = 6.57 A 1 - 0.673 (39) A 10-mH inductor with a minimum RMS current rating of 6.13 A and minimum saturation current rating of 6.57 A must be selected. A TDK RLF12560T-100M-7R5 7.5-A 10-mH inductor is selected. This inductor power dissipation is estimated by Equation 40. 2 PL » (ILrms ) ´ DCR (40) The TDK RLF12560T-100M-7R5 12.
TPS40210-Q1, TPS40211-Q1 www.ti.com CIN > SLVS861D – AUGUST 2008 – REVISED APRIL 2010 IL(ripple ) 4 ´ VIN(ripple ) ´ fSW ESR < VIN(ripple ) 2 ´ IL(ripple ) = = 1.02 A = 7.0 mF 4 ´ 60mV ´ 600kHz (47) 60mV = 30mW 2 ´ 1.02 A (48) For this design, to meet a maximum input ripple of 60 mV, a minimum 7.0-mF input capacitor with ESR less than 30 mΩ is needed. A 10-mF X7R ceramic capacitor is selected.
TPS40210-Q1, TPS40211-Q1 SLVS861D – AUGUST 2008 – REVISED APRIL 2010 RDS(on ) < PFET = 2 2 ´ (IRMS ) ´ D www.ti.com 0.50 W 2 ´ 6.132 ´ 0.674 = 9.8mW (55) A target MOSFET RDS(on) of 9.8 mΩ is calculated to limit the conduction losses to less than 250 mW. Reviewing 30-V and 40-V MOSFETs, an Si4386DY 9-mΩ MOSFET is selected. A gate resistor was added per Equation 30. The maximum gate charge at Vgs = 8 V for the Si4386DY is 33.2 nC, this implies RG = 3.3 Ω.
TPS40210-Q1, TPS40211-Q1 www.ti.com SLVS861D – AUGUST 2008 – REVISED APRIL 2010 To set the mid-band gain of the error amplifier to KCOMP use Equation 63. R4 = R7 ´ K COMP = R7 51.1kW = = 18.2kW K CO 2.80 (63) R4 = 18.7 kΩ selected. Place the zero at 10th the desired cross-over frequency. C2 = 10 10 = = 2837pF 2p ´ fL ´ R4 2p ´ 30kHz ´ 18.7kW (64) C2 = 2200 pF selected.
TPS40210-Q1, TPS40211-Q1 SLVS861D – AUGUST 2008 – REVISED APRIL 2010 www.ti.com TEST DATA GAIN AND PHASE vs FREQUENCY FET Vds and Vgs VOLTAGES vs TIME 80 180 60 VIN = 8 V VOUT = 24 V IOUT = 2 A 135 40 90 20 45 0 0 Gain -20 -45 -40 -90 -60 -135 -80 100 GDRV (5 V/ div) Phase – ° Gain – dB Phase FET Vds (20 V/ div) -180 1M 1000 10 k 100 k fSW – Frequency – Hz T – Time – 400 ns Figure 31. Figure 32.
TPS40210-Q1, TPS40211-Q1 www.ti.com SLVS861D – AUGUST 2008 – REVISED APRIL 2010 OUTPUT VOLTAGE vs LOAD CURRENT 24.820 VOUT – Output Voltage – V 24.772 24.724 VIN (V) 14 12 8 VIN = 8 V 24.676 24.628 24.580 VIN = 14 V 24.532 VIN = 12 V 24.484 24.436 24.388 24.340 0 0.5 1.0 1.5 2.0 ILOAD – Load Current – A 2.5 Figure 35. List of Materials Table 2. List of Materials, Design Example 1 REFERENCE DESIGNATOR DESCRIPTION SIZE PART NUMBER MANUFACTURER 0.406 x 0.
TPS40210-Q1, TPS40211-Q1 SLVS861D – AUGUST 2008 – REVISED APRIL 2010 www.ti.com DESIGN EXAMPLE 2 12-V Input, 700-mA LED Driver, Up to 35-V LED String Application Schematic L1 VIN C21 C1 GDRV C2 D1 B2100 R2 ISNS C3 R1 R11 C4 VIN R3 D2 C8 1 U1 TPS40211 RC VIN 10 C10 C9 Loop Response Injection R23 C6 R13 R4 DIS/EN C11 2 SS BP 9 3 DIS/EN GDRV 8 4 COMP ISNS 7 5 FB GND 6 GDRV ISNS C6 LEDC LEDC C13 R24 R6 D3 R15 C14 PWM Dimming UDG-08015 Figure 36.
TPS40210-Q1, TPS40211-Q1 www.ti.com SLVS861D – AUGUST 2008 – REVISED APRIL 2010 List of Materials Table 3. List of Materials, Design Example 2 REFERENCE DESIGNATOR TYPE DESCRIPTION SIZE C1, C2 10 mF, 25 V 1206 C3, C4 2.2 mF, 100 V 1210 C5 1 nF, NPO 0603 C6 100 pF, NPO 0603 C8 100 pF 0603 C9 0.1 mF 0603 C10 Capacitor 0.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE MATERIALS INFORMATION www.ti.com 14-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS40210QDGQRQ1 MSOPPower PAD DGQ 10 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 TPS40211QDGQRQ1 MSOPPower PAD DGQ 10 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.
PACKAGE MATERIALS INFORMATION www.ti.com 14-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS40210QDGQRQ1 MSOP-PowerPAD DGQ 10 2500 370.0 355.0 55.0 TPS40211QDGQRQ1 MSOP-PowerPAD DGQ 10 2500 370.0 355.0 55.
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