Datasheet

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FEATURES APPLICATIONS

DESCRIPTION

2 3

5 4

AVIN PVIN

FB GND SW

BOOST

OUT

UDG−04135

TPS40222

0 0.2 0.4 0.6 0.8 1.0

100

1.2 1.4 1.6

LOAD

− Load Current − A

η − Efficiency − %

= 5 V

OUT

= 1.25 V

OUT

= 3.3 V

TPS40222

SLUS642A – OCTOBER 2005 – REVISED JANUARY 2006

1.6-A, 1.25-MHz BUCK CONVERTER IN A 3 mm × 3 mm SON PACKAGE

• Disk Drives

• Input Voltage Range 4.5 V

to 8 V

• Set Top Box

• Output Voltage (0.8 V to 90% V

)

• Point of Load Power

• 0 A to 1.6 A Current Capability

• ASIC Power Supplies

• Fixed 1.25-MHz Switching Frequency

• Reference 0.8 V ±1%

• Internal 250 m Ω N-Channel MOSFET Switch

The TPS40222 is a fixed-frequency, current-mode,

• Current Mode Control with Internal Slope

non-synchronous buck converter optimized for

Compensation

applications powered by a 5-V distributed source.

• Internal Soft-Start

With internally determined operating frequency,

soft-start time, and control loop compensation, the

• Internal Loop Compensation

TPS40222 provides many features with a minimum of

• Short Circuit Protection

external components.

• Thermal Shutdown

The TPS40222 operates at 1.25 MHz and supports

• High Efficiency Up to 92%

up to 1.6-A output loads. The output voltage can be

• Small 3 mm × 3 mm SON Package

programmed to as low as 0.8 V. The TPS40222

utilizes pulse-by-pulse current limit as well as

frequency foldback to protect the converter during a

catastrophic short circuited output condition.

SIMPLIFIED APPLICATION DIAGRAM

TYPICAL EFFICIENCY

LOAD CURRENT

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (28 pages)

PAGE 1
TPS40222 www.ti.com SLUS642A – OCTOBER 2005 – REVISED JANUARY 2006 1.6-A, 1.25-MHz BUCK CONVERTER IN A 3 mm × 3 mm SON PACKAGE FEATURES APPLICATIONS • • • • • • • • • • • • • • • • • Input Voltage Range 4.5 VDC to 8 VDC Output Voltage (0.8 V to 90% VIN) 0 A to 1.6 A Current Capability Fixed 1.25-MHz Switching Frequency Reference 0.
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TPS40222 www.ti.com SLUS642A – OCTOBER 2005 – REVISED JANUARY 2006 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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TPS40222 www.ti.com SLUS642A – OCTOBER 2005 – REVISED JANUARY 2006 ELECTRICAL CHARACTERISTICS TJ = -40°C to 125°C, 4.5 ≤ VAVIN = VPVIN≤ 5.5 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 800 808 UNIT FEEDBACK VOLTAGE TJ = 25°C, No load 792 VFB Feedback voltage -40°C ≤ TJ≤ 125°C, No load, 4.5V ≤ VDD≤ 7 V 788 IFB Feedback input bias current VFB = 0.
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TPS40222 www.ti.com SLUS642A – OCTOBER 2005 – REVISED JANUARY 2006 DRP PACKAGE (BOTTOM VIEW) BOOST 6 1 FB AVIN 5 2 GND PVIN 4 3 SW A. Exposed pad provides a low thermal resistance of θJC= 2°C/W B. Connect exposed pad to GND. Table 1. TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION AVIN 5 I Input power to the control section of the device. Closely bypass this pin to GND with a low ESR ceramic capacitor of 1-µF or greater.
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TPS40222 www.ti.com SLUS642A – OCTOBER 2005 – REVISED JANUARY 2006 SIMPLIFIED BLOCK DIAGRAM BOOST PVIN 6 4 TPS40222 0.5 VREF FB f(VOSC) Oscillator TSD Soft Start 0.8 VREF f(IDRAIN) DC Bias Boost Diode IDRAIN Composite Ramp E/A + + PWM Comparator FB 1 2 MΩ Thermal Shutdown S Q R Q 3 SW 16 pF f(IDRAIN) + AVIN 5 References 0.8 VREF 0.
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TPS40222 www.ti.com SLUS642A – OCTOBER 2005 – REVISED JANUARY 2006 TYPICAL CHARACTERISTICS FEEDBACK VOLTAGE vs JUNCTION TEMPERATURE 803 803 802 802 VFB − Feedback Voltage − V VFB − Feedback Voltage − mV FEEDBACK VOLTAGE vs INPUT VOLTAGE (NO LOAD) 801 800 799 798 801 800 799 798 797 4 5 6 7 8 797 −50 9 −25 0 25 50 75 100 125 TJ − Junction Temperature − °C VIN − Input Voltage − V Figure 1. Figure 2.
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TPS40222 www.ti.com SLUS642A – OCTOBER 2005 – REVISED JANUARY 2006 TYPICAL CHARACTERISTICS (continued) OVERCURRENT vs JUNCTION TEMPERATURE (VIN=5V) 2.9 2.9 2.8 2.8 ICL − Overcurrent − A ICL − Overcurrent − A OVERCURRENT vs INPUT VOLTAGE 2.7 2.6 2.6 2.5 2.5 2.4 4.5 2.7 5.0 5.5 6.0 6.5 2.4 −50 7.0 −25 0 25 50 75 100 125 100 125 TJ − Junction Temperature − °C VIN − Input Voltage − V Figure 5. Figure 6.
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TPS40222 www.ti.com SLUS642A – OCTOBER 2005 – REVISED JANUARY 2006 DETAILED DESCRIPTION The TPS40222 is a fixed frequency PWM controller incorporating an internal high-side MOSFET switch and is intended for non-synchronous converter applications requiring load current of up to 1.6 A. Feedback Control To maintain output voltage regulation, a fixed-frequency, current-mode-control architecture is employed.
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TPS40222 www.ti.com SLUS642A – OCTOBER 2005 – REVISED JANUARY 2006 DETAILED DESCRIPTION (continued) Soft-Start During power-on, the TPS40222 slowly increases the voltage to the non-inverting input to the error amplifier. In this way, the TPS40222 slowly ramps up the output voltage until the voltage on the non-inverting input to the error amplifier reaches 0.8 V. At that time, the voltage at the non-inverting input to the error amplifier remains at 0.8 V.
PAGE 10
TPS40222 www.ti.com SLUS642A – OCTOBER 2005 – REVISED JANUARY 2006 APPLICATION INFORMATION Typical Application VIN C1 6 5 4 BOOST AVIN PVIN C2 TPS40222 FB GND SW 1 2 3 L1 VOUT D1 C3 R1 R2 UDG−04131 Figure 9. Typical Application Voltage Setting The output voltage may be set by knowing that the feedback voltage is 0.8 V and using Equation 3. To determine an output voltage, choose a convenient resistor value for R2 and calculate R1.
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TPS40222 www.ti.com SLUS642A – OCTOBER 2005 – REVISED JANUARY 2006 APPLICATION INFORMATION (continued) Table 2. Capacitor Selection (1) INDUCTOR VALUE (µH) 5-VIN RIPPLE CURRENT (mA) CMIN (µF) (PM > 50° at -40°C) fC (kHz) TJ = -40°C fC(kHz) TJ = 25°C fC(kHz) TJ = 125°C CLEAD VALUE (pF) omitted OUTPUT VOLTAGE VOUT = 3.3 V Not Recommended (2) 1.8 2.2 3.3 340 230 4.7 160 5.
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TPS40222 www.ti.com SLUS642A – OCTOBER 2005 – REVISED JANUARY 2006 Output Stage Component Selection In most applications, the user starts with a known output voltage and current load requirement as shown in Figure 10. PVIN SW TPS40222 4 3 5 2 AVIN VOUT 3.3 V 1.5 A L1 2.2 µH GND BOOST FB 6 R1 31.25 kΩ CLEAD C0 1 + Internal VREF 800 mV R2 10 kΩ UDG−05095 Figure 10. Output Stage As shown in Figure 10, the trimmed reference voltage is internally connected to the error amplifier.
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TPS40222 www.ti.com SLUS642A – OCTOBER 2005 – REVISED JANUARY 2006 Capacitor Selection One constraint on the capacitance is the overshoot allowed by a sudden load change. The worst case for a transient load release occurs at the time when the inductor has just finished a tON pulse. At this point, the inductor is operating at maximum current. When the output load is suddenly removed, all of the inductor current must be absorbed by the output capacitance.
PAGE 14
TPS40222 www.ti.com SLUS642A – OCTOBER 2005 – REVISED JANUARY 2006 These component selection decisions influence the phase margin and hence the stability of the system. For example, raising the output capacitance reduces the system crossover frequency and raises phase margin. Figure 11 illustrates this in a curve that shows phase margin as a function of output capacitance for two widely different inductors. The curves show that beyond a certain point, added capacitance has limited benefit.
PAGE 15
TPS40222 www.ti.com SLUS642A – OCTOBER 2005 – REVISED JANUARY 2006 Input Filter Capacitor (C1) Select a good quality, low ESR ceramic capacitor to bypass the input. For a conservative design, the capacitor should have a ripple current rating equal to the load current of the converter. Boost Capacitor (C2) The boost capacitor is sized to ensure there is enough energy available to turn on the internal MOSFET. For most applications, use a ceramic capacitor with a value between 33 nF and 100 nF.
PAGE 16
TPS40222 www.ti.com SLUS642A – OCTOBER 2005 – REVISED JANUARY 2006 VIN R4 C1 C5 6 5 4 BOOST AVIN PVIN C2 TPS40222 FB GND SW 1 2 3 L1 VOUT R3 C4 D1 C3 R1 R2 UDG−04130 Figure 14.
PAGE 17
TPS40222 www.ti.com SLUS642A – OCTOBER 2005 – REVISED JANUARY 2006 Application Circuit Schematic Figure 15 shows an example of an application incorporating a TPS40222 in a 1.2-V output DC-to-DC converter. Notice the use of parallel capacitors at the input and the output to reduce the effective ESR of the capacitance. +VIN 4.5 V to 5.5 V TP1 1 C1A 22 µF J1 C1B 22 µF C1C 0.1 µF R4 2 GND TP2 C5 1 µF 6 5 4 BOOST AVIN PVIN TPS40222 FB GND SW 1 2 3 C2 33 nF TP3 L1 3.
PAGE 18
TPS40222 www.ti.com SLUS642A – OCTOBER 2005 – REVISED JANUARY 2006 Table 3. List of Materials REFERENCE DESIGNATOR QTY VENDOR PART NUMBER DESCRIPTION VENDOR NOTES C1A, C1B 2 Capacitor, 22 µF ceramic, 1206 Input bypass C1D 1 Capacitor, 0.
PAGE 19
TPS40222 www.ti.com SLUS642A – OCTOBER 2005 – REVISED JANUARY 2006 TYPICAL CHARACTERISTICS SW 2 V/ div VOUT (0.5 V/ div) VIN (1 V/ div) t − Time − 200 µs/div t − Time − 100 ns/div Figure 18. Startup Waveform Figure 19. SW Node Waveform GAIN AND PHASE vs FREQUENCY 180 50 135 40 30 90 20 45 0 10 GAIN 0 −45 −10 −90 −20 −135 −30 100 1k 10 k 100 k Phase − ° Gain − dB PHASE −180 1M f − Frequency − Hz Figure 20.
PAGE 20
TPS40222 www.ti.com SLUS642A – OCTOBER 2005 – REVISED JANUARY 2006 PC BOARD LAYOUT RECOMMENDATIONS Device Pad Design The 6-pin package has an exposed thermal pad intended to help conduct heat out of the package, allowing a higher than otherwise available operating ambient temperature. Place three vias within the pad area, tying them to an analog ground plane. PCB Layout When designing a DC-to-DC converter layout, care must be taken to ensure a noise-free design.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS40222DRPR VSON DRP 6 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS40222DRPT VSON DRP 6 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS40222DRPT VSON DRP 6 250 180.0 12.4 3.3 3.3 1.1 8.0 12.
PAGE 24
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS40222DRPR VSON DRP 6 3000 367.0 367.0 35.0 TPS40222DRPT VSON DRP 6 250 210.0 185.0 35.0 TPS40222DRPT VSON DRP 6 250 210.0 185.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.