Datasheet

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BOOT

HDRV

LDRV/OC

COMP

PGOOD

EN/SS

TPS4030x

1 10BPVDD

PAD

OUT

UDG-09158

OUT

GND

TPS40303, TPS40304, TPS40305

www.ti.com

SLUS964A –NOVEMBER 2009–REVISED AUGUST 2012

3-V TO 20-V INPUT SYNCHRONOUS BUCK CONTROLLER

Check for Samples: TPS40303, TPS40304, TPS40305

FEATURES

CONTENTS

• Input Voltage Range from 3 V to 20 V

Device Ratings 2

• 300 KHz (TPS40303), 600 KHz (TPS40304) and

Electrical Characteristics 3

1.2 MHz (TPS40305) Switching Frequencies

Device Information 8

• High- and Low-Side FET R

DS(on)

Current

Application Information 10

Sensing

Design Examples 14

• Programmable Thermally Compensated OCP

Additional References 24

Levels

• Programmable Soft-Start

• 600 mV, 1% Reference Voltage

APPLICATIONS

• Voltage Feed-Forward Compensation

• POL Modules

• Supports Pre-Biased Output

• Printer

• Frequency Spread Spectrum

• Digital TV

• Thermal Shutdown Protection at 145°C

• Telecom

• 10-Pin 3 mm × 3 mm SON Package with

Ground Connection to Thermal Pad

DESCRIPTION

The TPS4030x is a family of cost-optimized synchronous buck controllers that operate from 3-V to 20-V input.

The controller implements a voltage-mode control architecture with input-voltage feed-forward compensation that

responds instantly to input voltage change. The switching frequency is fixed at 300 KHz, 600 KHz or 1.2 MHz.

Frequency Spread Spectrum feature adds dither to the switching frequency, significantly reducing the peak EMI

noise and making it much easier to comply with EMI standards.

The TPS4030x offers design with a variety of user programmable functions, including soft-start, Over- Current

Protection (OCP) levels, and loop compensation.

OCP level may be programmed by a single external resistor connected from LDRV pin to circuit ground. During

initial power on, the TPS4030x enters a calibration cycle, measures the voltage at the LDRV pin, and sets an

internal OCP voltage level. During operation, the programmed OCP voltage level is compared to the voltage drop

across the low side FET when it is on to determine whether there is an overcurrent condition. The TPS4030x

then enters a shutdown and restart cycle until the fault is removed.

SIMPLIFIED APPLICATION DIAGRAM

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (34 pages)

PAGE 1
TPS40303, TPS40304, TPS40305 www.ti.com SLUS964A – NOVEMBER 2009 – REVISED AUGUST 2012 3-V TO 20-V INPUT SYNCHRONOUS BUCK CONTROLLER Check for Samples: TPS40303, TPS40304, TPS40305 FEATURES CONTENTS 1 • • • • • • • • • • • Input Voltage Range from 3 V to 20 V 300 KHz (TPS40303), 600 KHz (TPS40304) and 1.
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TPS40303, TPS40304, TPS40305 SLUS964A – NOVEMBER 2009 – REVISED AUGUST 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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TPS40303, TPS40304, TPS40305 www.ti.com SLUS964A – NOVEMBER 2009 – REVISED AUGUST 2012 ELECTRICAL CHARACTERISTICS TJ = –40°C to 125°C, VVDD = 12 V, all parameters at zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX TJ = 25°C, 3 V < VVDD < 20 V 597 600 603 –40°C < TJ < 125°C, 3 V < VVDD < 20 V 594 600 606 UNIT VOLTAGE REFERENCE VFB FB input voltage mV INPUT SUPPLY VVDD Input supply voltage range 20 V IDDSD Shutdown supply current VEN/SS < 0.
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TPS40303, TPS40304, TPS40305 SLUS964A – NOVEMBER 2009 – REVISED AUGUST 2012 www.ti.
PAGE 5
TPS40303, TPS40304, TPS40305 www.ti.
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TPS40303, TPS40304, TPS40305 SLUS964A – NOVEMBER 2009 – REVISED AUGUST 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) OCSET CURRENT SOURCE vs JUNCTION TEMPERATURE 72 14 70 13 IOCSET – OCSET Current Source– mA IDD(SD)– Shutdown Current – mA SHUTDOWN CURRENT vs JUNCTION TEMPERATURE 68 66 64 62 60 12 11 10 9 8 7 VVDD = 12 V 58 –40 –25 –10 5 20 35 50 65 80 6 –40 –25 –10 95 110 125 TJ – Junction Temperature – °C 35 50 65 80 95 110 125 Figure 5. Figure 6.
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TPS40303, TPS40304, TPS40305 www.ti.com SLUS964A – NOVEMBER 2009 – REVISED AUGUST 2012 TYPICAL CHARACTERISTICS (continued) ENABLE LOW-LEVEL THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE HIGH-SIDE OVERCURRENT THRESHOLD vs JUNCTION TEMPERATURE 303.0 VIL – Enable Low-Level Threshold Voltage – mV VOCH – High-Side Overcurrent Threshold – mV 600 302.5 302.0 301.5 301.0 300.5 300.
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TPS40303, TPS40304, TPS40305 SLUS964A – NOVEMBER 2009 – REVISED AUGUST 2012 www.ti.com FB COMP PGOOD EN/SS VDD 5 4 3 2 1 8 9 10 SW LDRV/ OC BP Thermal Pad 6 7 BOOT HDRV PIN FUNCTIONS TERMINAL I/O DESCRIPTION NAME NO. BOOT 6 I Gate drive voltage for the high side N-channel MOSFET. A 100 nF capacitor (typical) must be connected between this pin and SW.
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TPS40303, TPS40304, TPS40305 www.ti.com SLUS964A – NOVEMBER 2009 – REVISED AUGUST 2012 TPS4030x BLOCK DIAGRAM + 10 mA Soft Start 0.6 VREF + 12.5% SS SS EN/SS 2 + SD BP 10 COMP 4 FB 6-V Regulator 1 + References OC SD Spread Spectrum Oscillator Clock PWM Logic 5 7 HDRV 8 SW 9 LDRV/OC BP Anti-Cross Conduction and Pre-Bias Circuit + 10 mA 0.6 VREF PGOOD BOOT PWM + SS 6 0.6 VREF BP Calibration Circuit BP 0.6 VREF –12.
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TPS40303, TPS40304, TPS40305 SLUS964A – NOVEMBER 2009 – REVISED AUGUST 2012 www.ti.com APPLICATION INFORMATION Introduction The TPS4030x is a family of cost-optimized synchronous buck controllers providing high-end features to construct high-performance DC/DC converters. Pre-bias capability eliminates concerns about damaging sensitive loads during startup.
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TPS40303, TPS40304, TPS40305 www.ti.com SLUS964A – NOVEMBER 2009 – REVISED AUGUST 2012 Soft-Start Time The soft-start time of the TPS4030x is user programmable by selecting a single capacitor. The EN/SS pin sources 10 µA to charge this capacitor. The actual output ramp-up time is the amount of time that it takes for the 10 µA to charge the capacitor through a 600mV range.
PAGE 12
TPS40303, TPS40304, TPS40305 SLUS964A – NOVEMBER 2009 – REVISED AUGUST 2012 www.ti.com OCP sensing at LDRV is a true inductor valley current detection, using sample and hold.
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TPS40303, TPS40304, TPS40305 www.ti.com SLUS964A – NOVEMBER 2009 – REVISED AUGUST 2012 Power Good The TPS4030x provides an indication that output is good for the converter. This is an open drain signal and pulls low when any condition exists that would indicate that the output of the supply might be out of regulation. These conditions include the following: • VFB is more than ±12.
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TPS40303, TPS40304, TPS40305 SLUS964A – NOVEMBER 2009 – REVISED AUGUST 2012 www.ti.com DESIGN EXAMPLES Design Example 1: Using the TPS40305 for a 12 V to 1.8 V Point-of-Load Synchronous Buck Regulator 12 V to 1.8 V Point-of-Load Synchronous Buck Regulator The following example illustrates the design process and component selection for a 12 V to 1.8 V point-of-load synchronous buck regulator using the TPS40305. Table 1.
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TPS40303, TPS40304, TPS40305 www.ti.com SLUS964A – NOVEMBER 2009 – REVISED AUGUST 2012 Inductor Selection (L1) Synchronous buck power inductors are typically sized for approximately 30% peak-to-peak ripple current (IRIPPLE) Given this target ripple current, the required inductor size can be calculated in Equation 3. L» VIN(max ) - VOUT 0.3 ´ IOUT ´ VOUT 1 14 V - 1.8 V 1.8 V 1 ´ = ´ ´ = 471nH VIN(max ) fSW 0.3 ´ 10A 14 V 1200 kHz (3) Selecting a standard 400-nH inductor value, solve for IRIPPLE =3.
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TPS40303, TPS40304, TPS40305 SLUS964A – NOVEMBER 2009 – REVISED AUGUST 2012 www.ti.com Peak Current Rating of Inductor With output capacitance, it is possible to calculate the charge current during start-up and determine the minimum saturation current rating for the inductor. The start-up charging current is approximated by Equation 9. V ´ COUT 1.8 V ´ 2 ´ 22 mF ICHARGE = OUT = = 0.053 A tSS 1.5ms (9) IL(peak ) = IOUT(max) + 12 IRIPPLE + ICHARGE = 10 A + 12 ´ 3.5 A + 0.053 A = 11.8 A (10) Table 2.
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TPS40303, TPS40304, TPS40305 www.ti.com SLUS964A – NOVEMBER 2009 – REVISED AUGUST 2012 CBP = 100 ´ MAX(QG1,QG2 ) (15) Since Q1 is larger than Q2, and the total gate charge of Q1 is 10 nC, a BP capacitor of 1.0 µF is calculated. A standard value of 1.0 µF is selected to limit noise on the BP regulator. Short Circuit Protection (R11) The TPS40305 uses the negative drop across the low-side FET at the end of the OFF time to measure the inductor current.
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TPS40303, TPS40304, TPS40305 SLUS964A – NOVEMBER 2009 – REVISED AUGUST 2012 www.ti.com GAIN AND PHASE vs FREQUENCY EFFICIENCY vs LOAD CURRENT 100 90 VIN = 8 V 85 135 90 40 Gain – dB 180 20 45 0 0 -20 h – Efficiency – % 60 95 Phase – ° 80 225 Phase VIN = 14 V IOUT = 10 A BW = 82 kHz Phase Margin 55° VIN = 12 V 80 VIN = 14 V 75 70 65 -45 Gain 60 -90 -40 55 -60 0.1 1 10 100 -135 1k 50 0 f – Frequency – kHz 4 2 6 8 10 ILOAD – Load Current – A Figure 15. Figure 16. ..
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TPS40303, TPS40304, TPS40305 www.ti.com SLUS964A – NOVEMBER 2009 – REVISED AUGUST 2012 TPS40305 Design Example List of Materials Table 3. Design Example List of Materials REFERENCE DESIGNATOR QTY VALUE DESCRIPTION SIZE PART NUMBER MFR C1 1 3.
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TPS40303, TPS40304, TPS40305 SLUS964A – NOVEMBER 2009 – REVISED AUGUST 2012 www.ti.com Layout Information 20 Figure 18. Top Copper with Components .. .. Figure 19. Top Internal Copper Layout .. .. Figure 20. Bottom Internal Copper Layout Figure 21.
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TPS40303, TPS40304, TPS40305 www.ti.com SLUS964A – NOVEMBER 2009 – REVISED AUGUST 2012 Design Example 2: A High Current, Low Voltage Design Using the TPS40304 For this 20-A, 12-V to 1.2-V design, the 600kHz, TPS40304 was selected for the balance between small size and high efficiency. System Design Specifications The system design specifications are shown in Table 4. Table 4. Design Example Electrical Characteristics PARAMETER TEST CONDITIONS MIN TYP 8.
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TPS40303, TPS40304, TPS40305 SLUS964A – NOVEMBER 2009 – REVISED AUGUST 2012 www.ti.com EFFICIENCY vs LOAD CURRENT GAIN AND PHASE vs FREQUENCY 100 225 90 80 180 85 60 135 40 90 20 45 0 0 95 VIN = 14 V 80 75 VIN = 12 V 70 Phase – ° Phase Gain – dB h – Efficiency – % VIN = 8 V 65 –20 –45 Gain 60 –90 –40 55 –60 1k 50 0 5 10 15 10 k 100 k –135 1M 20 f – Frequency – Hz ILOAD – Load Current – A Figure 23. 22 Submit Documentation Feedback Figure 24.
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TPS40303, TPS40304, TPS40305 www.ti.com SLUS964A – NOVEMBER 2009 – REVISED AUGUST 2012 Figure 25.
PAGE 24
TPS40303, TPS40304, TPS40305 SLUS964A – NOVEMBER 2009 – REVISED AUGUST 2012 www.ti.com Design Example 3: A Synchronous Buck Application Using the TPS40303 This example illustrates a 3.3-V/5-V/12-V to 0.6-V at 10-A synchronous buck application using the TPS40303 switching at 300 kHz. Schematic + + Figure 26. TPS40303 Design Example Schematic Typical Performance Characteristics A typical efficiency graph for this design example using the TPS40303 is shown in Figure 27.
PAGE 25
TPS40303, TPS40304, TPS40305 www.ti.com SLUS964A – NOVEMBER 2009 – REVISED AUGUST 2012 EFFICIENCY vs LOAD CURRENT 100 LINE AND LOAD REGULATION 601 VIN = 3.3 V 90 600 VIN = 3.3 V VOUT – Output Voltage – V 80 h – Efficiency – % 70 VIN = 5 V 60 50 VIN = 12 V 40 30 599 598 597 VIN = 5 V 596 595 20 VIN = 12 V 594 10 593 0 2 0 4 8 6 0 10 2 4 6 8 10 ILOAD – Load Current – A ILOAD – Load Current – A Figure 27. Figure 28.
PAGE 26
TPS40303, TPS40304, TPS40305 SLUS964A – NOVEMBER 2009 – REVISED AUGUST 2012 www.ti.com REVISION HISTORY Changes from Original (November 2009) to Revision A • 26 Page Changed minimum controllable pulse width max value from 100 to 70 ...............................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
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PACKAGE MATERIALS INFORMATION www.ti.com 7-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing TPS40303DRCR SON DRC 10 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS40303DRCT SON DRC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS40304DRCR SON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 7-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS40303DRCR SON DRC 10 3000 367.0 367.0 35.0 TPS40303DRCT SON DRC 10 250 210.0 185.0 35.0 TPS40304DRCR SON DRC 10 3000 367.0 367.0 35.0 TPS40304DRCR SON DRC 10 3000 367.0 367.0 35.0 TPS40304DRCT SON DRC 10 250 210.0 185.0 35.0 TPS40305DRCR SON DRC 10 3000 367.0 367.0 35.
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