Datasheet

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0.4

0.8

1.3

Time

Voltage (V)

EN1/SS1

SS_INT

SS SS

t I

600 mV

TPS40322

www.ti.com

SLUSAF8D –JUNE 2011–REVISED JANUARY 2014

Startup and Shutdown

Startup Sequence

When the ENx/SSx pin is pulled below 0.3 V, the respective channel is disabled. When ENx/SSx is released, the

controller starts automatically and an internal 40-µA current source begins to charge the external soft-start

capacitor. When the voltage across the soft-start capacitor is over 0.7 V, the internal BP regulator is enabled.

The ENx/SSx voltage is clamped to 1.3 V while waiting for signals indicating that BP6, VDD, and the oscillator

clock are good. After all the signals are confirmed, ENx/SSx is discharged to 0.4 V with a 140-µA current source,

and then charged again with the internal 10-µA current source. The operation is described by the waveform

shown in Figure 20. V

SS_INT

is an internal signal level shifted from ENx/SSx and then connected to the non-

inverting terminal of the error amplifier.

The soft-start time is determined by the internal charge current and the external capacitance. The actual output

ramp-up time is the time for the internal current source to charge the capacitor through a 600 mV range. There is

some initial lag time due to the offset (800 mV typical) from the actual ENx/SSx pin voltage to V

SS_INT

. The soft-

start sequence takes place in a closed loop fashion, meaning that the error amplifier controls the output voltage

constantly during the soft-start period and the feedback loop is never open (as occurs in duty cycle limit soft-start

designs). The error amplifier has two non-inverting inputs, one connected to the 600-mV reference voltage, and

the other connected to the offset V

SS_INT

. The error amplifier controls the FB pin to the lower of these two

voltages. As the voltage on the ENx/SSx pin ramps up past approximately 1.4 V (800 mV offset voltage plus the

600 mV reference voltage), the 600 mV reference voltage becomes the dominant input and the converter has

reached its final regulation voltage.

Equation 4 shows how to calculate the soft start capacitance.

where

• C

is the soft start capacitance

connected to ENx/SSx pin

• t

is the desired soft-start time

• I

is the internal soft-start current

(typically 10 µA) (4)

Figure 20. EN/SS Start-Up Waveform

Pre-Biased Output Start-Up

The TPS40322 contains a circuit that prevents current from being pulled from the output during the start-up

sequence in a pre-biased output condition. There are no PWM pulses until the internal soft-start voltage rises

above the error amplifier input (FBx pin), if the output is pre-biased. Once the soft-start voltage exceeds the error

amplifier input, the device slowly initiates synchronous rectification by starting the synchronous rectifier with a

narrow on-time. It then increments that on-time on a cycle-by-cycle basis until it coincides with the time dictated

by (1-D), where D is the duty cycle of the converter. This approach prevents the sinking of current from a pre-

biased output, and ensures the output voltage start-up and ramp-to-regulation sequences are smooth and

controlled.

DESIGN NOTE

During the soft-start sequence, when the PWM pulse width is shorter than the minimum

controllable on-time, which is generally caused by the PWM comparator and gate driver

delays, pulse skipping may occur and the output might show larger ripple voltage.