Datasheet

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TPS40322

SLUSAF8D –JUNE 2011–REVISED JANUARY 2014

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LAYOUT CONSIDERATIONS

Power Stage

A synchronous BUCK power stage has two primary current loops. The input current loop carries high AC

discontinuous current while the output current loop carries high DC continuous current. The input current loop

includes the input capacitors, the main switching MOSFET, the inductor, the output capacitors and the ground

path back to the input capacitors. To maintain the loop as small as possible, it is generally good practice to place

some ceramic capacitance directly between the drain of the main switching MOSFET and the source of the

synchronous rectifier (SR) through a power ground plane directly under the MOSFETs. The output current loop

includes the SR MOSFET, the inductor, the output capacitors, and the ground return between the output

capacitors and the source of the SR MOSFET. As with the input current loop, the ground return between the

output capacitor ground and the source of the SR MOSFET should be routed under the inductor and SR

MOSFET to minimize the power loop area. The SW node area should be as small as possible to reduce the

parasitic capacitance and minimize the radiated emissions. The gate drive loop impedance (HDRV-gate-source-

SW and LDRV-gate-source- GND) should be kept to as low as possible. The HDRV and LDRV connections

should widen to 20 mils as soon as possible out from the device pin.

Device Peripheral

The TPS40322 provides separate signal ground (AGND) and power ground (PGND1 and PGND2) pins. It is

required to properly separate the circuit grounds. The return path for the pins associated with the power stage

should be through PGND. The other pins (especially for those sensitive pins such as FB1, FB2, RT, ILIM1, and

ILIM2) should be through the low noise AGND. The AGND and PGND planes are suggested to be connected at

the output capacitor with single 20-mil trace. A minimum 0.1-µF ceramic capacitor must be placed as close to the

VDD pin and AGND as possible with at least 15-mil wide trace from the bypass capacitor to the AGND. A

minimum value of 3.3-µF ceramic capacitor should be connected from BP6 to PGND, placed as close to the BP6

pin as possible. When DCR sensing method is applied, the sensing resistor should be placed close to the SW

node and connected to the inductor with a Kelvin connection. The sensing traces from the power stage to the

chip should be away from the switching components. The sensing capacitor should be placed very close to the

CS+ and CS- pins for each output. The frequency setting resistor should be placed as close to RT pin and AGND

as possible. In two-phase mode, the ILIM2/VSNS and EN2/SS2/GSNS pins should be directly connected to the

point of load where the voltage regulation is required. A parallel pair of 10-mil traces connects the regulated

voltage back to the chip. They should be away from the switching components. The PowerPAD™ should be

electrically connected to AGND.

PowerPAD™ Layout

The PowerPAD™ package provides low thermal impedance for heat removal from the device. The PowerPAD™

derives its name and low thermal impedance from the large bonding pad on the bottom of the device. The circuit

board must have an area of solder-tinned-copper underneath the package. The dimensions of this area depend

on the size of the PowerPAD™ package.

Thermal vias connect this area to internal or external copper planes and should have a drill diameter sufficiently

small so that the via hole is effectively plugged when the barrel of the via is plated with copper. This plug is

needed to prevent wicking the solder away from the interface between the package body and the solder-tinned

area under the device during solder reflow. Drill diameters of 0.33 mm (13 mils) works well when 1-oz. copper is

plated at the surface of the board while simultaneously plating the barrel of the via. If the thermal vias are not

plugged when the copper plating is performed, then a solder mask material should be used to cap the vias with a

diameter equal to the via diameter plus 0.1 mm minimum. This capping prevents the solder from being wicked

through the thermal vias and potentially creating a solder void under the package. Refer to PowerPAD™

Thermally Enhanced Package (TI LIterature Number SLMA002) for more information on the PowerPAD™

package.