Datasheet

TPS40322
SLUSAF8D –JUNE 2011–REVISED JANUARY 2014 www.ti.com
ELECTRICAL CHARACTERISTICS
T
J
= –40°C to 125°C, V
VDD
= 12 V, R
RT
= 40 kΩ, f
SW
= 500 kHz (unless otherwise noted),
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
INPUT SUPPLY
VDD Input voltage range 3 20 V
IDD
SDN
Shutdown V
ENx/SSx
= 0 V 200 250 µA
IDD
Q
Quiescent, non-switching V
FB
= 0.65 V, ENx/SSx float 6 8 mA
UVLO
UVLO Minimum turn-on voltage 1.21 1.24 1.27 V
UVLO
HYS
Hysteresis current 13 15 17 μA
BP REGULATOR
BP Regulator voltage 7 V ≤ V
VDD
≤ 20 V 6.2 6.5 6.8 V
V
DO
Regulator dropout voltage I
BP
= 25 mA, V
VDD
= 3 V 50 100 mV
I
BP
Regulator continuous current limit
(1)
100 mA
V
BPUVLO
Regulator output UVLO 2.40 2.70 2.95 V
V
BPUVLO-HYS
Regulator output UVLO hysteresis 180 210 250 mV
OSCILLATOR/ RAMP GENERATOR
100 1000 kHz
f
SW
Oscillator frequency
R
RT
= 40 kΩ 450 500 550 kHz
V
RAMP
Ramp amplitude (peak-to-peak) 3 V < V
VDD
< 20 V VDD/8.5 V
V
VAL
Valley voltage 0.85 V
f
SYNC
SYNC frequency range 200 2000 kHz
t
PW(sync)
SYNC input minimum pulse width 100 ns
V
H(sync)
Rising edge threshold to set sync pulse 2 V
V
L(sync)
Falling edge threshold to reset sync pulse 0.8 V
f
MASTER
Master clock frequency 200 2000 kHz
Percent of master frequency for –20% 20%
Δf
SYNC
synchronization
Master 0°/180° phase shift 0.5 V
V
PHSET
Slave 0°/180° phase shift 0.6 2.0 V
Slave 90°/270° phase shift 2.1 V
PWM
PWM(off) Minimum PWM off-time 90 130 ns
t
ON(min)
Minimum controllable pulse width See
(1)
90 ns
t
DEAD
Output driver dead time HDRV off to LDRV on 20 35 40 ns
t
DEAD
Output driver dead time LDRV off to HDRV on 20 35 40 ns
ERROR AMPLIFIER AND VOLTAGE REFERENCE
0°C < T
J
< 70°C 597 600 603 mV
V
FB
FB input voltage
–40°C < T
J
< 125°C 594 600 606
I
FB
FB input bias current 20 75 nA
GBWP Unity gain bandwidth See
(1)
24 MHz
AVOL Open loop gain See
(1)
80 dB
I
OH
High-level output current 3 mA
I
OL
Low-level output current 9 mA
(1) Specified by design. Not production tested.
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