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SLUS489 − OCTOBER 2001

 

 

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FEATURES

D High-Frequency (2-MHz) Voltage Mode PWM

Controller

D 1.8-V to 9.0-V Input Voltage Range

D 0.8-V to 8.0-V Output Voltage Range (Higher in

Non-Synchronous Boost Topology)

D High-Efficiency Buck, Boost, SEPIC or

Flyback (Buck-Boost) Topology

D Synchronous Rectification for High-Efficiency

D Drives External MOSFETs for High-Current

Applications

D Synchronizable Fixed-Frequency PWM or

Automatic Pulsed Frequency Modulation

(PFM) Mode

D Built-In Soft-Start

D User Programmable Discontinuous or

Continuous Conduction Mode

D Selectable Pulse-by-Pulse Current Limiting or

Hiccup Mode Protection

TYPICAL BUCK APPLICATION

APPLICATIONS

D Networking Equipment

D Servers

D Base Stations

D Cellular Telephones

D Satellite Telephones

D GPS Devices

D Digital Still and Handheld Cameras

D Personal Digital Assistants (PDAs)

DESCRIPTION

The TPS43000 is a high-frequency, voltage-mode,

synchronous PWM controller that can be used in buck,

boost, SEPIC, or flyback topologies. This highly flexible,

full-featured controller is designed to drive a pair of

external MOSFETs (one N-channel and one

P-channel), enabling it for use with a wide range of

output voltages and power levels. With an automatic

PFM mode, a shutdown current of less than 1 µA, a

sleep-mode current of less than 100 µA and a full

operating current of less than 2 mA at 1 MHz, it is ideal

for building highly efficient, dc-to-dc converters.

The TPS43000 operates over a wide input voltage

range of 1.8 V to 9.0 V. Typical power sources are

distributed power systems, two to four nickel or alkaline

batteries, or one to two lithium-ion cells. It can be used

to generate regulated output voltages from as low as

0.8 V to 8 V or higher. It operates either in a

fixed-frequency mode, where the user programs the

frequency (up to 2 MHz), or in an automatic PFM mode.

In the automatic mode, the controller goes to sleep

when the inductor current goes discontinuous, and

wakes up when the output voltage has fallen by 2%. In

this hysteretic mode of operation, very high efficiency

can be maintained over a very wide range of load

current. The device can also be synchronized to an

external clock source using the dual function SYNC/SD

input pin.

UDG−01036

SYNC/SD

CCS

CCM

BUCK

PFM*

COMP FB

TPS43000

VIN

VOUT

NDRV

GND

PDRV

SWP

SWN

RTN

VIN

VOUT

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (31 pages)

PAGE 1
SLUS489 − OCTOBER 2001 FEATURES APPLICATIONS D High-Frequency (2-MHz) Voltage Mode PWM D D D D D D D D D D D D D D D D D Controller 1.8-V to 9.0-V Input Voltage Range 0.8-V to 8.
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SLUS489 − OCTOBER 2001 description (continued) The TPS43000 features a selectable two-level current-limit circuit which senses the voltage drop across the energizing MOSFET. The user can select either pulse-by-pulse current limiting or hiccup mode overcurrent protection. The TPS43000 also features a low-power (LP) mode (which reduces gate charge losses in the N-channel MOSFET at high input/output voltages), undervoltage lockout, and soft-start.
PAGE 3
SLUS489 − OCTOBER 2001 electrical characteristics over recommended operating junction temperature range, TA = −40_C to 85_C for the TPS43000, RT = 75 kΩ (500 kHz), VIN = VP = 3.5 V, VOUT = 3.1 V, COMP/FB pins shorted, BUCK-configured, TA = TJ (unless otherwise noted) VIN PARAMETER Start-up voltage Undervoltage lockout (UVLO) hysteresis TEST CONDITIONS VP = VOUT = 3.5 V, No MOSFETs connected No load MIN TYP MAX 1.45 1.65 1.85 V 60 150 300 mV SYNC/SD = 1.
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SLUS489 − OCTOBER 2001 electrical characteristics over recommended operating junction temperature range, TA = −40_C to 85_C for the TPS43000, RT = 75 kΩ (500 kHz), VIN = VP = 3.5 V, VOUT = 3.1 V, COMP/FB pins shorted, BUCK-configured, TA = TJ (unless otherwise noted) soft-start PARAMETER Soft-start time TEST CONDITIONS MIN TYP MAX RT = 37.5 kΩ (1 MHz) 1.0 3.0 6.0 RT = 75 kΩ (500 kHz) 2.0 5.5 12.0 RT = 150 kΩ (250 kHz) 4.0 10.5 24.
PAGE 5
SLUS489 − OCTOBER 2001 electrical characteristics over recommended operating junction temperature range, TA = −40_C to 85_C for the TPS43000, RT = 75 kΩ (500 kHz), VIN = VP = 3.5 V, VOUT = 3.1 V, COMP/FB pins shorted, BUCK-configured, TA = TJ (unless otherwise noted) PWM PARAMETER TEST CONDITIONS BUCK threshold voltage BUCK pull-down current BUCK maximum duty cycle MIN TYP MAX 0.4 0.7 1.0 V 0.5 1.
PAGE 6
SLUS489 − OCTOBER 2001 electrical characteristics over recommended operating junction temperature range, TA = −40_C to 85_C for the TPS43000, RT = 75 kΩ (500 kHz), VIN = VP = 3.5 V, VOUT = 3.1 V, COMP/FB pins shorted, BUCK-configured, TA = TJ (unless otherwise noted) NDRV PARAMETER VIN driven rise time VIN driven fall time TEST CONDITIONS CO = 1 nF, VOUT = 3.1 V VP = VIN = 5 V, VP = VIN = 5 V, VOUT = 3.
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SLUS489 − OCTOBER 2001 Terminal Functions TERMINAL NAME BUCK CCM NO. 5 4 DESCRIPTION I/O I Input pin to select topology. Connect this pin to VIN for a buck converter, ground it for a boost or SEPIC. This configures the logic to the two gate drive outputs, and controls DMAX. This pin has a weak internal pulldown. I Input pin determines whether or not the lZERO comparator allows discontinuous conduction mode operation.
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SLUS489 − OCTOBER 2001 functional block diagram + 300 mV VOUT 10 VINEST + R + VBEST 800 mV VREF 1.246 V VIN 9 2.75 V 784 mV VDD UVLO + DELAY TO ZERO 200 mV 1.6 R VINEST REFGOOD REFBAD 3.6 V + VIN VOUT CCM 4 RECTOFF (STOP SWITCH RECTIFICATION) + 10 mV GND 12 SWP 15 + LEB IZERO Q R Q LPM + VOUT VIN 3−BIT UP COUNTER S Q R Q SLEEP LPM PFM 6 RESET 784 mV + VINEST FB 8 ERROR AMPLIFIER + + 800 mV REFGOOD HICCUP COMP 3.
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SLUS489 − OCTOBER 2001 APPLICATION INFORMATION general information The TPS43000 is a high-frequency, synchronous PWM controller optimized for distributed power, or battery-powered applications where size and efficiency are of critical importance. It includes high-speed, high-current MOSFET drivers for those applications requiring low RDS(on) external MOSFETs. (See functional block diagram).
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SLUS489 − OCTOBER 2001 APPLICATION INFORMATION fixed PWM with forced CCM (PFM and CCM tied to VIN) CCM is forced under all operating conditions in this mode. The synchronous rectifier turns on shortly after the energizing MOSFET turns off and remains on until just prior to the start of the next clock cycle when the energizing MOSFET turns on. The user should design the converter to operate in CCM over its entire operating range in order to prevent the inductor current from going negative.
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SLUS489 − OCTOBER 2001 APPLICATION INFORMATION When the RDS(on) of the MOSFET is used as the sense element, several issues arise. Before the IZERO comparator is enabled, the MOSFET must be fully enhanced, and the drain-to-source voltage must be allowed to settle. The TPS43000 has an internal circuit that enables the IZERO comparator approximately 40 ns after the rectifier MOSFET is enhanced.
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SLUS489 − OCTOBER 2001 APPLICATION INFORMATION synchronization and shutdown The TPS43000 incorporates a dual function synchronization and shutdown pin. It may be used to synchronize the TPS43000’s switching frequency to an external clock, or to shutdown the device entirely. To synchronize the internal clock to an external source, the SYNC/SD pin must be driven high, greater than 1.6 V. The circuitry synchronizes to the rising edge of the input.
PAGE 13
SLUS489 − OCTOBER 2001 APPLICATION INFORMATION start-up and soft-start The TPS43000 incorporates an UVLO circuit that disables the output drivers when the voltage at the VIN pin is below 1.65 V. In order to prevent the converter from oscillating during low input voltage startup, the UVLO circuit is designed with 200 mV of hysteresis and the converter remains on until VIN drops below 1.45 V. The TPS43000 has a built-in soft-start that varies as a function of the switching frequency.
PAGE 14
SLUS489 − OCTOBER 2001 APPLICATION INFORMATION error amplifier The TPS43000 uses voltage mode control for each of the topologies. The output voltage is sensed and fed back to the FB pin (inverting input) and compared to an internal 800 mV reference connected to the non-inverting input. The difference (i.e. error voltage), is amplified by the internal error amplifier.
PAGE 15
SLUS489 − OCTOBER 2001 APPLICATION INFORMATION The frequency of the poles and zeros are defined by the following equations: zeros f z1 + (2p 1 R2 C1) f z2 [ (2p 1 R1 C3) f p1 + (2p 1 R3 C3) f p2 [ (2p 1 R2 C2) (6) , assuming R1 ơ R3 (7) poles (8) , assuming C1 ơ C2 (9) In voltage mode control, the buck, boost, flyback, and SEPIC toplogies all have a 2nd order double-pole LC filter characteristic when operated in CCM.
PAGE 16
SLUS489 − OCTOBER 2001 APPLICATION INFORMATION With voltage-mode control, the closed-loop design goal for each of the topologies with the Type III error amplifier compensation is to set the crossover frequency above the resonant frequency of the LC filter (prevents filter oscillations during a transient response), but below the lowest possible RHP zero frequency. This is accomplished by setting the two zeros in the compensation network before the LC double pole frequency.
PAGE 17
SLUS489 − OCTOBER 2001 APPLICATION INFORMATION design examples: buck, boost, non-synchronous boost, flyback, and SEPIC buck converter The buck topology is simple and efficient, and should be used whenever the desired output voltage is less than the minimum input voltage. Figure 4 shows the TPS43000 in a typical (750 kHz) buck converter with an input voltage range of 3.0 V to 9.0 V, an output voltage of 2.7 V, and a load current from 0 A to 2 A. L1 3.
PAGE 18
SLUS489 − OCTOBER 2001 APPLICATION INFORMATION where fSW is the switching frequency, L is the inductor value, and D is the duty cycle. The duty cycle for a buck converter is defined as: V D + OUT V IN (18) Note that in these equations the voltage drop across the rectifier has been neglected. boost converter The boost topology is simple and efficient, and should be used whenever the desired output voltage is greater than the maximum input voltage.
PAGE 19
SLUS489 − OCTOBER 2001 APPLICATION INFORMATION For a boost converter, the average output current is related to the peak inductor current by the following equation: I pk + ǒVOUT ǒh I V OUT Ǔ Ǔ ) IN ǒ2 ǒVIN f SW D Ǔ Ǔ L (19) where fSW is the switching frequency, L is the inductor value, and D is the duty cycle. The duty cycle for a boost converter is defined as: D+ ǒVOUT * VINǓ V OUT (20) Note that in these equations the voltage drop across the rectifier has been neglected.
PAGE 20
SLUS489 − OCTOBER 2001 APPLICATION INFORMATION L1 3.3 µH D1 ZHCS1000 VIN VOUT C7 100 µF C8 120 µF R5 1 kΩ TPS43000 1 SYNC/SD SWN 16 2 CCS SWP 15 3 RT 4 CCM 5 BUCK 6 PFM NDRV 11 7 COMP VOUT 10 8 FB R4 49.9 kΩ C2 330 pF C1 3300 pF R2 30.1 kΩ VP 14 PDRV 13 GND 12 VIN C3 680 pF VIN C6 0.47 µF 9 R3 24.9 kΩ Q2 Si9804DY VIN VIN C5 0.47 µF C4 0.47 µF R1 750 kΩ RBIAS 53.6 kΩ UDG−01038 Figure 6. 12-V Output Non-Synchronous Boost Topology 20 www.ti.
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SLUS489 − OCTOBER 2001 APPLICATION INFORMATION flyback converter A flyback converter (750 kHz) using the TPS43000 is shown in Figure 7. It uses a standard two-winding coupled inductor with a 1:1 turns ratio. The advantage of this topology is that the output voltage can be greater or less than the input voltage. For example, this is ideal for generating 3.3 V from a lithium-ion cell. D1 L1B ZHCS1000 (OPTIONAL) VIN L1A 3.
PAGE 22
SLUS489 − OCTOBER 2001 I pk + ǒVOUT ǒh I V OUT Ǔ Ǔ IN ) ǒ2 ǒVIN f D Ǔ SW Ǔ L (21) where fSW is the switching frequency, L is the inductor value, and D is the duty cycle. The duty cycle for a flyback converter is defined as: D+ V OUT ǒVIN ) VOUTǓ (22) Note that in these equations the voltage drop across the rectifier has been neglected. SEPIC converter The TPS43000 may also be used in the SEPIC topology.
PAGE 23
SLUS489 − OCTOBER 2001 APPLICATION INFORMATION The SEPIC topology offers the same advantage of the flyback in that it can generate an output voltage that is greater or less than the input voltage. However, it also offers improved efficiency. Although it requires an additional capacitor in the power stage, it greatly reduces ripple current in the input capacitor and improves efficiency by transferring the energy in the leakage inductance of the coupled inductor to the output.
PAGE 24
SLUS489 − OCTOBER 2001 APPLICATION INFORMATION Table 1. SMT Commercial Inductor Manufacturers Coilcraft Inc. (800) 322−2645 1102 Silver Lake RD, Cary, IL 60013 Coiltronics Inc. (407) 241−7876 6000 Park of Commerce Blvd, Boca Raton, FL 33487 Dale Electronics, Inc. (605) 665−9301 East Highway 50, Yankton, SD 57078 Pulse Engineering Ltd.
PAGE 25
SLUS489 − OCTOBER 2001 APPLICATION INFORMATION grounding A ground plane is highly recommended. The GND pin of the TPS43000 should be close to the source of the N-channel MOSFET, the input filter capacitor, and the output filter capacitor.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS43000PWR Package Package Pins Type Drawing TSSOP PW 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 12.4 Pack Materials-Page 1 6.9 B0 (mm) K0 (mm) P1 (mm) 5.6 1.6 8.0 W Pin1 (mm) Quadrant 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS43000PWR TSSOP PW 16 2000 367.0 367.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.