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SLUS564C − JULY 2003 − REVISED OCTOBER 2008

     

     

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FEATURES

Wide Input Voltage Range: 4.5-V to 28-V

D Selectable Dual and DDR Modes

D Selectable Fixed Frequency Voltage Mode

D Advanced Power Good Logic Monitors both

Channels

D Selectable Autoskip Mode

D Integrated Boot Strap Diodes

D 180° Phase Shift Between Channels

D Integrated 5-V, 60-mA Regulator

D Input Feedforward Control

D 1% Internal 0.85-V Reference

D R

DS(on)

Overcurrent Detection (4200 ppm/°C)

D Integrated OVP, UVP and Power Good Timers

D 30-pin TSSOP Package

APPLICATIONS

Notebook Computers System Bus and I/O

D DDR I or DDR II Termination

DESCRIPTION

The TPS51020 is a multi-function dual-

synchronous step-down controller for notebook

system power. The part is specifically designed

for high performance, high efficiency applications

where the loss associated with a current sense

resistor is unacceptable. The TPS51020 utilizes

feed forward voltage mode control to attain high

efficiency without sacrificing line response.

Efficiency at light load conditions can be

maintained high as well by incorporating autoskip

operation. A selectable, Suspend to RAM (STR)

supported, DDR option provides a one chip

solution for all switching applications from

5-V/3.3-V supply to a complete DDR termination

solution.

ORDERING INFORMATION

TA PLASTIC TSSOP (DBT)

−40°C to 85°C

TPS51020DBT

−40°C to 85°C

TPS51020DBTR (T&R)

SIMPLIFIED

APPLICATION

DIAGRAM

UDG−03144

VO1

TPS51020

COMP2

SSTRT2

PGOOD

VO2

ENBL2

ENBL1

REF_X

GND

DDR

VO1_VDDQ

SSTRT1

COMP1

REG5_IN

VREG5

VBST2

OUT2_U

LL2

OUT2_D

OUTGND2

VIN

TRIP1

OUTGND1

OUT1_D

LL1

OUT1_U

VBST1

INV2

INV1

SKIP

VIN

VO2

VIN

VO2

VO1

VIN

VO1

VO2

VREG5

TRIP2

VREG5

EXT_5V

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (28 pages)

PAGE 1
SLUS564C − JULY 2003 − REVISED OCTOBER 2008 FEATURES D Wide Input Voltage Range: 4.5-V to 28-V D Selectable Dual and DDR Modes D Selectable Fixed Frequency Voltage Mode D Advanced Power Good Logic Monitors both D D D D D D D D D Channels Selectable Autoskip Mode Integrated Boot Strap Diodes 180° Phase Shift Between Channels Integrated 5-V, 60-mA Regulator Input Feedforward Control 1% Internal 0.
PAGE 2
SLUS564C − JULY 2003 − REVISED OCTOBER 2008 ABSOLUTE MAXIMUM RATINGS Over operating free-air temperature range unless otherwise noted. All voltage values are with respect to the network ground terminal unless otherwise noted. (1) TPS51020 Input voltage range Ouput voltage range VBST1, VBST2 −0.3 to 35 VBST1, VBST2 (with respect to LL ) −0.3 to 7 VIN, TRIP1, TRIP2, ENBL1, ENBL2, DDR −0.3 to 30 SKIP, INV1, INV2 −0.
PAGE 3
SLUS564C − JULY 2003 − REVISED OCTOBER 2008 TSSOP (0.5 mm) DBT PACKAGE (TOP VIEW) INV1 COMP1 SSTRT1 SKIP VO1_VDDQ DDR GND REF_X ENBL1 ENBL2 VO2 PGOOD SSTRT2 COMP2 INV2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 VBST1 OUT1_U LL1 OUT1_D OUTGND1 TRIP1 VIN TRIP2 VREG5 REG5_IN OUTGND2 OUT2_D LL2 OUT2_U VBST2 ELECTRICAL CHARACTERISTICS TA = −40°C to 85°C, 4.5 V < VIN < 20 V, CVIN = 0.1 µF, CVREG5 = 2.2 µF, CREF_X = 0.01 µF, PGOOD = 0.
PAGE 4
SLUS564C − JULY 2003 − REVISED OCTOBER 2008 ELECTRICAL CHARACTERISTICS (continued) TA = −40°C to 85°C, 4.5 V < VIN < 20 V, CVIN = 0.1 µF, CVREG5 = 2.2 µF, CREF_X = 0.01 µF, PGOOD = 0.
PAGE 5
SLUS564C − JULY 2003 − REVISED OCTOBER 2008 ELECTRICAL CHARACTERISTICS (continued) TA = −40°C to 85°C, 4.5 V < VIN < 20 V, CVIN = 0.1 µF, CVREG5 = 2.2 µF, CREF_X = 0.01 µF, PGOOD = 0.2 V, ENBLx = DDR = VIN, INVx = COMPx, RSSTRTx = OPEN, TRIP1 = TRIP2 = VIN, LLx = GND, VBSTx = LLx+5, C(OUTx_U, OUTx_D)=1 nF, REG5_IN = 0V, GND = OUTGNDx = 0 V, VO1_VDDQ = VO2 = 0 V (unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 0.84 0.85 0.86 V 0 |5.0| mV 2 3 0.
PAGE 6
SLUS564C − JULY 2003 − REVISED OCTOBER 2008 ELECTRICAL CHARACTERISTICS (continued) TA = −40°C to 85°C, 4.5 V < VIN < 20 V, CVIN = 0.1 µF, CVREG5 = 2.2 µF, CREF_X = 0.01 µF, PGOOD = 0.2 V, ENBLx = DDR = VIN, INVx = COMPx, RSSTRTx = OPEN, TRIP1 = TRIP2 = VIN, LLx = GND, VBSTx = LLX+5, C(OUTx_U, OUTx_D)=1 nF, REG5_IN = 0V, GND = OUTGNDx = 0 V, VO1_VDDQ = VO2 = 0 V (unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX 1.8 2.3 2.
PAGE 7
SLUS564C − JULY 2003 − REVISED OCTOBER 2008 ENBL1 ENBL1 ENBL2 ENBL2 fSW − Switching Frequency − kHz 470 fSW − Switching Frequency − kHz 470 360 270 360 270 5.0 3.6 C 1.5 1.2 A B 0 SSTRT2 5.0 3.6 C 1.5 1.2 0 A B t0 t1 t2 t3 360 270 270 5.0 SSTRT1 t4 VSSTRT − Soft-Start Voltage − V VSSTRT − Soft-Start Voltage − V 270 360 t5 SSTRT1 3.6 1.5 1.2 0 SSTRT2 5.0 3.6 1.5 1.
PAGE 8
SLUS564C − JULY 2003 − REVISED OCTOBER 2008 TERMINAL FUNCTIONS (continued) TERMINAL NAME PGOOD NO. 12 I/O DESCRIPTION O Power good output. This is an open drain pull-down pin for power good. It remains low during soft-start until both outputs become within ±7.5%. If INV1 or INV2 is out of regulation, or VREG5V goes under UVLO then this pin goes low. The internal delay timer counts 2048 clks at low to high (by design, no delay for high to low).
PAGE 9
SLUS564C − JULY 2003 − REVISED OCTOBER 2008 FUNCTIONAL BLOCK DIAGRAM Shows Channel 1 (VO1_VDDQ) and the supporting circuitry. www.ti.
PAGE 10
SLUS564C − JULY 2003 − REVISED OCTOBER 2008 APPLICATION INFORMATION PWM OPERATION The PWM control block utilizes a fixed-frequency, feed-forward, voltage-mode control scheme with a wide-bandwidth, low-impedance output error amplifier as the voltage servo control block. This scheme allows the highest efficiency down conversion while maintaining excellent line regulation and fast transient response.
PAGE 11
SLUS564C − JULY 2003 − REVISED OCTOBER 2008 APPLICATION INFORMATION SKIP MODE OPERATION If the SKIP pin is set HIGH, the SMPS operates in the fixed PWM mode. While a LOW signal is applied, the controller operates in autoskip mode. In the autoskip mode, the operation changes from constant frequency PWM mode to an energy-saving skip mode automatically by detecting the edge of discontinuous current mode.
PAGE 12
SLUS564C − JULY 2003 − REVISED OCTOBER 2008 APPLICATION INFORMATION 5-V LINEAR REGULATOR (VREG5) The VREG5 voltage is the bias for all the low voltage circuitry in the TPS51020 as well as the DC boost voltage for the MOSFET gate drivers. Total available current is 60 mA. Bypass this pin to GND by 4.7-µF. The under voltage lockout (UVLO) circuit monitors the output of this regulator to protect internal circuitry from low input voltages.
PAGE 13
SLUS564C − JULY 2003 − REVISED OCTOBER 2008 APPLICATION INFORMATION ENABLE AND SOFT-START Each SMPS is switched into standby mode separately by grounding the corresponding ENBLx pin. The 5-V supply is enabled if either the DDR, ENBL1 or ENBL2 pin(s) goes high ( >2.2 V). Softstart of each SMPS is achieved by slowly ramping the error amplifier reference voltage by following a buffered version of the SSTRTx pin voltage.
PAGE 14
SLUS564C − JULY 2003 − REVISED OCTOBER 2008 APPLICATION INFORMATION 10-V N-CHANNEL FET BIAS or (VOUT1)/2 VTT VOLTAGE REFERENCE (REF_X) TPS51020’s REF_X provides two functions depending on the operational mode. One is a linear regulator that supply 10-V for FET switch biasing in the dual mode, the other is VTT reference voltage in the DDR mode. If DDR is high ( > 2.
PAGE 15
SLUS564C − JULY 2003 − REVISED OCTOBER 2008 APPLICATION INFORMATION If one channel is enabled in the period between T0 and T1, (the other channel’s ramp time plus delay time,) the PGOOD delay counter restarts counting softstart finish after the last channel has finished softstart. Enabling after T1 is ignored by PGOOD until the channel finishes its softstart. If either of the SMPS output goes out by ± 7.5% or UVLO is detected while ENBLx is high, PGOOD pulls low.
PAGE 16
SLUS564C − JULY 2003 − REVISED OCTOBER 2008 APPLICATION INFORMATION OVERCURRENT PROTECTION Overcurrent protection (OCP) is achieved by comparing the drain to source voltage of the high-side and low-side MOSFET to a set point voltage. This voltage appears at the TRIPx pin and is defined by the conversion voltage, typically VIN, minus the I × R drop of the ITRIP current flowing through the external resistor connected to the conversion voltage.
PAGE 17
SLUS564C − JULY 2003 − REVISED OCTOBER 2008 APPLICATION INFORMATION D The output voltage sensing trace and the feedback components should be as short as possible and be isolated from the power components and traces. D The low pass filter for VIN should be placed close to the TPS51020 and be referenced to signal GND. D The bootstrap capacitor CBST (connected from VBST to LL) should be placed close to the TPS51020. D VREG5 requires at least 4.
PAGE 18
SLUS564C − JULY 2003 − REVISED OCTOBER 2008 APPLICATION INFORMATION VBAT 8 V to 20 V C01a 22u GND C12 R101 R12 R01 100k R101 C14 R04 49.7k 3900p 1.8k R02 330 100k R102 Q01 C02 6800p 2.2ux2 15 L01 C08 Q02 1 INV1 2 COMP1 3 SSTRT1 4 SKIP 5 VO1_VDDQ 10k C15 100k 0.01u 6 DDR 7 GND 8 REF_X (10V_REF ) TPS51020 C04a R09 VBST1 30 OUT1_U 29 LL1 28 C20 5V_X Q11 R200 GND R13 51k R201 R16 18k R14 C27 0 0 18k 51k C01c Q12 2.
PAGE 19
SLUS564C − JULY 2003 − REVISED OCTOBER 2008 APPLICATION INFORMATION VBAT 8 V to 20 V C01a GND C12 R12 R01 C14 R02 R101 Q01 C02 4700p 1.2k 100k 7.62k 4700p 2.2ux2 15 R04 L01 4.7k C08 Q02 2.5V_OUT 5.6u C04b 0.1u R102 R03 3.9k C15 100k 0.01u (VO1_VDDQ/2_REF ) 1 INV1 2 COMP1 3 SSTRT1 4 SKIP 5 VO1_VDDQ 6 DDR 7 GND 8 REF_X TPS51020 9 ENBL1 10 ENBL2 11 VO2 12 PGOOD 13 SSTRT2 C19 0.
PAGE 20
SLUS564C − JULY 2003 − REVISED OCTOBER 2008 TYPICAL CHARACTERISTICS SHUTDOWN CURRENT vs JUNCTION TEMPERATURE SUPPLY CURRENT vs JUNCTION TEMPERATURE 140 2.5 VENBLx − VDDR = 0 V REG5V_IN = Open IVIN(SHTDWN) − Shutdown Current − nA IVIN − Input Supply Current − mA VVIN = 12 V 2.0 1.5 1.0 0.5 −50 0 50 100 120 100 80 60 40 20 0 −50 150 0 TJ − Junction Temperature − °C −2.50 25 −2.45 ISSQ − SSRTx Charge Current − µA ITRIPSINK − TRIP1 Sink Current − µA VTRIP − VVIN = 0.
PAGE 21
SLUS564C − JULY 2003 − REVISED OCTOBER 2008 TYPICAL CHARACTERISTICS OSCILLATOR FREQUENCY vs JUNCTION TEMPERATURE SOFTSTART TIME vs SOFTSTART CAPACITANCE 500 100 k VVIN = 12 V fOSC − Oscillator Frequency − kHz VVIN = 12 V TA = 25°C tSS − Softstart Time − µs 10 k 1k 100 10 100 10 1k 10 k fOSC(HI) 400 fOSC(TYP) 350 300 fOSC(LO) 250 200 −50 1 1 450 100 k 0 CSSTRT − Softstart Capacitance − pF Figure 12 150 OVERVOLTAGE PROTECTION THRESHOLD vs JUNCTION TEMPERATURE 900 1400 V
PAGE 22
SLUS564C − JULY 2003 − REVISED OCTOBER 2008 TYPICAL CHARACTERISTICS VREG5 OUTPUT VOLTAGE vs VREG5 OUTPUT CURRENT 5.2 VVIN = 12 V TA = 25°C VVREG5 − VREG5 Output Voltage − V 5.1 VOUT1 50 mV/div 5.0 4.9 4.8 4.7 4.6 IOUT1 2 A/div 4.5 fOSC= 290 kHz VIN = 20 V, VOUT1 = 2.5 V 1 A ≤ IOUT1 ≤ 6 A, 1A/ms 4.4 4.3 0 −20 −40 −60 −80 −100 t − Time − 100 ms / div IVREG − VREG5 Output Current − mA Figure 16 VOUT1 1 V/div Figure 17.
PAGE 23
SLUS564C − JULY 2003 − REVISED OCTOBER 2008 TYPICAL CHARACTERISTICS VVIN = 8 V VDDQ (1 V/div) ENBL1 5 V/div Efficiency − % ENBL2 5 V/div VDDQ Disabled S5 VVIN = 20 V VTT Disabled S3 VOUT2 2 V/div VOUT1 2 V/div VTT (1 V/div) fOSC = 290 kHz VVO1 = 5 V t − Time − 5 ms / div t − Time − 5 ms / div Figure 20. Soft-Stop Figure 21.
PAGE 24
SLUS564C − JULY 2003 − REVISED OCTOBER 2008 PWM MODE EFFICIENCY vs OUTPUT CURRENT AUTOSKIP MODE EFFICIENCY vs OUTPUT CURRENT 100 100 VVIN = 8 V VVIN = 8 V 80 80 Efficiency − % Efficiency − % VVIN = 12 V 60 40 VVIN = 20 V VVIN = 20 V 40 0.1 fOSC = 290 kHz VVO1 = 2.5 V fOSC = 290 kHz VVO1 = 2.5 V 1 10 IOUT − Output Current − A Figure 24 24 VVIN = 12 V 20 20 0 0.01 60 0 0.01 0.1 1 IOUT − Output Current − A Figure 25 www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.