Datasheet

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FEATURES DESCRIPTION

APPLICATIONS

SKIPSEL

TONSEL

PGOOD1

EN1

EN5

EN3

PGOOD2

EN2

TPS51120RHB

(QFN−32)

VBST1

DRVH1

LL1

DRVL1

VBST2

DRVH2

LL2

DRVL2

PGND2

VO2

COMP2

VFB2

GND

VREF2

VFB1

COMP1

VO1

CS2

VREG3

V5FILT

V5REG

VIN

CS1

PGND1

C30

VO1

5V/6A

IRF7832

IRF7821

−

VO1_GND

PGND1

VBAT

VO2

3.3V/6A

IRF7832

IRF7821

−VO2_GND

PGND2

VBAT

GND

PowerPAD

R50

5.1

V5FILT

EN_1

P_GOOD1

P_GOOD2

EN_2

EN_LDO5

EN_LDO3

GND

R11

100 kΩ

C10

20 µF

4.7 µH

C1B

150 µF

C1A

150 µF

C11

0.1 µF

C31

1 nF

R21

100 kΩ

C21

0.1 µF

C10

20 µF

2.2 µH

C2A

150 µF

C2B

150 µF

R22

3.3 kΩ

R12

3.6 kΩ

C51

1 µF

C50

10 µF

C30

10 µF

UDG−05074

TPS51120

SLUS670B – JULY 2005 – REVISED FEBRUARY 2007

DUAL CURRENT MODE, SYNCHRONOUS STEP-DOWN CONTROLLER WITH 100-mA

STANDBY REGULATORS FOR NOTEBOOK SYSTEM POWER

• 3.3-V and 5-V 100-mA Bootstrapped Standby

The TPS51120 is a highly sophisticated dual current

Regulators with Independent Enables

mode synchronous step-down controller. It is a full

featured controller designed to run directly off a

• Selectable D-CAP

Mode Enables Fast

three- or four-cell Li-ion battery and provide

Transient Response Less than 100 ns

high-power and 5-V and/or 3.3-V standby regulation

• Selectable Low Ripple Current Mode

for all the downstream circuitry in a notebook

• Less than 1% Internal Reference Accuracy

computer system. High current, 100-mA, 5-V or

3.3-V on-board linear regulators have glitch-free

• Selectable PWM-only/Auto-skip Modes

switch over function to SMPS and can be kept alive

• Low-side R

DS(on)

Loss-less Current Sensing

independently during standby state. The

• R

SENSE

Accurate Current Sense Option

pseudo-constant frequency adaptive on-time control

scheme supports full range of current mode

• Internal Soft-start and Integrated V

OUT

operation including simplified loop compensation,

Discharge Transistors

ceramic output capacitors as well as seamless

• Integrated 2-V Reference

transition to reduced frequency operation at

• Adaptive Gate Drivers with Integrated Boost

light-load condition. Optional D-CAP™ mode

Diode

operation optimized for SP-CAP or POSCAP output

capacitors allows further reduction of external

• Power Good for Each Channel with Delay

compensation parts. Dynamic UVP supports VIN line

Timer

sag without latch off by hitting 5V UVP. No negative

• Fault Disable Mode

voltage appears at output voltage node during

• Supply Input Voltage Range: 4.5 V to 28 V

UVLO, UVP, and OCP, OTP or loss of VIN.

The TPS51120 32-pin QFN package is specified

from –40 ° C to 85 ° C ambient temperature.

• Notebook Computers System Bus and I/O

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

D-CAP is a registered trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (40 pages)

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TPS51120 www.ti.com SLUS670B – JULY 2005 – REVISED FEBRUARY 2007 DUAL CURRENT MODE, SYNCHRONOUS STEP-DOWN CONTROLLER WITH 100-mA STANDBY REGULATORS FOR NOTEBOOK SYSTEM POWER FEATURES • • • • • • • • • • • • • DESCRIPTION 3.
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TPS51120 www.ti.com SLUS670B – JULY 2005 – REVISED FEBRUARY 2007 ORDERING INFORMATION (1) (2) TA PACKAGE -40°C to 85°C PLASTIC QUAD FLAT PACK (QFN) (1) (2) ORDERABLE PART NUMBER TPS51120RHBT TPS51120RHBR PINS 32 OUTPUT SUPPLY MINIMUM ORDER QUANTITY Tape-and-reel 250 Tape-and-reel 3000 ECO PLAN Green (RoHS and no Sb/Br) All packaging options have Cu NIPdAu lead/ball finish.
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TPS51120 www.ti.com SLUS670B – JULY 2005 – REVISED FEBRUARY 2007 DISSIPATION RATINGS PACKAGE TA < 25°C POWER RATING (W) DERATING FACTOR ABOVE TA = 25°C (W/°C) TA = 85°C POWER RATING (W) 32-pin QFN (1) 2.6 0.026 1.0 QFN (2) 2.9 0.029 1.2 32-pin (1) (2) JEDEC standard PCB. Enhanced thermal conductance by 3 x 3 thermal vias beneath thermal pad. RECOMMENDED OPERATING CONDITIONS MIN MAX 4.5 5.5 VBST1, VBST2 -0.1 34 VBST1, VBST2 wrt LL -0.1 5.5 VIN, EN5 -0.
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TPS51120 www.ti.
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TPS51120 www.ti.com SLUS670B – JULY 2005 – REVISED FEBRUARY 2007 ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range, VVIN = 12 V, VVREG5 = VV5FILT = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX IVREG3 = 20 mA, 6V < VIN < 28V, TA= 25°C 3.25 3.30 3.35 UNIT VREG3 VOLTAGE VVREG3 VREG3 Output Regulation Voltage IVREG3 = 1 - 50 mA , 6V < VIN < 28V, TA= 0 to 85°C 3.21 3.
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TPS51120 www.ti.
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TPS51120 www.ti.
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TPS51120 www.ti.com SLUS670B – JULY 2005 – REVISED FEBRUARY 2007 DEVICE INFORMATION TERMINAL FUNCTIONS TERMINAL NAME 8 NO. I/O DESCRIPTION Loop compensation pin (error amplifier output). Connect RC from this pin to GND for proper loop compensation with current mode operation. Tie this pin to V5FILT for D-CAP™ mode operation. COMP1 2 O COMP2 7 O CS1 23 I CS2 18 I DRVH1 27 O DRVH2 14 O DRVL1 25 O DRVL2 16 O EN1 29 I EN2 12 I EN3 10 I VREG3, 3.
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TPS51120 www.ti.
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TPS51120 www.ti.
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TPS51120 www.ti.com SLUS670B – JULY 2005 – REVISED FEBRUARY 2007 DETAILED DESCRIPTION PWM Operation The switching mode power supply (SMPS) block of TPS51120 supports an adaptive on time control pulse-width-modulation (PWM). Switching frequency is selectable from four choices for maximum efficiency (5 V/180 kHz, 3.3 V/270 kHz), minimum component size (5 V/380 kHz, 3.3 V/580 kHz) or the other two intermediates.
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TPS51120 www.ti.com SLUS670B – JULY 2005 – REVISED FEBRUARY 2007 DETAILED DESCRIPTION (continued) Adaptive On-Time Control The TPS51120 employs adaptive on time control scheme and does not have a dedicated oscillator on board. However, it works almost constant frequency over the entire input voltage range (pseudo-constant frequency) by feed-forwarding the input and output voltage into the on-time one-shot timer.
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TPS51120 www.ti.com SLUS670B – JULY 2005 – REVISED FEBRUARY 2007 DETAILED DESCRIPTION (continued) Light Load Operation TPS51120 automatically reduces switching frequency at light load condition to maintain high efficiency. This reduction of frequency is achieved smoothly and without an increase in load regulation. Detail operation is described as follows.
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TPS51120 www.ti.com SLUS670B – JULY 2005 – REVISED FEBRUARY 2007 DETAILED DESCRIPTION (continued) 3.3V, 100 mA, LDO and Switchover (VREG3) A 3.3-V, 100-mA linear regulator is integrated as a second regulator in the TPS51120. This LDO provides a handy standby supply for 3.3 V ‘Always On’ voltages in the notebook system. The characteristics of this LDO are identical to the 5V LDO except for the switchover voltage. Apply 10-µF ceramic capacitor from VREG3 to PGND in adjacent to the device.
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TPS51120 www.ti.com SLUS670B – JULY 2005 – REVISED FEBRUARY 2007 DETAILED DESCRIPTION (continued) Soft-Stop Discharge mode or ‘Soft Stop’ is always on during Faults or Disable. In this mode, an event that would cause the switcher to be turned off (EN1 or EN2 low, OVP, UVP, UVLO) causes the output to be discharged through 10-Ω transistor inside the VO terminal. The external rectifying MOSFET is not turned on for the soft off operation to avoid a chance to cause negative voltage at the output.
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TPS51120 www.ti.com SLUS670B – JULY 2005 – REVISED FEBRUARY 2007 DETAILED DESCRIPTION (continued) Undervoltage Protection For under voltage protection (UVP), the TPS51120 monitors VFB voltage. When the VFB voltage is lower than 70% of the target and the UVP comparator output goes high, the internal UVP delay counter begins count. After the 128 clocks, approximately 0.5 ms, TPS51120 latches off both channels as DRVH and DRVL at low.
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TPS51120 www.ti.com SLUS670B – JULY 2005 – REVISED FEBRUARY 2007 DETAILED DESCRIPTION (continued) Table 4. Enable Logic States (VOUT1=5 V, VOUT2=3.3 V) (continued) EN5 (1) EN3 EN1 EN2 VREG5 VREG3 VREF2 (2) SMPS1 SMPS2 High High-to-Low Low High-to-Low LDO 5 V Off Off Off Off High-to-Low High Low Low Off LDO 3.
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TPS51120 www.ti.com SLUS670B – JULY 2005 – REVISED FEBRUARY 2007 DETAILED DESCRIPTION (continued) Table 5. Protection States (VOUT1 = 5 V, VOUT2 = 3.3 V) DRVH1 DRVL1 DRVH2 DRVL2 PGOOD1 PGOOD2 VREG5 VREG3 VREF2 FOR RESTART UVPch1 Low Low Low Low Low/Low LDO 5 V LDO 3.3 V On Toggle EN1 UVPch2 Low Low Low Low Low/Low LDO 5 V LDO 3.3 V On Toggle EN2 OVPch1 Low High Low Low Low/Low LDO 5 V LDO 3.3 V On Toggle EN1 OVPch1 Low Low Low High Low/Low LDO 5 V LDO 3.
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TPS51120 www.ti.com SLUS670B – JULY 2005 – REVISED FEBRUARY 2007 Here, the inductor is located inside the local feedback loop and its inductance does not appear in the small signal model. As a result, a modulated current source including the power inductor can be modeled as a current source with its transconductance of 1/RS and the output capacitor represent the modulator portion. This simplified model is applicable in the frequency space up to approximately a half of the switching frequency.
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TPS51120 www.ti.com SLUS670B – JULY 2005 – REVISED FEBRUARY 2007 2. Choose rectifying (bottom) MOSFET. When RDS(on) sensing scheme is selected, the rectifying MOSFET’s on-resistance is used as this RS so that lower RDS(on) does not always promise better performance. In order to clearly detect inductor current, minimum RS recommended is to give 15 mV or larger ripple voltage with the inductor ripple current. This promises smooth transition from CCM to DCM or vice versa.
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TPS51120 www.ti.com SLUS670B – JULY 2005 – REVISED FEBRUARY 2007 D-CAP™ Mode Operation A buck converter system using D-CAP™ mode can be simplified as shown in Figure 2. Figure 2. Linearizing the Modulator The VO voltage is compare with internal reference voltage after divider resistors (Internal resistor mode. For adjustable mode, the comparison is directly at VFB). The PWM comparator determines the timing to turn on top MOSFET.
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TPS51120 www.ti.com SLUS670B – JULY 2005 – REVISED FEBRUARY 2007 Layout Considerations Certain points must be considered before starting a layout work using the TPS51120. • Connect RC low-pass filter from VREG5 to V5FILT, 1 µF and 5.1 Ω are recommended. Place the filter capacitor close to the device, within 12 mm (0.5 inches) if possible. • VREG5 and VREG3 require at least 4.
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TPS51120 www.ti.com SLUS670B – JULY 2005 – REVISED FEBRUARY 2007 C23 180 pF R24 15 kΩ R25 16.5 kΩ C13 220 pF C22 1 nF C12 2.2 nF R24 33 kΩ 2 1 VO1 10 EN3 3 COMP1 EN_LDO3 EN5 R21 100 kΩ 4 VFB1 9 5 VREF2 COMP2 EN_LDO5 6 GND GND 7 VFB2 8 VO2 GND R15 26.7 kΩ R14 33 kΩ C31 1 nF V5FILT R14 11 kΩ SKIPSEL TONSEL 31 PowerPad GND 11 PGOOD2 P_GOOD2 V5FILT 32 PGOOD1 30 R11 12 mΩ P_GOOD1 VBAT VBAT Q3 IRF7821 L2 1.2 µH VO2 1.5 V/6 A 12 EN2 EN_2 C21 0.
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TPS51120 www.ti.com SLUS670B – JULY 2005 – REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS (continued) VIN STANDBY CURRENT vs INPUT VOLTAGE 140 140 120 120 IIN532 − Standby Current − µA IIN532 − Standby Current − µA VIN STANDBY CURRENT vs JUNCTION TEMPERATURE 100 80 60 40 20 80 60 40 20 0 0 50 100 TJ − Junction Temperature − °C 150 5 Figure 8.
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TPS51120 www.ti.com SLUS670B – JULY 2005 – REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS (continued) NO-LOAD BATTERY CURRENT vs INPUT VOLTAGE CURRENT SENSE CURRENT vs JUNCTION TEMPERATURE 16 0.5 ITRIP − Current Sense Current − µA IBATT − Battery Current − mA 14 0.4 0.3 0.2 0.1 AUTO−SKIP 280 kHz (CH1) 430 kHz (CH2) 12 16 20 VIN − VIN Input Voltage − V 8 6 4 0 −50 24 0 50 100 TJ − Junction Temperature − °C Figure 11. Figure 12.
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TPS51120 www.ti.com SLUS670B – JULY 2005 – REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS (continued) SWITCHING FREQUENCY vs INPUT VOLTAGE 400 SWITCHING FREQUENCY vs INPUT VOLTAGE 400 TONSEL = FLOAT TONSEL = 5 V 350 fSW − Switching Frequency − kHz fSW − Switching Frequency − kHz 350 CH2 300 250 200 CH1 150 100 50 300 CH2 250 200 CH1 150 100 50 0 0 6 10 14 18 24 VIN − VIN Input Voltage − V 28 6 Figure 16.
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TPS51120 www.ti.com SLUS670B – JULY 2005 – REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS (continued) SWITCHING FREQUENCY vs OUTPUT CURRENT SWITCHING FREQUENCY vs OUTPUT CURRENT 400 400 TONSEL = 5 V fSW − Switching Frequency − kHz fSW − Switching Frequency − kHz TONSEL = FLOAT CH2−PWM Only 300 CH2 Auto−skip 200 CH1−PWM Only 100 300 CH2−PWM Only CH2 Auto−skip 200 CH1−PWM Only 100 CH1 Auto−skip CH1 Auto−skip 0 0.001 0.01 0.1 1 0 0.001 10 IOUT − Output Current − A 0.01 0.
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TPS51120 www.ti.com SLUS670B – JULY 2005 – REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS (continued) VREF2 OUTPUT VOLTAGE vs OUTPUT CURRENT 3.340 2.020 3.320 2.015 VREF2 − VREF2 Output Voltage − V VREG3 − VREG3 Output Voltage − V VREG3 OUTPUT VOLTAGE vs OUTPUT CURRENT 3.300 3.280 3.260 3.240 3.220 2.010 2.005 2.000 1.995 1.990 1.985 3.200 0 20 40 60 80 1.980 −100 −80 −60 100 Figure 23. Figure 24. 5-V OUTPUT VOLTAGE vs OUTPUT CURRENT 3.
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TPS51120 www.ti.com SLUS670B – JULY 2005 – REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS (continued) 5-V OUTPUT VOLTAGE vs INPUT VOLTAGE 3.3-V OUTPUT VOLTAGE vs INPUT VOLTAGE 3.32 5.050 VOUT2 − 3.3-V Output Voltage − V VOUT1 − 5-V Output Voltage − V 3.32 5.025 5.000 IO = 6 A 4.975 IO = 0 A 3.31 3.33 IO = 6 A 3.30 4.950 3.27 6 8 10 12 14 16 18 20 22 VIN − VIN Input Voltage − V 24 6 26 8 10 12 14 16 18 20 22 24 26 VIN − VIN Input Voltage − V Figure 27. Figure 28.
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TPS51120 www.ti.com SLUS670B – JULY 2005 – REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS (continued) VOUT2 (100 mV/div) VOUT1 (100 mV/div) IIND (5 A/div) IIND (5 A/div) IOUT2 (5 A/div) IOUT1 (5 A/div) t − Time − 20 µs/div t − Time − 20 µs/div Figure 31. 5-V Load Transient Response Figure 32. 3.3-V Load Transient Response EN1 (5 V/div) EN2 (5 V/div) VO1 (2 V/div) VO2 (2 V/div) PGOOD1 (5 V/div) PGOOD2 (5 V/div) t − Time − 1 ms/div t − Time − 1 ms/div Figure 33.
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TPS51120 www.ti.com SLUS670B – JULY 2005 – REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS (continued) VREG5 (200 mV/div) VREG3 (200 mV/div) VO2 (200 mV/div) VO1 (200 mV/div) t − Time − 1 ms/div t − Time − 1 ms/div Figure 35. 5-V Switchover Waveforms Figure 36. 3.3-V Switchover Waveforms EN1 (5 V/div) EN2 (5 V/div) VO1 (5 V/div) VO2 (5 V/div) PGOOD1 (5 V/div) PGOOD2 (5 V/div) DRVL1 (5 V/div) DRVL2 (5 V/div) t − Time − 1 ms/div t − Time − 1 ms/div Figure 37.
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TPS51120 www.ti.com SLUS670B – JULY 2005 – REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS (continued) GAIN AND PHASE vs FREQUENCY GAIN AND PHASE vs FREQUENCY 80 135 60 40 90 40 90 20 45 20 45 0 0 0 0 −45 Gain −90 −40 −60 −135 −60 10 k 100 k f − Frequency − kHz −180 1M −80 1k −45 Submit Documentation Feedback ° −90 Gain −135 −180 10 k 100 k 1M f − Frequency − kHz Figure 39.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS51120RHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 TPS51120RHBT VQFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS51120RHBR VQFN RHB 32 3000 367.0 367.0 35.0 TPS51120RHBT VQFN RHB 32 250 210.0 185.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.