Datasheet

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FEATURES APPLICATIONS

DESCRIPTION

STANDARD DDR APPLICATION

TPS51200

REFIN

VLDOIN

PGND

VOSNS

VIN

PGOOD

GND

REFOUT

3.3 V

PGOOD

SLP_S3

0.1 mF

VTTREF

VLDOIN

VTT

VDDQ

UDG-08025

TPS51200

SLUS812 – FEBRUARY 2008

www.ti.com

SINK/SOURCE DDR TERMINATION REGULATOR

• Memory Termination Regulator for DDR,

• Input Voltage: Supports 2.5-V Rail and 3.3-V

DDR2, DDR3, and Low Power DDR3/DDR4

Rail

• Notebook/Desktop/Server

• VLDOIN Voltage Range: 1.1 V to 3.5 V

• Telecom/Datacom, GSM Base Station,

• Sink/Source Termination Regulator Includes

LCD-TV/PDP-TV, Copier/Printer, Set-Top Box

Droop Compensation

• Requires Minimum Output Capacitance of

20- µ F (typically 3 × 10- µ F MLCCs) for Memory

The TPS51200 is a sink/source Double Data Rate

Termination Applications (DDR)

(DDR) termination regulator specifically designed for

• PGOOD to Monitor Output Regulation

low input voltage, low-cost, low-noise systems where

• EN Input

space is a key consideration.

• REFIN Input Allows for Flexible Input Tracking

The TPS51200 maintains a fast transient response

Either Directly or Through Resistor Divider

and only requires a minimum output capacitance of

• Remote Sensing (VOSNS) 20 µ F. The TPS51200 supports a remote sensing

function and all power requirements for DDR, DDR2,

• ± 10-mA Buffered Reference (REFOUT)

DDR3, and Low Power DDR3/DDR4 VTT bus

• Built-in Soft Start, UVLO and OCL

termination.

• Thermal Shutdown

In addition, the TPS51200 provides an open-drain

• Meets DDR, DDR2 JEDEC Specifications;

PGOOD signal to monitor the output regulation and

Supports DDR3 and Low-Power DDR3/DDR4

an EN signal that can be used to discharge VTT

VTT Applications

during S3 (suspend to RAM) for DDR applications.

• SON-10 PowerPAD™Package

The TPS51200 is available in the thermally-efficient

SON-10 PowerPAD package, and is rated both

Green and Pb-free. It is specified from -40 ° C to

+85 ° C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2 PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (36 pages)

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TPS51200 www.ti.com SLUS812 – FEBRUARY 2008 SINK/SOURCE DDR TERMINATION REGULATOR FEATURES APPLICATIONS • Input Voltage: Supports 2.5-V Rail and 3.3-V Rail • VLDOIN Voltage Range: 1.1 V to 3.
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TPS51200 www.ti.com SLUS812 – FEBRUARY 2008 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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TPS51200 www.ti.com SLUS812 – FEBRUARY 2008 ELECTRICAL CHARACTERISTICS Over recommended free-air temperature range, VVIN = 3.3 V,VVLDOIN = 1.8 V, VREFIN = 0.9 V, VVOSNS = 0.9 V, VEN = VVIN, COUT = 3 × 10 µF and circuit shown in Section 1. (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT IIN Supply current TA = 25 °C, VEN = 3.3 V, No Load 0.7 1 TA = 25 °C, VEN = 0 V, VREFIN = 0, No Load 65 80 200 400 1 50 µA 0.
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TPS51200 www.ti.com SLUS812 – FEBRUARY 2008 ELECTRICAL CHARACTERISTICS (continued) Over recommended free-air temperature range, VVIN = 3.3 V,VVLDOIN = 1.8 V, VREFIN = 0.9 V, VVOSNS = 0.9 V, VEN = VVIN, COUT = 3 × 10 µF and circuit shown in Section 1. (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 2.2 2.3 2.
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TPS51200 www.ti.com SLUS812 – FEBRUARY 2008 DEVICE INFORMATION DRC PACKAGE TPS51200 (Bottom View) VOSNS 5 PGND 4 VO 3 VLDOIN 2 REFIN 1 6 REFOUT 7 EN 8 GND 9 PGOOD 10 VIN TERMINAL FUNCTIONS TERMINAL NAME NO. I/O EN 7 I For DDR VTT application, connect EN to SLP_S3. For any other application(s), use EN as the ON/OFF function. DESCRIPTION GND 8 – Ground.Signal ground. Connect to negative terminal of the output capacitor. PGND 4 – Power ground output for the LDO PGOOD 9 O PGOOD output.
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TPS51200 www.ti.com SLUS812 – FEBRUARY 2008 FUNCTIONAL BLOCK DIAGRAM REFIN + 1 2.
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TPS51200 www.ti.com SLUS812 – FEBRUARY 2008 DETAILED DESCRIPTION VO SINK/SOURCE REGULATOR The TPS51200 is a sink/source tracking termination regulator specifically designed for low input voltage, low-cost, and low external component count systems where space is a key application parameter. The TPS51200 integrates a high-performance, low-dropout (LDO) linear regulator that is capable of both sourcing and sinking current.
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TPS51200 www.ti.com SLUS812 – FEBRUARY 2008 THERMAL SHUTDOWN The TPS51200 monitors the its junction temperature. If the device junction temperature exceeds its threshold value, (typically 150°C), the VO and REFOUT regulators are both shut off, discharged by the internal discharge MOSFETs. This shutdown is a non-latch protection.
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TPS51200 www.ti.com SLUS812 – FEBRUARY 2008 APPLICATION INFORMATION VIN CAPACITOR Add a ceramic capacitor, with a value between 1.0-µF and 4.7-µF, placed close to the VIN pin, to stabilize the bias supply (2.5- V rail or 3.3- V rail) from any parasitic impedance from the supply. VLDO INPUT CAPACITOR Depending on the trace impedance between the VLDOIN bulk power supply to the device, a transient increase of source current is supplied mostly by the charge from the VLDOIN input capacitor.
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TPS51200 www.ti.com SLUS812 – FEBRUARY 2008 3.3VIN VVDDQ = 1.5 V 0.390 V 0.370 V VLDOIN REFIN REFOUT (VTTREF) EN (S3_SLP) VVO = 0.75 V Tss VO TSS = PGOOD CO x VO IOOCL 2 ms UDG-08021 Figure 1. Typical Timing Diagram for S3 and pseudo-S5 Support 3.3VIN EN VLDOIN REFIN REFOUT (VTTREF) VO tSS determined by the SS time of VLDOIN VVO = 0.75 V PGOOD UDG-08020 2ms Figure 2.
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TPS51200 www.ti.com SLUS812 – FEBRUARY 2008 Output Tolerance Consideration for VTT DIMM Applications The TPS51200 is specifically designed to power up the memory termination rail (as shown in Figure 3). The DDR memory termination structure determines the main characteristics of the VTT rail, which is to be able to sink and source current while maintaining acceptable VTT tolerance. See Figure 4 for typical characteristics for a single memory cell.
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TPS51200 www.ti.com SLUS812 – FEBRUARY 2008 Because VTT accuracy has a direct impact on the memory signal integrity, it is imperative to understand the tolerance requirement on VTT. Based on JEDEC VTT specifications for DDR and DDR2 (JEDEC standard: DDR JESD8-9B May 2002; DDR2 JESD8-15A Sept 2003). VTTREF – 40 mV < VTT < VTTREF + 40 mV, for both dc and ac conditions The specification itself indicates that VTT must keep track of VTTREF for proper signal conditioning.
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TPS51200 www.ti.com SLUS812 – FEBRUARY 2008 Figure 5. Bode Plot for a Typical DDR3 Configuration Figure 5 shows the bode plot simulation for a typical DDR3 configuration of the TPS51200, where: • • • • • • • VIN = 3.3 V VVLDOIN = 1.5 V VVO = 0.75 V IIO = 2 A 3 × 10-µF capacitors included ESR = 2.5 mΩ ESL = 800 pH The unity-gain bandwidth is approximately 1 MHz and the phase margin is 52°. The 0-dB level is crossed, the gain peaks because of the ESL effect. However, the peaking is kept well below 0 dB.
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TPS51200 www.ti.com SLUS812 – FEBRUARY 2008 OUTPUT VOLTAGE vs OUTPUT CURRENT 790 VOUT – Output Voltage – mV VIN = 3.3 V 0°C 780 25°C 770 760 -40°C 750 740 730 720 710 700 -3 DDR3 -40°C 0°C 25°C 85°C -2 85°C -1 0 1 IOUT – Output Current – A 2 3 Figure 6. DC Regulaltion Figure 7. Transient LDO Design Guidelines The minimum input to output voltage difference (headroom) decides the lowest usable supply voltage Gm-driven to drive a certain load.
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TPS51200 www.ti.com VVO – Output Voltage – V SLUS812 – FEBRUARY 2008 1/Gm Inflection Point (between 2 A and 3 A) 1/RDS(on) Overcurrent Limit ISRC - Source Current - A UDG-08026 Figure 8.
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TPS51200 www.ti.com SLUS812 – FEBRUARY 2008 THERMAL DESIGN Because the TPS51200 is a linear regulator, the VO current flows in both source and sink directions, thereby dissipating power from the device. When the device is sourcing current, the voltage difference between VLDOIN and VO times IO (IIO) current becomes the power dissipation as shown in Equation 2.
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TPS51200 www.ti.com SLUS812 – FEBRUARY 2008 For further information regarding the PowerPAD™ package and the recommended board layout, refer to the PowerPAD™ package application note (SLMA002). This document is available at www.ti.com. LAYOUT CONSIDERATIONS Consider the following points before starting the TPS51200 layout design. • The input bypass capacitor for VLDOIN should be placed as close as possible to the pin with short and wide connections.
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TPS51200 www.ti.com SLUS812 – FEBRUARY 2008 TYPICAL CHARACTERISTICS For Figure 10 through Figure 24, 3 × 10-µF MLCCs (0805) are used on the output. OUTPUT VOLTAGE vs OUTPUT CURRENT OUTPUT VOLTAGE vs OUTPUT CURRENT 940 1.30 VIN = 3.3 V 930 VOUT – Output Voltage – mV VOUT– Output Voltage – V 1.28 1.26 -40°C 0°C 1.24 1.22 DDR -40°C 0°C 25°C 85°C 1.20 920 910 -40°C 0°C 900 890 DDR2 -40°C 0°C 25°C 85°C 880 85°C 1.18 85°C 870 -3 -2 -1 0 1 IOUT – Output Current – A 2 -3 3 Figure 11.
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TPS51200 www.ti.com SLUS812 – FEBRUARY 2008 TYPICAL CHARACTERISTICS (continued) For Figure 10 through Figure 24, 3 × 10-µF MLCCs (0805) are used on the output. OUTPUT VOLTAGE vs OUTPUT CURRENT OUTPUT CURRENT vs OUTPUT VOLTAGE 1.30 1.00 VIN = 2.5 V VIN = 2.5 V 1.25 1.20 VOUT – Output Voltage – V VOUT– Output Voltage – V 0.95 1.15 25°C 1.10 1.05 1.00 DDR 85°C -40°C 0°C 25°C 85°C 0.95 -40°C -40°C 0.90 0.85 0.80 85°C DDR2 0.75 0°C 0.90 25°C & 0°C -40°C 0°C 25°C 85°C 0.
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TPS51200 www.ti.com SLUS812 – FEBRUARY 2008 TYPICAL CHARACTERISTICS (continued) For Figure 10 through Figure 24, 3 × 10-µF MLCCs (0805) are used on the output. REFOUT VOLTAGE vs REFOUT CURRENT REFOUT VOLTAGE vs REFOUT CURRENT 1.255 905 1.254 25°C 904 VREFOUT – Output Voltage – mV VREFOUT – Output Voltage – V 25°C 1.253 1.252 1.251 1.250 -40°C 1.249 DDR 1.248 1.
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TPS51200 www.ti.com SLUS812 – FEBRUARY 2008 TYPICAL CHARACTERISTICS (continued) For Figure 10 through Figure 24, 3 × 10-µF MLCCs (0805) are used on the output. DROPOUT VOLTAGE vs OUTPUT CURRENT GAIN AND PHASE vs FREQUENCY 1.25 V 1.6 60 Phase 150 50 1.4 100 0.90 V 1.2 0.6 V 1.0 0.8 0.75 V 30 50 20 0 10 Gain -50 Phase – Degrees 40 Gain – dB VDRPOUT – Output Voltage – V 200 70 1.8 0 0.6 -100 -10 VOUT(V) 0.60 0.75 0.90 1.25 0.4 0.2 -20 -30 1k 0 0 0.5 1.0 1.5 2.0 2.
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TPS51200 www.ti.com SLUS812 – FEBRUARY 2008 DESIGN EXAMPLES Design Example 1 This design example describes a 3.3-VIN, DDR2 Configuration R1 10 kW TPS51200 1 VVDDQ = 1.8 V R2 10 kW VVLDOIN = VVDDQ = 1.8 V C7 10 mF C2 10 mF 3.3 VIN R3 100 kW 2 VLDOIN PGOOD 9 3 VO GND 8 4 PGND EN 7 5 VOSNS REFOUT 6 C6 4.7 mF PGOOD C8 10 mF VVTT = 0.9 V C1 10 mF VIN 10 REFIN C4 1000 pF C3 10 mF SLP_S3 VTTREF C5 0.1 mF UDG-08028 Figure 25. 3.
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TPS51200 www.ti.com SLUS812 – FEBRUARY 2008 Design Example 2 This design example describes a 3.3-VIN, DDR3 Configuration R1 10 kW TPS51200 1 VVDDQ = 1.5 V R2 10 kW VVLDOIN = VVDDQ = 1.5 V C7 10 mF C2 10 mF 3.3 VIN R3 100 kW 2 VLDOIN PGOOD 9 3 VO GND 8 4 PGND EN 7 5 VOSNS REFOUT 6 C6 4.7 mF PGOOD C8 10 mF VVTT = 0.75 V C1 10 mF VIN 10 REFIN C4 1000 pF C3 10 mF SLP_S3 VTTREF C5 0.1 mF UDG-08029 Figure 26. 3.
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TPS51200 www.ti.com SLUS812 – FEBRUARY 2008 Design Example 3 This design example describes a 2.5-VIN, DDR3 Configuration R1 10 kW TPS51200 1 VVDDQ = 1.5 V R2 10 kW VVLDOIN = VVDDQ = 1.5 V C7 10 mF C2 10 mF 2.5 VIN R3 100 kW 2 VLDOIN PGOOD 9 3 VO GND 8 4 PGND EN 7 5 VOSNS REFOUT 6 C6 4.7 mF PGOOD C8 10 mF VVTT = 0.75 V C1 10 mF VIN 10 REFIN C4 1000 pF C3 10 mF SLP_S3 VTTREF C5 0.1 mF UDG-08030 Figure 27. 2.
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TPS51200 www.ti.com SLUS812 – FEBRUARY 2008 Design Example 4 This design example describes a 3.3-VIN, LP DDR3 Configuration R1 10 kW TPS51200 1 VVDDQ = 1.2 V R2 10 kW VVLDOIN = VVDDQ = 1.2 V C7 10 mF C2 10 mF 3.3 VIN R3 100 kW 2 VLDOIN PGOOD 9 3 VO GND 8 4 PGND EN 7 5 VOSNS REFOUT 6 C6 4.7 mF PGOOD C8 10 mF VVTT = 0.6 V C1 10 mF VIN 10 REFIN C4 1000 pF C3 10 mF SLP_S3 VTTREF C5 0.1 mF UDG-08031 Figure 28. 3.
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TPS51200 www.ti.com SLUS812 – FEBRUARY 2008 Design Example 5 This design example describes a 3.3-VIN, DDR3 Tracking Configuration R1 10 kW TPS51200 1 VVDDQ = 1.5 V R2 10 kW VVLDOIN = VVDDQ = 1.5 V C7 10 mF C2 10 mF 3.3 VIN R3 100 kW 2 VLDOIN PGOOD 9 3 VO GND 8 4 PGND EN 7 5 VOSNS REFOUT 6 C6 4.7 mF PGOOD C8 10 mF VVTT = 0.75 V C1 10 mF VIN 10 REFIN C4 1000 pF C3 10 mF VTTREF C5 0.1 mF UDG-08032 Figure 29. 3.
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TPS51200 www.ti.com SLUS812 – FEBRUARY 2008 Design Example 6 This design example describes a 3.3-VIN, LDO Configuration. R1 10 kW TPS51200 2.5 V 1 R2 3.86 kW VVLDOIN = VVLDOREF = 2.5 V C7 10 mF C2 10 mF 3.3 VIN R3 100 kW 2 VLDOIN PGOOD 9 3 VO GND 8 4 PGND EN 7 5 VOSNS REFOUT 6 C6 4.7 mF PGOOD C8 10 mF VVLDO = 1.8 V C1 10 mF VIN 10 REFIN C4 1000 pF C3 10 mF ENABLE REFOUT C5 0.1 mF UDG-08033 Figure 30. 3.
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TPS51200 www.ti.com SLUS812 – FEBRUARY 2008 Design Example 7 This design example describes a 3.3-VIN, DDR3 Configuration with LFP. R1 10 kW TPS51200 1 VVDDQ = 1.5 V R2 10 kW VIN 10 REFIN C4 1000 pF R3 100 kW VVLDOIN = VVDDQ = 1.5 V C7 10 mF 3.3 VIN 2 VLDOIN PGOOD 9 3 VO GND 8 4 PGND EN 7 5 VOSNS REFOUT 6 C6 4.7 mF PGOOD C8 10 mF VVTT = 0.75 V R4(1) C1 10 mF C2 10 mF C3 10 mF SLP_S3 VTTREF C5 0.1 mF C9(1) UDG-08034 Figure 31. 3.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 23-Feb-2014 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS51200DRCR SON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS51200DRCT SON DRC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS51200DRCR SON DRC 10 3000 367.0 367.0 35.0 TPS51200DRCT SON DRC 10 250 210.0 185.0 35.
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