Datasheet

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VTT

VTTSNS

PGND

VTTREF

VDDQSNS

VLDOIN

TPS51206

10 VDD

8GND

PowerPad

VTT

VTTREF

UDG-11024

S3_SLP

S5_SLP

5 V or 3.3 V

Supply

VDDQ

TPS51206

www.ti.com

SLUSAH1A –MAY 2011–REVISED OCTOBER 2013

2-A Peak Sink/Source DDR Termination Regulator with VTTREF Buffered Reference For

DDR2, DDR3 and DDR3L

Check for Samples: TPS51206

FEATURES

APPLICATIONS

• Supply Input Voltage: Supports 3.3-V Rail and

• DDR2/DDR3/DDR3L Memory Power Supplies

5-V Rail

• SSTL_18, SSTL_15, SSTL_135 and HSTL

• VLDOIN Input Voltage Range: VTT+0.4 V to Termination

3.5 V

DESCRIPTION

• VTT Termination Regulator

The TPS51206 is a sink/source double date rate

– Output Voltage Range: 0.5 V to 0.9 V

(DDR) termination regulator with VTTREF buffered

– 2-A Peak Sink and Source Current

reference output. It is specifically designed for low

– Requires Only 10-μF MLCC Output

input voltage, low cost, low external component count

systems where space is a key consideration. The

Capacitor

TPS51206 maintains fast transient response and only

– ±20 mV Accuracy

requires 1 × 10-µF of ceramic output capacitance.

• VTTREF Buffered Reference

The TPS51206 supports a remote sensing function

– VDDQ/2 ± 1% Accuracy

and all power requirements for DDR2, DDR3 and

Low-Power DDR3 (DDR3L) VTT bus. The VTT

– 10-mA Sink/Source Current

current capability is ±2A peak. The TPS51206

• Supports High-Z in S3 and Soft-Stop in S4/S5

supports all of the DDR power states, putting VTT to

with S3/S5 Inputs

High-Z in S3 state (suspend to RAM) and discharging

• Over Temperature Protection

VTT and VTTREF in S4/S5 state (suspend to disk).

• 10-pin 2mm x 2mm SON(DSQ) Package

The TPS51206 is available in 10-pin, 2x2, SON

(DSQ) PowerPAD™ package and specified from

–40°C to 85°C.

SIMPLIFIED APPLICATION

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (25 pages)

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TPS51206 www.ti.com SLUSAH1A – MAY 2011 – REVISED OCTOBER 2013 2-A Peak Sink/Source DDR Termination Regulator with VTTREF Buffered Reference For DDR2, DDR3 and DDR3L Check for Samples: TPS51206 FEATURES APPLICATIONS • • • 1 2 • • • • • • Supply Input Voltage: Supports 3.3-V Rail and 5-V Rail VLDOIN Input Voltage Range: VTT+0.4 V to 3.5 V VTT Termination Regulator – Output Voltage Range: 0.5 V to 0.
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TPS51206 SLUSAH1A – MAY 2011 – REVISED OCTOBER 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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TPS51206 www.ti.com SLUSAH1A – MAY 2011 – REVISED OCTOBER 2013 ELECTRICAL CHARACTERISTICS over operating free-air temperature range, VVDD=5 V, VLDOIN is connected to VDDQSNS, VS3=VS5=5 V (unless otherwise noted) PARAMETER TEST CONDITION MIN TYP MAX UNIT SUPPLY CURRENT μA IVDD(S0) VDD supply current, in S0 TA = 25°C, No load, VS3 = VS5 = 5 V, VVDDQSNS = 1.8 V IVDD(S3) VDD supply current, in S3 TA = 25°C, No load, VS3 = 0 V, VS5 = 5 V, VVDDQSNS = 1.
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TPS51206 SLUSAH1A – MAY 2011 – REVISED OCTOBER 2013 www.ti.com DEVICE INFORMATION DSQ PACKAGE (TOP VIEW) VDDQSNS 1 10 VLDOIN 2 9 S5 VTT 3 8 GND PGND 4 7 S3 VTTSNS 5 6 VTTREF Power PAD VDD PIN FUNCTIONS PIN NAME NO. I/O DESCRIPTION GND 8 – Signal ground PGND 4 – Power GND for VTT LDO S3 7 I S3 signal input S5 9 I S5 signal input VDD 10 I Device power supply input (3.
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TPS51206 www.ti.com SLUSAH1A – MAY 2011 – REVISED OCTOBER 2013 FUNCTIONAL BLOCK DIAGRAM VLDOIN 2 VDDQSNS 1 + 6 VTTREF 3 VTT 4 PGND + GND GND 8 VTTREF Disharge OTP-OK GND VTT Disharge OTP GND VDD 10 + EN-VTTREF 2.9V/2.
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TPS51206 SLUSAH1A – MAY 2011 – REVISED OCTOBER 2013 www.ti.com TYPICAL CHARACTERISTICS 300 5 VDD Shutdown Current (µA) VDD Supply Current (µA) 250 200 150 100 50 0 −40 −25 −10 5 20 35 50 65 80 Junction Temperature (°C) 95 3 2 1 0 −40 −25 −10 110 125 Figure 1. VDD Supply Current vs. Junction Temperature VLDOIN Shutdown Current (µA) 3 2 1 0 −40 −25 −10 5 20 35 50 65 80 Junction Temperature (°C) 95 3 2 1 0 −40 −25 −10 110 125 95 110 125 0.770 TA = −40°C TA = 25°C TA = 85°C 0.
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TPS51206 www.ti.com SLUSAH1A – MAY 2011 – REVISED OCTOBER 2013 TYPICAL CHARACTERISTICS (continued) 0.690 0.615 TA = −40°C TA = 25°C TA = 85°C 0.610 VTTREF Voltage (V) VTTREF Voltage (V) 0.685 0.680 0.675 0.670 0.665 −8 −6 0.605 0.600 0.595 0.590 VVDDQSNS = 1.35 V VVDD = 5 V 0.660 −10 −4 −2 0 2 4 VTTREF Current (mA) 6 8 TA = −40°C TA = 25°C TA = 85°C VVDDQSNS = 1.2 V VVDD = 5 V 0.585 −10 10 −8 Figure 7. VTTREF Load Regulation (0.675 V) 8 10 TA = −40°C TA = 25°C TA = 85°C 0.790 0.
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TPS51206 SLUSAH1A – MAY 2011 – REVISED OCTOBER 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) VVTTREF(10 mV/div) 0.9 V offset VVTTREF(10 mV/div) 0.75 V offset VVTT VVTT (20 mV/div) 0.9 V offset (20 mV/div) 0.75 V offset VVDDQSNS VVDDQSNS (50 mV/div) 1.8 V offset (50 mV/div) 1.5 V offset IVTT (2 A/div) IVTT (2 A/div) Time (200 ms/div) Time (200 ms/div) Figure 13. VTT Load Transient Response (0.9 V) Figure 14. VTT Load Transient Response (0.75 V) VVTTREF(10 mV/div) 0.
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TPS51206 www.ti.com SLUSAH1A – MAY 2011 – REVISED OCTOBER 2013 TYPICAL CHARACTERISTICS (continued) IVTTREF= 0 A S5: Low to High VVTTREF(500 mV/div) VVTTREF(500 mV/div) IVTTREF= 0 A VVTT (500 mV/div) IVTT = 0 A S3: Low to High VVTT (500 mV/div) VS5 (5 V/div) VS5 (5 V/div) VS3 (5 V/div) VS3 (5 V/div) Time (40 ms/div) Time (1 ms/div) Figure 19. Start-Up Waveforms (S5: Low to High) Figure 20. Start-Up Waveforms (S3: Low to High) 0.
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TPS51206 SLUSAH1A – MAY 2011 – REVISED OCTOBER 2013 www.ti.com DETAILED DESCRIPTION VTT SINK/SOURCE REGULATOR The TPS51206 is a sink/source tracking termination regulator specifically designed for low input voltage, low cost, and low external component count systems where space is a key application parameter.
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TPS51206 www.ti.com SLUSAH1A – MAY 2011 – REVISED OCTOBER 2013 VDD VLDOIN VDDQSNS S5 VTTREF S3 VTT UDG-11136 Figure 23.
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TPS51206 SLUSAH1A – MAY 2011 – REVISED OCTOBER 2013 www.ti.com APPLICATION INFORMATION VDD CAPACITOR Add a ceramic capacitor, with a value 0.1 µF (or greater) and X5R grade (or better), placed close to the VDD terminal, to stabilize the bias supply voltage from any parasitic impedance from the power supply rail.
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TPS51206 www.ti.com SLUSAH1A – MAY 2011 – REVISED OCTOBER 2013 THERMAL DESIGN Because the TPS51206 is a linear regulator, the VTT current flows in both source and sink directions, thereby dissipating power from the device. When the device is sourcing current, the voltage difference between VLDOIN and VTT times IVTT (VTT current) current becomes the power dissipation as shown in Equation 1.
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TPS51206 SLUSAH1A – MAY 2011 – REVISED OCTOBER 2013 www.ti.com VDDQ Sense Input VTT Power Supply Input LAYOUT CONSIDERATIONS 0.1 mF 0402 10 mF 0603 VDDQSNS VDD VLDOIN S5 VTT VTT Output GND PGND 10 mF 0603 5-V or 3.3-V Supply Input 0.22 mF 0402 S3 VTTSNS VTTREF VTTREF Output Via to Ground Plane Via for VTTSNS Etch Beneath Component UDG-11135 Figure 25. PCB Layout Guideline Consider the following before beginning a TPS51206 layout design.
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TPS51206 www.ti.com SLUSAH1A – MAY 2011 – REVISED OCTOBER 2013 APPLICATION DIAGRAMS Figure 26 shows an application diagram for a configuration where VLDOIN and VDDQ are connected. TPS51206 VDDQ 1 VDDQSNS 2 VLDOIN VTT 3 VTTSNS 5 VTT C1 10 mF C3 10 mF S3_SLP 7 S3 S5_SLP 9 S5 PGND 4 VTTREF 6 C4 0.22 mF 10 VDD 5 V or 3.3 V C2 0.1 mF VTTREF GND 8 PowerPad UDG-11026 GND Figure 26. VLDOIN=VDDQ Configuration Table 2.
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TPS51206 SLUSAH1A – MAY 2011 – REVISED OCTOBER 2013 www.ti.com Figure 27 shows an application diagram for a configuration where VLDOIN and VDDQ are separated. TPS51206 VDDQ Sense VTT Power 1 VDDQSNS 2 VLDOIN VTT 3 VTTSNS 5 VTT C1 10 mF C3 10 mF S3_SLP 7 S3 S5_SLP 9 S5 5 V or 3.3 V Supply PGND 4 VTTREF 6 C4 0.22 mF 10 VDD C2 0.1 mF VTTREF GND 8 PowerPad UDG-11027 GND Figure 27. VLDOIN Separated from VDDQ Configuration Table 3.
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TPS51206 www.ti.com SLUSAH1A – MAY 2011 – REVISED OCTOBER 2013 REVISION HISTORY Changes from Original (MAY 2011) to Revision A • Page Added minimum and maximum values to the wake up condition of the VDD UVLO threshold voltage specification .........
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 25-Oct-2013 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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PACKAGE MATERIALS INFORMATION www.ti.com 25-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS51206DSQR SON DSQ 10 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2 TPS51206DSQT SON DSQ 10 250 180.0 8.4 2.3 2.3 1.15 4.0 8.
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PACKAGE MATERIALS INFORMATION www.ti.com 25-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS51206DSQR SON DSQ 10 3000 210.0 185.0 35.0 TPS51206DSQT SON DSQ 10 250 210.0 185.0 35.
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