Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - voltage regulators - DC DC switch controllers D-CAP™, D-CAP2™ WQFN 16

VREF

REFIN

GSNS

VSNS

TPS51219RTE

5 6 7 8

PGND

GND

TRIP

COMP

16 15 14 13

BST

MODE

PGOOD

PwrPd

VSNS

GSNS

PGOOD

V5IN

OUT

UDG-11006

TPS51219

www.ti.com

SLUSAG1B –MARCH 2011– REVISED OCTOBER 2011

High Performance, Single-Synchronous Step-Down Controller

with Differential Voltage Feedback

FEATURES

DESCRIPTION

The TPS51219 is a small-sized single buck controller

• Differential Voltage Feedback

with adaptive on-time control. It provides a choice of

• DC Compensation for Accurate Regulation

control modes (D-CAP™ or D-CAP2™) to meet a

• Wide Input Voltage Range: 3 V to 28 V

wide range of system requirements. It is designed for

tight DC regulation requirements such as the VCCIO

• Output Voltage Range: 0.5 V to 2.0 V with

application for Intel

notebooks. The performance

Fixed Options of 1.05 V and 1.00 V

and flexibility of the TPS51219 makes it suitable for

• Wide Output Load Range: 0 A to 20 A+

low output voltage, high current, PC system power

• Adaptive On-Time Modulation with Selectable

rails and similar point-of-load (POL) power supplies.

Control Architecture and Frequency

Differential voltage feedback and the voltage

compensation function combine to provide high

– D-CAP™ Mode at 300 kHz/400 kHz for Fast

precision power to load devices.

Transient Response

A small package, fixed voltage options and minimal

– D-CAP2™ Mode at 500 kHz/670 kHz for

external component count saves cost and space,

Ceramic Output Capacitor

while a dedicated EN pin and pre-set frequency

• 4700 ppm/°C, Low-Side R

DS(on)

Current Sensing

selections minimize design effort. The skip-mode at

• R

SENSE

Accurate Current Sense Option

light load condition, strong gate drivers, and low-side

FET R

DS(on)

current sensing provides high efficiency

• Internal, 1-ms Voltage Servo Softstart

operation over a broad load range. The external

• Built-In Output Discharge

resistor current sense option enables accurate

• Power Good Output

current sensing. The conversion input voltage (the

high-side FET drain voltage) ranges from 3 V to 28 V

• Integrated Boost Switch

and output voltage ranges from 0.5 V to 2.0 V. The

• Built-In OVP/UVP/OCP

device requires an external 5-V supply.

• Thermal Shutdown (Non-latched)

The TPS51219 is available in a 16-pin, QFN package

• 3 mm × 3 mm, 16-Pin, QFN (RTE) Package

and is specified for ambient temperature from -40°C

to 85°C.

APPLICATIONS

• Notebook Computers

• I/O Supplies

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2D-CAP, D-CAP2 are trademarks of Texas Instruments.

3Intel is a registered trademark of Intel.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (37 pages)

PAGE 1
TPS51219 SLUSAG1B – MARCH 2011 – REVISED OCTOBER 2011 www.ti.com High Performance, Single-Synchronous Step-Down Controller with Differential Voltage Feedback FEATURES DESCRIPTION • • • • The TPS51219 is a small-sized single buck controller with adaptive on-time control. It provides a choice of control modes (D-CAP™ or D-CAP2™) to meet a wide range of system requirements. It is designed for tight DC regulation requirements such as the VCCIO application for Intel® notebooks.
PAGE 2
TPS51219 SLUSAG1B – MARCH 2011 – REVISED OCTOBER 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
PAGE 3
TPS51219 SLUSAG1B – MARCH 2011 – REVISED OCTOBER 2011 www.ti.com RECOMMENDED OPERATING CONDITIONS MIN Supply voltage V5 BST –0.1 33.5 BST (1) –0.1 5.5 -3 28 SW (2) –4.5 28 EN, TRIP, MODE –0.1 5.5 REFIN, VSNS, COMP –0.1 3.5 GSNS –0.3 0.3 PGND –0.1 0.1 –3 33.5 DH Output voltage range TA (1) (2) MAX 5.5 SW Input voltage range TYP 4.5 DH (1) –0.1 5.5 DH (2) –4.5 33.5 DL –0.1 5.5 PGOOD –0.1 5.5 VREF –0.1 3.
PAGE 4
TPS51219 SLUSAG1B – MARCH 2011 – REVISED OCTOBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS over operating free-air temperature range, VV5 = 5 V, VMODE= 0 V, VEN= 5 V (unless otherwise noted) PARAMETER TEST CONDITION MIN TYP MAX UNIT SUPPLY CURRENT IV5 V5 supply current TA = 25°C, No load, VEN = 5 V 560 IV5SDN V5 shutdown current TA = 25°C, No load, VEN = 0 V 0.5 Output voltage IVREF = 0 μA wrt GSNS μA 2.
PAGE 5
TPS51219 SLUSAG1B – MARCH 2011 – REVISED OCTOBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range, VV5 = 5 V, VMODE= 0 V, VEN= 5 V (unless otherwise noted) PARAMETER TEST CONDITION MIN TYP MAX UNIT μA LOGIC THRESHOLD IMODE VTHMODE MODE source current MODE threshold voltage VLL EN low-level voltage VLH EN high-level voltage VLHYST EN hysteresis voltage ILLK EN input leakage current 15.6 16.7 17.
PAGE 6
TPS51219 SLUSAG1B – MARCH 2011 – REVISED OCTOBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range, VV5 = 5 V, VMODE= 0 V, VEN= 5 V (unless otherwise noted) PARAMETER TEST CONDITION MIN TYP MAX Wake-up 4.2 4.4 4.5 Shutdown 3.7 3.9 4.
PAGE 7
TPS51219 SLUSAG1B – MARCH 2011 – REVISED OCTOBER 2011 www.ti.com DEVICE INFORMATION VREF PGOOD MODE EN BST RTE PACKAGE (TOP VIEW) 16 15 14 13 1 12 SW TPS51219 VSNS 4 PowerPADTM 10 DL 9 5 6 7 8 PGND 3 GND GSNS 11 DH TRIP 2 COMP REFIN V5 PIN FUNCTIONS PIN NAME BST NO. 13 I/O DESCRIPTION I High-side MOSFET gate driver bootstrap voltage input. Connect a capacitor from the BST pin to the SW pin.
PAGE 8
TPS51219 SLUSAG1B – MARCH 2011 – REVISED OCTOBER 2011 www.ti.com FUNCTIONAL BLOCK DIAGRAM VREF 1 Reference TPS51219 + UV VREFIN – 32% Set_1p05v VREFIN +8/16% EN + 16 PGOOD Delay + GSNS 3 OV VREFIN + 20% + VREFIN – 8/16% COMP 5 VSNS 4 + VREFIN REFIN PWM + OVP Set_resistor _sensing UVP 16.7 mA 2 Soft-Start Set_adj 0.3 V Control Mode On-Time Current Sense Selection + Control Logic Set_adj Discharge + 15 MODE 13 BST Set_1p05v VBG 11 DH 2.
PAGE 9
TPS51219 SLUSAG1B – MARCH 2011 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS 10 V5 Supply Current (µA) 800 600 400 200 VV5 = 5 V VEN = 5 V No Load 0 −50 0 25 50 75 Junction Temperature (°C) 100 8 6 4 2 0 −50 125 −25 0 25 50 75 Junction Temperature (°C) 100 125 Figure 2. V5 Shutdown Current vs Junction Temperature 16 150 VV5 = 5 V VTRIP = 0.
PAGE 10
TPS51219 SLUSAG1B – MARCH 2011 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS Figure 11 and Figure 12 refer to the application schematic in Figure 33. 800 800 RMODE = 100 kΩ VIN = 12 V VOUT = 1.05 V L = 0.56 µH 600 500 400 300 200 100 0 RMODE = 200 kΩ VIN = 12 V VOUT = 1.05 V L = 0.56 µH 700 Switching Frequency (kHz) Switching Frequency (kHz) 700 600 500 400 300 200 100 0 2 4 6 8 10 12 14 Output Current (A) 16 18 0 20 0 Figure 7.
PAGE 11
TPS51219 SLUSAG1B – MARCH 2011 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS VSNS−GSNS − 1.00−V Output Voltage (V) Figure 11, Figure 12, and Figure 13 refer to the application schematic in Figure 33. Figure 14, Figure 15 and Figure 16, refer to the application schematic in Figure 33 except the parameters of L1 (0.56 µH), C7 (2 × 330 µF) and Q3 (not used). 100 90 80 Efficiency (%) 70 60 50 40 30 20 VIN = 8 V VIN = 12 V VIN = 20 V 10 RMODE = 1 kΩ 0 0.001 0.01 0.1 1 1.
PAGE 12
TPS51219 SLUSAG1B – MARCH 2011 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS VIN=20 V VIN=20 V VSNS-GSNS (20 mV/div) offset: 1.00 V VSNS-GSNS (20 mV/div) offset: 1.05 V IOUT (8 A/div) offset: 6 A IOUT (8 A/div) COUT = 2 x 330 µF(Bulk) + 12 x 22 µF(MLCC) COUT = 5 x 330 µF(Bulk) + 12 x 22 µF(MLCC) Figure 17. 1.05-V Load Transient Response EN (5 V/div) IOUT = 15A Figure 18. 1.00-V Load Transient Response IOUT = 0 A VSNS-GSNS (500mV/div) EN (5 V/div) VSNS-GSNS (500mV/div) 0.
PAGE 13
TPS51219 SLUSAG1B – MARCH 2011 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS Figure 22 refers to application schematic of Figure 33. IOUT = 0 A EN (5 V/div) VSNS-GSNS (500mV/div) PGOOD (5V/div) Time (100 ms/div) 80 180 60 135 40 90 20 45 0 0 −20 −45 −40 −60 −80 100 Phase (°) Gain (dB) Figure 21. 1.05-V Soft-stop Waveforms −90 Gain Phase 1000 VIN =12 V IOUT =15 A RMODE =1 kΩ 10000 Frequency (Hz) −135 100000 −180 1000000 Figure 22. Bode Plot, VOUT=1.
PAGE 14
TPS51219 SLUSAG1B – MARCH 2011 – REVISED OCTOBER 2011 www.ti.com APPLICATION INFORMATION Swtich Mode Power Supply Control The TPS51219 is a high performance, single-synchronous step-down controller with differential voltage feedback. The TPS51219 realizes accurate regulation at the specific load point over wide load range with the combination of three functions. • 2-V Reference with 0.8% Tolerance.
PAGE 15
TPS51219 SLUSAG1B – MARCH 2011 – REVISED OCTOBER 2011 www.ti.com Soft-Start and Powergood Provide a voltage supply to VIN and V5 before asserting EN to high. TPS51219 provides integrated soft-start functions to suppress in-rush current at start-up. The soft-start is achieved by controlling internal reference voltage ramping up. Figure 24 shows the start-up waveforms. The switching regulator waits for 400μs after EN assertion. The MODE pin voltage is read in this period.
PAGE 16
TPS51219 SLUSAG1B – MARCH 2011 – REVISED OCTOBER 2011 www.ti.com D-CAP™ Mode Figure 25 shows a simplified model of D-CAP™ mode architecture in the TPS51219. C1 VIN COMP 5 VSNS DH gM=130 mS 4 11 VOUT + + Lx PWM REFIN Control Logic and Driver 2 R1 VREF RLOAD ESR DL 1 + 2.0 V 10 COUT R2 UDG-11009 Figure 25. Simplified D-CAP™ Model The transconductance amplifier and the capacitance C1 configure an integrator. The VSNS voltage is compared with REFIN voltage.
PAGE 17
TPS51219 SLUSAG1B – MARCH 2011 – REVISED OCTOBER 2011 www.ti.com Jitter is another attribute caused by signal-to-noise ratio of the feedback signal. One of the major factors that determine jitter performance in D-CAP™ mode is the down-slope angle of the VSNS ripple voltage. Figure 26 shows, in the same noise condition, that jitter is improved by making the slope angle larger. VVSNS Slope (1) Jitter (2) Slope (2) Jitter 20 mV (1) VREFIN VREFIN +Noise tON tOFF Time UDG-11010 Figure 26.
PAGE 18
TPS51219 SLUSAG1B – MARCH 2011 – REVISED OCTOBER 2011 www.ti.com D-CAP2™ Mode Operation Figure 27 shows simplified model of D-CAP2™ architecture. VIN CC1 VSNS SW RC1 4 12 CC2 C1 RC2 DH 11 COMP G 5 + – + + PWM Comparator REFIN LX Control Logic and Driver VOUT DL 10 ESR 2 RLOAD COUT R1 VREF 1 + R2 2.0 V TPS51219 UDG-11011 Figure 27. Simplified Modulator Using D-CAP2™ Mode When the TPS51219 operates in D-CAP2™ mode, connect the COMP and VSNS pins as shown in Figure 27.
PAGE 19
TPS51219 SLUSAG1B – MARCH 2011 – REVISED OCTOBER 2011 www.ti.com Light-Load Operation In auto-skip mode, the TPS51219 SMPS control logic automatically reduces its switching frequency to improve light-load efficiency. To achieve this intelligence, a zero cross detection comparator is used to prevent negative inductor current by turning off the low-side MOSFET. Equation 6 shows the boundary load condition of this skip mode and continuous conduction operation.
PAGE 20
TPS51219 SLUSAG1B – MARCH 2011 – REVISED OCTOBER 2011 www.ti.com Overcurrent limiting using resistor sensing is shown in Equation 9. æ 25mV ö IIND(ripple) æ 25mV ö 1 VIN - VOUT VOUT IOCL = ç =ç ´ ÷+ ÷+ ´ 2 LX fSW ´ VIN è REXT ø è REXT ø 2 where • • IIND(ripple) is inductor ripple current REXT is the external current sense resistance (9) In an overcurrent condition, the current to the load exceeds the current to the output capacitor, thus the output voltage tends to fall down.
PAGE 21
TPS51219 SLUSAG1B – MARCH 2011 – REVISED OCTOBER 2011 www.ti.com External Components Selection The external components selection is simple in D-CAP™ mode. 1. DETERMINE THE VALUE OF R1 AND R2 The output voltage is determined by the value of the voltage-divider resistor, R1 and R2 as shown in Figure 25. R1 is connected between VREF and REFIN pins, and R2 is connected between the REFIN pin and GSNS. Setting R1 as 10-kΩ is a good starting point. Determine R2 using Equation 10. R1 R2 = æ ö ç ÷ ç ÷ 2.
PAGE 22
TPS51219 SLUSAG1B – MARCH 2011 – REVISED OCTOBER 2011 www.ti.com Lx Lx TPS51219 TPS51219 IOUT DL 10 10 TRIP TRIP Rx 6 + REXT 25 mV (typ) RX 6 + + IOUT DL + Cx 25 mV (typ) REXT Cx RXC ESL UDG-11043 Figure 28. Resistor Sensing with Compensation ESL UDG-11044 Figure 29. Adjustment of Overcurrent Limitation in Resistor Sensing A voltage divider can be configured to adjust for overcurrent limitation, as described in Figure 29.
PAGE 23
TPS51219 SLUSAG1B – MARCH 2011 – REVISED OCTOBER 2011 www.ti.com D-CAP2™ Mode Determine output capacitance to meet small signal stability as shown in Equation 22 and Equation 23. (RC ´ CC ) f £ SW 2p ´ G ´ L X ´ COUT 3 where • G = 0.25 (22) f gM £ 0 2p ´ C1 10 where • the RC × CC time constant is 32 µs for operation at 500 kHz.
PAGE 24
TPS51219 SLUSAG1B – MARCH 2011 – REVISED OCTOBER 2011 www.ti.com Layout Considerations Certain issues must be considered before designing a layout using the TPS51219. VREF VIN TPS51219 1 REFIN 0.1 mF V5 2 10 nF #1 VOUT 9 2.2 mF GSNS #2 GSNS DL 3 10 VSNS PGND VSNS #3 4 8 10 nF COMP 5 TRIP 6 MODE 15 GND PwrPad 7 UDG-11012 Figure 30.
PAGE 25
TPS51219 SLUSAG1B – MARCH 2011 – REVISED OCTOBER 2011 www.ti.com Connect VSNS directly to the output voltage sense point at the load device. Connect GSNS to ground return points at the load device. Insert a 10-Ω, 1-nF, R-C filter between the sense point and the VSNS pin where the COMP capacitance is connected as shown in Case 1 (Figure 31).
PAGE 26
TPS51219 SLUSAG1B – MARCH 2011 – REVISED OCTOBER 2011 • www.ti.com Connections from gate drivers to the respective gate of the high-side or the low-side MOSFET should be as short as possible to reduce stray inductance. Use 0.65 mm (25 mils) or wider trace and via(s) of at least 0.5 mm (20 mils) diameter along this trace.
PAGE 27
TPS51219 SLUSAG1B – MARCH 2011 – REVISED OCTOBER 2011 www.ti.com 1.05-V/20-A, D-CAP™ 400-kHz, RDS(on) Sensing Application Circuit V5IN 4.5V to 5.5V R2 200k R1 100k VIN EN 1 VREF REFIN GSNS VSNS 2 3 C1 0.1uF 13 14 4x10uF /25V 5 4 1-3 L1 0.45uH 11 Vout 1.05V/20A 10 9 C4 2.2uF 4 1-3 C7 5x330uF 5 5 4 1-3 C8 12x22uF 8 7 6 5 0.1uF /50V 8V to 20V 12 Q2 FDMS8670AS C2 0.01uF C9 1nF C6 R4 0 SW DH DL V5 U1 TPS51219 Q1 FDMS8680 C3 0.1uF COMP TRIP GND PGND 4 15 16 PwPd 3.
PAGE 28
TPS51219 SLUSAG1B – MARCH 2011 – REVISED OCTOBER 2011 www.ti.com TPS51219 1.00-V/10.4-A, D-CAP2™ 500-kHz, Resistor Sensing Application Circuit V5IN 4.5V to 5.5V R2 33k R1 100k VIN EN 3 C1 0.1uF VREF REFIN GSNS VSNS 13 14 U1 TPS51219 0.1uF /50V 4x10uF /25V 8V to 20V 5 4 1-3 SW DH DL V5 12 L1 0.45uH 11 Vout 1.00V/10.4A 10 9 5 C7 C4 2.2uF Q2 FDMS8670AS 4 C8 1-3 2x330uF 12x22uF 8 7 6 5 C6 R4 0 COMP TRIP GND PGND 4 15 16 PwPd 1 2 Q1 FDMS8680 C3 0.
PAGE 29
TPS51219 SLUSAG1B – MARCH 2011 – REVISED OCTOBER 2011 www.ti.com TPS51219 1.00-V/10.4-A, D-CAP™ 400-kHz, Resistor Sensing Application Circuit V5IN 4.5V to 5.5V R2 47k R1 100k VIN EN 3 4 14 13 16 U1 TPS51219 C10 1nF R7 10 7 0.1uF /50V 4x10uF /25V 8V to 20V 5 4 1-3 SW DH DL V5 12 L1 0.45uH 11 Vout 1.00V/10.4A 10 9 5 C4 2.2uF Q2 FDMS8670AS 4 C7 1-3 C8 2x330uF 12x22uF 8 6 5 C2 0.01uF C6 R4 0 COMP TRIP GND PGND C1 0.1uF VREF REFIN GSNS VSNS Q1 FDMS8680 C3 0.
PAGE 30
PACKAGE OPTION ADDENDUM www.ti.
PAGE 31
PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PAGE 32
PACKAGE MATERIALS INFORMATION www.ti.com 10-Jun-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS51219RTER WQFN RTE 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS51219RTER WQFN RTE 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS51219RTET WQFN RTE 16 250 330.0 12.4 3.3 3.3 1.1 8.0 12.
PAGE 33
PACKAGE MATERIALS INFORMATION www.ti.com 10-Jun-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS51219RTER WQFN RTE 16 3000 367.0 367.0 35.0 TPS51219RTER WQFN RTE 16 3000 338.0 355.0 50.0 TPS51219RTET WQFN RTE 16 250 338.0 355.0 50.
PAGE 34
PAGE 35
PAGE 36
PAGE 37
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.