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DRVH2

VIN

VREG3

EN2

DRVH1

V5SW

EN1

TPS51220A

(QFN32)

PGOOD2

SKIPSEL2

CSP2

CSN2

PGOOD1

SKIPSEL1

CSP1

CSN1

VF B 1

SW 1

V B ST 1

D RV L1

VR E G5

GN D

D RVL 2

V BS T2

SW 2

C O MP 1

FU NC

VR EF 2

T RIP

C OM P2

VF B 2

VO1

5.0V

C22

VBAT

PowerPAD

C 02

C01

VREG5

5V/100mA

R23

R13

C11

R11

PGOOD1

EN1

VREG3

3.3V/10mA

Q11

Q12

Q22

Q21

C13

R12

GND

R14

GND

R24

GND

C23

C21

R21

R22

GND

PGOOD2

EN2

VO2

3.3V

C03

R01

PGND

GND

SKIPSEL1 SKIPSEL2

VBAT

VO2

C12

VBAT

VO1

VREG5

C14

PGND

PGND PGND

C24

GND

TPS51220A

www.ti.com

SLUS897E –DECEMBER 2008–REVISED JANUARY 2013

Fixed Frequency, 99% Duty Cycle Peak Current Mode Notebook System Power Controller

Check for Samples: TPS51220A

FEATURES

• Input Voltage Range: 4.5 V to 32 V

• Powergood Output for Each Channel

• Output Voltage Range: 1 V to 12 V • OCL/OVP/UVP/UVLO Protections

(OVP Disable Option)

• Selectable Light Load Operation

(Continuous / Auto Skip / Out-Of-Audio™ Skip) • Thermal Shutdown (Non-Latch)

• Programmable Droop Compensation • Output Discharge Function (Disable Option)

• Voltage Servo Adjustable Soft Start • Integrated Boot Strap MOSFET Switch

• 200-kHz to 1-MHz Fixed-Frequency PWM • QFN-32 (RTV/RSN) Package

• Selectable Current/ D-CAP™ Mode

APPLICATIONS

Architecture

• Notebook Computer System and I/O Bus

• 180° Phase Shift Between Channels

• Point of Load in LCD TV, MFP

• Resistor or Inductor DCR Current Sensing

• Adaptive Zero Crossing Circuit

DESCRIPTION

The TPS51220A is a dual synchronous buck regulator controller with two LDOs. It is optimized for 5-V/3.3-V

system controller, enabling designers to cost effectively complete 2-cell to 4-cell notebook system power supply.

The TPS51220A supports high efficiency, fast transient response, and 99% duty cycle operation. It supports

supply input voltage ranging from 4.5 V to 32 V, and output voltages from 1 V to 12 V. Two types of control

schemes can be chosen depending on the application. Peak current mode supports stability operation with lower

ESR capacitor and output accuracy. The D-CAP mode supports fast transient response. The high duty (99%)

operation and the wide input/output voltage range supports flexible design for small mobile PCs and a wide

variety of other applications. The fixed frequency can be adjusted from 200 kHz to 1 MHz by a resistor, and each

channel runs 180° out-of-phase. The TPS51220A can also synchronize to the external clock, and the interleaving

ratio can be adjusted by its duty. The TPS51220A is available in the 32-pin 5×5/4×4 QFN package and is

specified from –40°C to 85°C.

TYPICAL APPLICATION CIRCUIT

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2Out-Of-Audio, D-CAP, PowerPAD are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (53 pages)

PAGE 1
TPS51220A www.ti.com SLUS897E – DECEMBER 2008 – REVISED JANUARY 2013 Fixed Frequency, 99% Duty Cycle Peak Current Mode Notebook System Power Controller Check for Samples: TPS51220A FEATURES 1 • • • 2 • • • • • • • Input Voltage Range: 4.
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TPS51220A SLUS897E – DECEMBER 2008 – REVISED JANUARY 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. FUNCTIONAL BLOCK DIAGRAM VIN EN V5SW + 4.7V/ 4.5V + 1.25V + + VREG5 4.7V/ 4.5V VREG3 GND V5OK + 4.2V/ 3.8V Ready GND + THOK 150/ 140 Deg-C VREF2 1.
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TPS51220A www.ti.com SLUS897E – DECEMBER 2008 – REVISED JANUARY 2013 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) TPS51220A Input voltage range (2) VIN –0.3 to 34 VBST1, VBST2 –0.3 to 39 VBST1, VBST2 (3) –0.3 to 7 SW1, SW2 –7 to 34 CSP1, CSP2, CSN1, CSN2 –1 to 13.5 EN, EN1, EN2, VFB1, VFB2, TRIP, SKIPSEL1, SKIPSEL2, FUNC –0.
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TPS51220A SLUS897E – DECEMBER 2008 – REVISED JANUARY 2013 www.ti.com ORDERING INFORMATION PACKAGE (1) TA -40°C to 85°C Plastic Quad Flat Pack (QFN) PINS 32 ORDERABLE DEVICE NUMBER TRANSPORT MEDIA TPS51220ARTVT 250 TPS51220ARTVR 3000 Tape and Reel TPS51220ARSNT TPS51220ARSNR (1) QUANTITY ECO PLAN Green (RoHS and no Sb/Br) 250 3000 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com.
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TPS51220A www.ti.com SLUS897E – DECEMBER 2008 – REVISED JANUARY 2013 ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range, VEN = 3.3 V, VVIN = 12 V, VV5SW = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOLTAGE TRANSCONDUCTANCE AMPLIFIER gMv Gain VID Differential Input Voltage Range TA = 25°C ICOMPSINK COMP Maximum Sink Current COMPx = 1.8 V ICOMPSRC COMP Maximum Source Current COMPx = 1.
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TPS51220A SLUS897E – DECEMBER 2008 – REVISED JANUARY 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range, VEN = 3.
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TPS51220A www.ti.com SLUS897E – DECEMBER 2008 – REVISED JANUARY 2013 ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range, VEN = 3.3 V, VVIN = 12 V, VV5SW = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INTERFACE AND LOGIC THRESHOLD VEN EN Threshold IENLK EN leak current Wake up 0.8 1 1.2 Hysteresis 0.1 0.2 0.3 0.45 0.50 0.55 0.1 0.2 0.3 EN = 0 V, or EN = 3.
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TPS51220A SLUS897E – DECEMBER 2008 – REVISED JANUARY 2013 www.ti.
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TPS51220A www.ti.com SLUS897E – DECEMBER 2008 – REVISED JANUARY 2013 PIN FUNCTIONS (continued) PIN NAME RF NO. 3 I/O DESCRIPTION I/O Frequency setting pin. Connect a frequency setting resistor to (signal) GND. Connect to an external clock for synchronization. Control architecture and OVP functions selection pin. FUNC 11 I VREF2 13 O GND: Current mode, OVP enable VREF2: D-CAP mode, OVP disable VREG3: D-CAP mode, OVP enable VREG5: Current mode, OVP disable 2-V reference output.
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TPS51220A SLUS897E – DECEMBER 2008 – REVISED JANUARY 2013 www.ti.com TYPICAL CHARACTERISTICS INPUT VOLTAGE SHUTDOWN CURRENT vs INPUT VOLTAGE INPUT VOLTAGE SHUTDOWN CURRENT vs JUNCTION TEMPERATURE 15 15 VI = 12 V IVINSDN -– Shutdown Current – mA IVINSDN -– Shutdown Current – mA TA = 25°C 12 9 6 3 10 15 20 25 9 6 3 0 -50 0 5 12 30 0 VI – Input Voltage – V Figure 1. Figure 2.
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TPS51220A www.ti.com SLUS897E – DECEMBER 2008 – REVISED JANUARY 2013 TYPICAL CHARACTERISTICS (continued) NO LOAD BATTERY CURRENT vs INPUT VOLTAGE NO LOAD BATTERY CURRENT vs INPUT VOLTAGE 1.0 1.0 EN = on EN1 = off EN2 = on 0.8 EN = on EN1 = on EN2 = on 0.9 IVBAT – Battery Current – mA IVBAT – Battery Current – mA 0.9 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 5 10 15 20 25 5 10 20 25 VI – Input Voltage – V VI – Input Voltage – V Figure 5. Figure 6.
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TPS51220A SLUS897E – DECEMBER 2008 – REVISED JANUARY 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) VREG3 OUTPUT VOLTAGE vs OUTPUT CURRENT VREG5 OUTPUT VOLTAGE vs OUTPUT CURRENT 3.40 VVREG5 – 5-V Linear Regulator Output Voltage – V VVREG3 – 3.3-V Linear Regulator Output Voltage – V 5.10 VI = 12 V 3.35 VI = 12 V 5.05 3.30 5.00 3.25 4.95 3.20 4.
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TPS51220A www.ti.com SLUS897E – DECEMBER 2008 – REVISED JANUARY 2013 TYPICAL CHARACTERISTICS (continued) OVP/UVP THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE VBST LEAKAGE CURRENT vs JUNCTION TEMPERATURE 150 1.5 IBSTLK – VBST Leakage Current – mA Voltage Protection Threshold – % OVP UVP 130 110 90 70 50 -50 0 50 100 1.2 0.9 0.6 0.3 0 -50 150 TJ – Junction Temperature – °C 100 Figure 13. Figure 14.
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TPS51220A SLUS897E – DECEMBER 2008 – REVISED JANUARY 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) 5-V OUTPUT VOLTAGE vs INPUT VOLTAGE 3.3-V OUTPUT VOLTAGE vs INPUT VOLTAGE 3.40 5.2 Auto-Skip Mode fSW = 330 kHz Auto-Skip Mode fSW = 330 kHz 5.0 VO2 – 3.3-V Output Voltage – V VO1 – 5-V Output Voltage – V 5.1 3.35 4.9 4.8 3.30 4.7 4.6 4.5 3.25 IO (A) 4.4 0 4 8 4.3 4.2 4.5 5.0 5.5 6.5 6.0 0 4 8 3.20 4.5 7.0 IO (A) 5.0 5.5 6.5 6.
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TPS51220A www.ti.com SLUS897E – DECEMBER 2008 – REVISED JANUARY 2013 TYPICAL CHARACTERISTICS (continued) 3.3-V EFFICIENCY vs OUTPUT CURRENT 3.3-V EFFICIENCY vs OUTPUT CURRENT 100 100 VI = 8 V Auto-Skip 90 VI = 12 V 60 h – Efficiency – % h – Efficiency – % 80 CCM OOA 40 VI = 12 V Current Mode RGV = 12 kW 5.0-V SMPS: ON 20 0 0.001 0.01 0.1 1 70 60 40 0.001 1 Figure 22. 5-V SWITCHING FREQUENCY vs OUTPUT CURRENT 3.
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TPS51220A SLUS897E – DECEMBER 2008 – REVISED JANUARY 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) 5-V OUTPUT VOLTAGE vs OUTPUT CURRENT 3.3-V OUTPUT VOLTAGE vs OUTPUT CURRENT 5.10 3.40 5.08 3.38 5.06 VO2 – 3.3-V Output Voltage – V VO1 – 5.0-V Output Voltage – V Auto-Skip and OOA 3.36 Auto-Skip 5.04 3.34 5.02 3.32 5.00 3.30 OOA 4.98 CCM 3.28 CCM 4.96 3.26 4.94 3.24 VI = 12 V Current Mode RGV = 18 kW 4.92 VI = 12 V Current Mode RGV = 12 kW 3.22 4.90 3.
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TPS51220A www.ti.com SLUS897E – DECEMBER 2008 – REVISED JANUARY 2013 TYPICAL CHARACTERISTICS (continued) 5-V OUTPUT VOLTAGE vs OUTPUT CURRENT 3.3-V OUTPUT VOLTAGE vs OUTPUT CURRENT 5.10 3.40 5.08 3.38 Auto-Skip 3.36 VO2 – 3.3-V Output Voltage – V VO1 – 5.0-V Output Voltage – V 5.06 Auto-Skip and OOA 3.34 5.04 3.32 5.02 5.00 3.30 OOA 4.98 3.28 CCM CCM 3.26 4.96 4.94 3.24 VI = 12 V D-CAP Mode RGV = 10 kW 4.92 VI = 12 V D-CAP Mode RGV = 10 kW 3.22 3.20 4.
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TPS51220A SLUS897E – DECEMBER 2008 – REVISED JANUARY 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) 5.0-V SWITCH-OVER WAVEFORMS VREG5 (100 mV/div) VO1 (100 mV/div) 2 ms/div Figure 33.
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TPS51220A www.ti.com SLUS897E – DECEMBER 2008 – REVISED JANUARY 2013 TYPICAL CHARACTERISTICS 5.0-V START-UP WAVEFORMS 3.3-V START-UP WAVEFORMS EN2 (5V/div) EN1 (5V/div) Vout1 (2V/div) Vout2 (2V/div) PGOOD2 (5V/div) 1msec/div PGOOD1 (5V/div) 1msec/div Figure 34. Figure 35. 5.0-V SOFT-STOP WAVEFORMS 3.3-V SOFT-STOP WAVEFORMS EN1 (5V/div) EN2 (5V/div) Vout1 (2V/div) Vout2 (2V/div) PGOOD2 (5V/div) PGOOD1 (5V/div) 10msec/div 1msec/div 1msec/div 10msec/div Figure 36. Figure 37.
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TPS51220A SLUS897E – DECEMBER 2008 – REVISED JANUARY 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) 5.0-V LOAD TRANSIENT RESPONSE 3.3-V LOAD TRANSIENT RESPONSE VI =12V, Auto-skip VI=12V, Auto-skip VO1 (100mV/div) VO2 (100mV/div) SW1 (10V/div) IO1 (5A/div) 100 100 mms/div s/div SW2 (10V/div) Figure 38. 20 IO2 (5A/div) 100 100 mms/div s/div Figure 39.
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TPS51220A www.ti.com SLUS897E – DECEMBER 2008 – REVISED JANUARY 2013 DETAILED DESCRIPTION ENABLE AND SOFT START When EN is Low, the TPS51220A is in the shutdown state. Only the 3.3-V LDO stays alive, and consumes 7 μA (typically). When EN becomes High, the TPS51220A is in the standby state. The 2-V reference and the 5-V LDO become enabled, and consume about 80 μA with no load condition, and are ready to turn on SMPS channels. Each SMPS channel is turned on when ENx becomes High.
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TPS51220A SLUS897E – DECEMBER 2008 – REVISED JANUARY 2013 www.ti.com 3.3-V, 10-mA LDO (VREG3) A 3.3-V, 10-mA, linear regulator is integrated in the TPS51220A. This LDO services some of the analog circuit in the device and provides a handy standby supply for 3.3-V Always On voltage in the notebook system. Apply a 2.2-μF (at least 1-μF), high quality X5R or X7R ceramic capacitor from VREG3 to (signal) GND in adjacent to the device.
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TPS51220A www.ti.com SLUS897E – DECEMBER 2008 – REVISED JANUARY 2013 PWM FREQUENCY CONTROL The TPS51220A has a fixed frequency control scheme with 180° phase shift. The switching frequency can be determined by an external resistor which is connected between RF pin and GND, and can be calculated using Equation 1. 1 × 105 fsw éëkHz ùû = RF ëékΩ ûù (1) TPS51220A can also synchronize to more than 2.5 V amplitude external clock by applying the signal to the RF pin.
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TPS51220A SLUS897E – DECEMBER 2008 – REVISED JANUARY 2013 www.ti.com In both cases, the TPS51220A shows jitter inherent to the blanking time. Since the device is a fixed frequency controller, the rising edge of the switching node is settled at the clock cycle. Consequently, jitter is observed at a period of switching node falling edge. This jitter does not represent small signal instability.
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TPS51220A SLUS897E – DECEMBER 2008 – REVISED JANUARY 2013 ILL(peak) – Inductor Current Limit – A www.ti.com 20% of IOCL ILL(PEAK) Ramp Signal ILL(PEAK) at Light Load 7% of IOCL tON 1/fSW t – Time Figure 43. Inductor Current Limit at Pulse Skipping Table 2.
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TPS51220A SLUS897E – DECEMBER 2008 – REVISED JANUARY 2013 www.ti.com HIGH-SIDE DRIVER The high-side driver is designed to drive high current, low RDS(on) N-channel MOSFET(s). The drive capability is represented by its internal resistance, which is 1.7Ω for VBSTx to DRVHx, and 1Ω for DRVHx to SWx. When configured as a floating driver, 5 V of bias voltage is delivered from VREG5 supply. The instantaneous drive current is supplied by the flying capacitor between VBSTx and SWx pins.
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TPS51220A www.ti.com SLUS897E – DECEMBER 2008 – REVISED JANUARY 2013 ADAPTIVE ZERO CROSSING TPS51220A has an adaptive zero crossing circuit which performs optimization of the zero inductor current detection at skip mode operation. This function pursues ideal low-side MOSFET turning off timing and compensates inherent offset voltage of the ZC comparator and delay time of the ZC detection circuit.
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TPS51220A SLUS897E – DECEMBER 2008 – REVISED JANUARY 2013 www.ti.com OVERVOLTAGE/UNDERVOLTAGE PROTECTION TPS51220A monitors the output voltage to detect overvoltage and undervoltage. When the output voltage becomes 15% higher than the target value, the OVP comparator output goes high and the circuit latches as the high-side MOSFET driver OFF and the low-side MOSFET driver ON, and shuts off another channel.
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TPS51220A www.ti.com SLUS897E – DECEMBER 2008 – REVISED JANUARY 2013 APPLICATION INFORMATION EXTERNAL PARTS SELECTION A buck converter using the TPS51220A consists of linear circuits and a switching modulator. Figure 44 and Figure 45 show basic scheme. Voltage divider R1 VFB Gmv DRVH PWM Control logic & Driver + + R2 VIN Switching Modulator Ramp comp. + + 1.0V Lx Rs DRVL ESR RL Co COMP Cc Rgv Gmc Rgc VREF CSP + + CSN 2.0V Error Amplifier Figure 44.
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TPS51220A SLUS897E – DECEMBER 2008 – REVISED JANUARY 2013 www.ti.com 3. Choose the inductor. The inductance value should be determined to give the ripple current of approximately 25% to 50% of maximum output current. Recommended ripple current rate is about 30% to 40% at the typical input voltage condition, next equation uses 33%. (VIN(TYP) - VOUT ) × VOUT 1 L= × 0.
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TPS51220A www.ti.com SLUS897E – DECEMBER 2008 – REVISED JANUARY 2013 VFB signal 30mV VFBRIPPLE =VoRIPPLE x 1/Vout Time tSW = 1/fSW Figure 46. Required voltage feedback ramp signal 7. Calculate Cc. The purpose of this capacitance is to cancel zero caused by ESR of the output capacitor. If ceramic capacitor(s) is used, there is no need for Cc.
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TPS51220A SLUS897E – DECEMBER 2008 – REVISED JANUARY 2013 www.ti.com INDUCTOR DCR CURRENT SENSING To use inductor DCR as current sensing resistor (Rs), the configuration needs to change as below. However, the equation that must be satisfied is the same as the one for the resistor sensing. VIN Inductor DRVH Control logic & Driver Lx Rs(DCR) DRVL Co Rx CSP + Cx CSN Figure 48. Inductor DCR Current Sensing VIN Inductor DRVH Control logic & Driver Lx Rs(DCR) DRVL Co Rx CSP + Cx Rc CSN Figure 49.
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TPS51220A www.ti.com SLUS897E – DECEMBER 2008 – REVISED JANUARY 2013 Inductor Lx Rx Rs(DCR) RNTC Rc1 Rc2 CO CSP + Cx CSN Figure 50. Inductor DCR Current Sensing With Temperature Compensate LAYOUT CONSIDERATIONS Certain points must be considered before starting a PCB layout work using the TPS51220A. Placement • Place RC network for CSP1 and CSP2 close to the device pins. • Place bypass capacitors for VREG5, VREG3 and VREF2 close to the device pins.
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TPS51220A SLUS897E – DECEMBER 2008 – REVISED JANUARY 2013 www.ti.com sensing comparator inputs (CSPx and CSNx). (See Figure 52) Current sensing Device RC network next to IC Figure 52. Current Sensing Traces • • • • Use small copper space for VFBx. These are short and narrow traces to avoid noise coupling Connect VFB resistor trace to the positive node of the output capacitor. Use signal GND for VREF2 and VREG3 capacitors, RF and VFB resistors, and the other sensitive analog components.
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VO1 5.0V/8A PGND C11 L1 VBAT Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links :TPS51220A GND R14 7.5k W EN R16 4.7W 32 R11 120k W R15 4.3k W GND 8 C15 100p F CSN1 9 CSP1 7 R12 30k W GND C13 0.1mF SKIPSEL1 6 PGOOD1 5 PGOOD1 SKIPSEL1 EN1 4 RF 3 DRVH1 V5SW 2 1 C14 0.1m F EN1 R01 300k W Q12 PGND GND VO1 VO1 PGND C12 SW 1 V F B1 31 10 PowerPAD R13 18k W VREF2 11 12 14 VREF2 GND VREF2 13 25 C24 0.
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TPS51220A SLUS897E – DECEMBER 2008 – REVISED JANUARY 2013 www.ti.com Table 6. Current Mode, DCR Sensing, 5-V/8-A, 3.3-V/8-A, 330-kHz SYMBOL SPECIFICATION MANUFACTURER PART NUMBER C11 2 × 330 μF, 6.3 V, 18 mΩ Sanyo 6TPE330MIL C12 2 × 10 μF, 25 V Murata GRM32DR71E106K C21 470 μF, 4.0V, 15 mΩ Sanyo 4TPE470MFL C22 2 × 10 μF, 25 V Murata GRM32DR71E106K L1 3.3 μH, 10.7 A, 10.5 mΩ TOKO FDV1040-3R3M L2 3.3 μH, 10.7 A, 10.5 mΩ TOKO FDV1040-3R3M Q11, Q21 30-V, 12 A, 10.
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VO1 5.0V/8A PGND C11 L1 VBAT Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links :TPS51220A GND R14 7.5k W EN R16 4.7W 32 R11 120k W R15 4.3k W GND 8 CSN1 C15 1.8n F 9 CSP1 7 R12 30k W GND C13 0.1mF SKIPSEL1 6 PGOOD1 5 PGOOD1 SKIPSEL1 EN1 4 RF 3 DRVH1 V5SW 2 1 C14 0.1m F EN1 R01 300k W Q12 PGND GND VO1 VO1 PGND C12 SW 1 V F B1 31 10 PowerPAD VREF2 R13 10k W 11 12 GND 13 14 VREF2 VREF2 25 C24 0.1 mF 15 C25 1.8n F R23 9.
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TPS51220A SLUS897E – DECEMBER 2008 – REVISED JANUARY 2013 www.ti.com Table 7. Current Mode (Non-droop), DCR Sensing, 5-V/8-A, 3.3-V/8-A, 330-kHz SYMBOL SPECIFICATION MANUFACTURER PART NUMBER C11 2 x 330 μF, 6.3 V 18 mΩ Sanyo 6TPE330MIL C12 2 x 10 μF, 25 V Murata GRM32DR71E106K C21 470 μF, 4.0V, 15 mΩ Sanyo 4TPE470MFL C22 2 x 10 μF, 25 V Murata GRM32DR71E106K L1 3.3 μH, 10.7 A, 10.5 mΩ TOKO FDV1040-3R3M L2 3.3 μH, 10.7 A, 10.5 mΩ TOKO FDV1040-3R3M Q11, Q21 30-V, 12-A, 10.
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VO1 5.0V/8A PGND C11 VREG3 L1 VBAT R14 7.5k W Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links :TPS51220A EN R16 4.7W 32 R11 120k W R15 4.3k W GND 8 CSN1 9 CSP1 7 R12 30k W GND C13 0.1mF SKIPSEL1 6 PGOOD1 5 PGOOD1 SKIPSEL1 EN1 4 RF 3 DRVH1 V5SW 2 1 C14 0.1m F EN1 R01 300k W Q12 PGND GND VO1 VO1 PGND C12 SW 1 V F B1 31 10 PowerPAD VREF2 R13 10k W 11 12 14 VREF2 GND VREF2 13 25 C24 0.
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TPS51220A SLUS897E – DECEMBER 2008 – REVISED JANUARY 2013 www.ti.com Table 8. D-CAP Mode, DCR Sensing, 5-V/ 8-A, 3.3-V/8-A, 330-kHz SYMBOL SPECIFICATION MANUFACTURER PART NUMBER C11 2 x 330 μF, 6.3 V, 18 mΩ Sanyo 6TPE330MIL C12 2 x 10 μF, 25 V Murata GRM32DR71E106K C21 470 μF, 4.0V, 15 mΩ Sanyo 4TPE470MFL C22 2 x 10 μF, 25 V Murata GRM32DR71E106K L1 3.3 μH, 10.7 A, 10.5 mΩ TOKO FDV1040-3R3M L2 3.3 μH, 10.7 A, 10.5 mΩ TOKO FDV1040-3R3M Q11, Q21 30 V, 12 A, 10.
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VO1 5.0V/5A PGND C11 L1 VBAT Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links :TPS51220A GND R14 6.8k W EN R16 4.7W 32 R11 120k W R15 56k W GND 8 C15 100p F CSN1 9 CSP1 7 R12 30k W GND C13 0.1mF SKIPSEL1 6 PGOOD1 5 PGOOD1 SKIPSEL1 EN1 4 RF 3 DRVH1 V5SW 2 1 C14 0.1m F EN1 R01 330k W Q12 PGND GND VO1 VO1 PGND C12 SW 1 V F B1 31 10 PowerPAD R13 10k W VREF2 11 12 14 VREF2 GND VREF2 13 25 C24 0.
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TPS51220A SLUS897E – DECEMBER 2008 – REVISED JANUARY 2013 www.ti.com Table 9. Current Mode, DCR Sensing, 5-V/5-A, 3.3-V/5-A, 300-kHz SYMBOL SPECIFICATION MANUFACTURER PART NUMBER C11 2 × 120 μF, 6.3V, 15 mΩ Panasonic EEFCX0J121R C12 2 × 10 μF, 25 V Murata GRM32DR71E106K C21 2 × 220 μF, 4.0 V, 15 mΩ Panasonic EEFCX0G221R C22 2 × 10 μF, 25 V Murata GRM32DR71E106K L1 4.0 μH, 10.3 A, 6.6 mΩ Sumida CEP125-4R0MC-H L2 4.0 μH, 10.3 A, 6.6 mΩ Sumida CEP125-4R0MC-H Q11, Q21 30 V, 13.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS51220ARSNR QFN RSN 32 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 TPS51220ARSNR QFN RSN 32 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 TPS51220ARSNT QFN RSN 32 250 180.0 12.4 4.25 4.25 1.15 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS51220ARSNR QFN RSN 32 3000 367.0 367.0 35.0 TPS51220ARSNR QFN RSN 32 3000 367.0 367.0 35.0 TPS51220ARSNT QFN RSN 32 250 210.0 185.0 35.0 TPS51220ARSNT QFN RSN 32 250 210.0 185.0 35.0 TPS51220ARTVR WQFN RTV 32 3000 367.0 367.0 35.0 TPS51220ARTVR WQFN RTV 32 3000 367.0 367.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.