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SLUS571 − SEPTEMBER 2003

  

  

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FEATURES

High Efficiency − No Current Sense Resistor

Required, R

DS(on)

Overcurrent Detection with

Temperature Compensation

D Adjustable Output Voltage Down to 0.9 V

D Voltage-Mode PWM Control: Maximum

500-kHz Operation

D 180° Out-of-Phase Control

D Individual Standby and Soft-Start for Each

Channel − Easy Power Sequencing

D Overvoltage and Undervoltage Protection

D Built-In Boot-Strap Diode

D Built-In 5-V Linear Regulator

D Accurate ± 1% 0.85-V Reference

APPLICATIONS

Consumer Game Systems

D DSP Applications

D Digital Set-Top Box

D VGA and Sound Cards

DESCRIPTION

The TPS5124 is dual independent high efficiency

synchronous step-down controller. It supports a

low-voltage/high-current power supply applica−

tions that use either a 5-V or 12-V bus voltage.

Since both controllers of the TPS5124 operate

180 degree out-of-phase, the input current ripple

is minimized resulting in a smaller input

capacitance and reduced power supply cost.

The current protection circuit detects the

drain-to-source voltage drop across the high-side

and low-side power MOSFET while it is

conducting. Also, the current protection circuit has

a temperature coefficient to compensate for the

DS(on)

variation of the MOSFET. This

resistor-less current protection and built-in boost

diode simplify the system design and reduces the

external parts count. Other features such as

undervoltage lockout, overvoltage, undervoltage,

and programmable short-circuit protection

promote system reliability.

TPS5124

FB2

SS2

N/C

SCP

STBY2

STBY1

REF

GND

N/C

SS1

FB1

VLSD

VREF5

LH2

OUT2_U

LL2

OUT2_D

OUTGND2

TRIP2

VCC

TRIP1

OUTGND1

OUT1_D

LL1

OUT1_U

LH1

INV2

INV1

N/C

UDG−03123

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (18 pages)

PAGE 1
SLUS571 − SEPTEMBER 2003 FEATURES D High Efficiency − No Current Sense Resistor D D D D D D D D DESCRIPTION The TPS5124 is dual independent high efficiency synchronous step-down controller. It supports a low-voltage/high-current power supply applica− tions that use either a 5-V or 12-V bus voltage.
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SLUS571 − SEPTEMBER 2003 ABSOLUTE MAXIMUM RATINGS −40°C ≤ TA ≤ 85°C, all voltage values are with respect to the network ground terminal unless otherwise noted. (1) TPS5124 Input voltage range Ouput voltage range VCC, STBY1, STBY2, TRIP1, TRIP2 −0.3 to 16 LH1, LH2 wrt GND −0.3 to 22 LH1, LH2 (wrt the corresponding LL terminal) −0.3 to 6 SS1, SS2, CT, INV1, INV2, SCP, VLSD −0.3 to 6 OUT1_U, OUT2_U −1 to 22 OUT1_U, OUT2_U (wrt the corresponding LL terminal) −0.
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SLUS571 − SEPTEMBER 2003 ELECTRICAL CHARACTERISTICS TJ = −40°C to 85°C, VCC = 12 V (unless otherwise noted) TEST CONDITIONS PARAMETER MIN TYP MAX UNIT SUPPLY CURRENTS ICC ICCS Supply current VVREF5 Output voltage TA = 25°C, 7.5 V ≤ VCC ≤ 15 V, 0 mA ≤ IO ≤ 10 mA VLN5 VLD5 Line regulation 7.
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SLUS571 − SEPTEMBER 2003 ELECTRICAL CHARACTERISTICS(continued) TJ = −40°C to 85°C, VCC = 12 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OUTPUT DRIVER OUT_U sink current V(OUTx_U) − V(LLx) = 3 V V(LHx) − V(OUTx_U) = 3 V OUT_U source current OUT_D sink current 1.2 −1.2 V(OUTx_D) = 3 V V(OUTx_D) = 2 V OUT_D source current A 1.5 −1.
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SLUS571 − SEPTEMBER 2003 TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION CT 5 I/O External capacitor from CT to GND adjusts frequency of the triangle oscillator. FB1 2 O Feedback output of SBRC−Channel 1 error amplifier. FB2 14 O Feedback output of SBRC−Channel 2 error amplifier. GND 7 − Signal GND. INV1 1 I Inverting inputs of Channel 1 error amplifier and OVP1/UVP1 comparator. INV2 15 I Inverting inputs of Channel 2 error amplifier and OVP2/UVP2 comparator.
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SLUS571 − SEPTEMBER 2003 FUNCTIONAL BLOCK DIAGRAM VLSD SS1 3 Soft−Start 1 30 LH1 Delay SFT1 29 OUT1_U FB1 2 INV1 + + + 28 LL1 PWM COMP + E/A 1 21 VLSD 27 OUT1_D Delay 0.85 V 26 OUTGND1 CT 5 Current Comparator Oscillator OVP1 STBY1 SFT1 25 TRIP1 UVLO + + + 0.85 V+12% OVP2 SFT2 + STBY2 + Current Protection Trigger 24 VCC 0.85 V+12% SCP + 11 Timer 23 TRIP2 UVP1 Current Comparator + + 0.
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SLUS571 − SEPTEMBER 2003 FUNCTIONAL DESCRIPTION INPUT VOLTAGE RANGE TPS5124 supports two input voltage ranges. When VVCC is between 6.5 V and 15 V, VLSD is connected to VREF5 with R-C filter (see Figure 1). When VVCC is between 4.5 V and 5.5 V, VLSD is connected to VCC with R-C filter and VREF5 is connected to VCC. (see Figure2). REFERENCE VOLTAGE (0.85 V) This 0.85-V reference voltage is used to set the output voltage and the reference for the overvoltage and undervoltage protections.
PAGE 8
SLUS571 − SEPTEMBER 2003 FUNCTIONAL DESCRIPTION OVER CURRENT PROTECTION (OCP) Over current protection (OCP) is achieved by comparing the drain-to-source voltage of the high-side and low-side MOSFET to a set-point voltage, which is defined by both the internal current source, ITRIP, and the external resistor connected between the VCC and TRIP pins. ITRIP has a typical value of 13 µA at 25°C.
PAGE 9
SLUS571 − SEPTEMBER 2003 FUNCTIONAL DESCRIPTION STANDBY The SBRC controller can be switched into standby mode separately by grounding STBY pin. Table 1. Standby Logic STBY1 STBY2 SBRC (CH1) SBRC (CH2) 5-V REGULATOR L L DISABLED DISABLED DISABLED L H DISABLED ENABLED ENABLED H L ENABLED DISABLED ENABLED H H ENABLED ENABLED ENABLED UNDERVOLTAGE LOCK OUT (UVLO) For undervoltage lock out (UVLO), the TPS5124 monitors VREF5 voltage.
PAGE 10
VIN 10 GND R27 GND C01 R26 R17 C29 R16 C19 www.ti.com R25 C28 C21 C04 C03 C02 C11 C18 R15 R23 Figure 1.
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VIN GND R27 GND C01 R26 R17 C29 R16 C19 www.ti.
PAGE 12
SLUS571 − SEPTEMBER 2003 APPLICATION INFORMATION SHUTDOWN SUPPLY CURRENT vs JUNCTION TEMPERATURE SUPPLY CURRENT vs JUNCTION TEMPERATURE 3.0 1000 VINV = VCT = 0 V VVCC = 12 V VINV = VCT = 0 V VSTBY1 = VSTBY2 = 0 V VVCC = 12 V ICC − Supply Current − nA ICC − Supply Current − mA 800 2.5 2.0 1.5 600 400 200 1.
PAGE 13
SLUS571 − SEPTEMBER 2003 APPLICATION INFORMATION UVP THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE OVP THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 1.0 VUVP − UVP Threshold Voltage − V VOVP − OVP Threshold Voltage − V 1.0 0.8 0.6 0.4 0.2 VVCC = 12 V 0 −50 0 50 100 VVCC = 12 V 0.8 0.6 0.4 0.
PAGE 14
SLUS571 − SEPTEMBER 2003 APPLICATION INFORMATION SOFT-START TIME vs SOFT-START CAPACITANCE SCP DELAY TIME vs SCP CAPACITANCE 100 k 100 k TJ = 25°C VVCC = 12 V 10 k 10 k tSS − Soft-Start Tmie − µs tDELAY − SCP Delay Time − µs TJ = 25°C VVCC = 12 V UVP 1000 1000 100 OVP 10 10 1 10 1 100 1000 10 k 100 k 10 100 1000 10 k CSSx − Soft-Start Capacitance − pF CSCP − SCP Capacitance − pF Figure 12 Figure 11 14 100 www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.