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

SLVS426 − MAY 2002

   

   

FEATURES

D Three Independent Step-Down DC/DC

Controllers and One LDO Controller

D Input Voltage Range

− Switcher: 4.5 V ~ 28 V

− LDO: 1.1 V ~ 3.6 V

D Output Voltage Range

− Switcher: 0.9 V ~ 5.5 V

− LDO: 0.9 V ~ 2.5 V

D Synchronous for High Efficiency

D Precision V

ref

(±1.5%)

D PWM Mode Control : Max. 500 kHz Operation

D Auto PWM/SKIP Mode Available

D High Speed Error Amplifier

D Over Current Protection With Temperature

Compensation Circuit for Each Channel

D Overvoltage and Undervoltage Protection

D Programmable Short-Circuit Protection

D Powergood With Programmable Delay Time

D 5-V and 3.3-V Linear Regulators

APPLICATIONS

D Notebook PCs, PDAs

D Consumer Game Systems

D DSP Application

DESCRIPTION

The TPS5130 is composed of three independent

synchronous buck regulator controllers (SBRC) and

one low drop-out (LDO) regulator controller. On-chip

high-side and low-side synchronous rectifier drivers are

integrated to drive less expensive N-channel

MOSFETs. The LDO controller can also drive an

external N-channel MOSFET. Since the input current

ripple is minimized by operating 180 degree out of

phase, it allows a smaller input capacitance resulting in

reduced power supply cost. The SBRC of the TPS5130

automatically adjusts from PWM mode to SKIP mode

to maintain high efficiency under light load conditions.

Resistor-less current protection for the synchronous

buck controller and the fixed high-side driver voltage

simplifies the system design and reduces the external

parts count. The LDO controller has a current limit

protection and overshoot protection to suppress output

voltage hump at load transient. To further extend

battery life, the TPS5130 features dead-time control

and very low quiescent current.

See application section of this data sheet for more detailed information.

VIN

Vo1

5 V

Vo3

Vo_LDO

TPS5130

OUT3_u OUT1_u

OUT3_d OUT1_d

LL3 LL1

VIN

INV3 INV1

OUT2_u

OUT2_d

LL2

INV2

LDO_IN

LDO_GATE

LDO_CUR

INV_LDO

REG5V_IN

GND

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Summary of content (31 pages)

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www.ti.com SLVS426 − MAY 2002 FEATURES APPLICATIONS D Notebook PCs, PDAs D Consumer Game Systems D DSP Application D Three Independent Step-Down DC/DC Controllers and One LDO Controller D Input Voltage Range − Switcher: 4.5 V ~ 28 V − LDO: 1.1 V ~ 3.6 V DESCRIPTION The TPS5130 is composed of three independent synchronous buck regulator controllers (SBRC) and one low drop-out (LDO) regulator controller.
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www.ti.com SLVS426 − MAY 2002 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION PACKAGED DEVICES PLASTIC TQFP (PT)(1) TA −40°C to 85°C TPS5130PT (1) The PT package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS5130PTR).
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www.ti.com SLVS426 − MAY 2002 RECOMMENDED OPERATING CONDITIONS MIN Supply voltage MAX UNIT 4.5 28 LDO_IN 1.1 3.6 REG5V_IN 4.5 5.5 −0.1 33 4.5 28 STBY_LDO, LL1/2/3, TRIP, STBY_VREF3.3/5 −0.1 28 LDO_GATE −0.1 8 INV1/2/3, INV_LDO, CT, PWM_SEL, FLT, PG_DELAY, SS_STBY1/2/3 −0.1 6 PGOUT, FB1/2/3, OUT1/2/3_d −0.1 5.5 LDO_CUR, LDO_OUT −0.1 3.
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www.ti.com SLVS426 − MAY 2002 ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range, V(VIN) = V(VIN_SENSE12) = V(VIN_SENSE3) = 12 V (unless otherwise noted) VREF3.3 PARAMETER VO TEST CONDITIONS IO = 0 mA to 30 mA, TA = 25°C V(VIN) = 5.5 V to 28 V, Output voltage Line regulation Load regulation IOS Short circuit output current IO = 1 mA to 10 mA, V(VREF3.3) = 0 V, V(VIN) = 5.5 V to 28 V, MIN TYP MAX UNIT 3.15 3.30 3.45 V IO = 10 mA V(VIN) = 5.
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www.ti.
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www.ti.com SLVS426 − MAY 2002 PIN ASSIGNMENTS VIN_SENSE12 41 40 39 38 37 TRIP2 OUT2_d 43 42 TRIP1 OUTGND1 OUT1_d LL1 OUT1_u 46 45 44 OUTGND2 48 47 LH1 FLT INV1 PT (TOP VIEW) 36 LL2 SS_STBY1 2 35 OUT2_u INV2 3 34 LH2 FB2 4 33 VIN SS_STBY2 5 32 VREF3.3 PWM_SEL 6 31 VREF5 CT 7 30 REG5V_IN GND 8 29 LDO_IN REF 9 28 LDO_CUR STBY_VREF5 10 27 LDO_GATE STBY_VREF3.
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www.ti.com SLVS426 − MAY 2002 Terminal Functions (Continued) TERMINAL NAME NO. I/O DESCRIPTION LH1 46 I/O Bootstrap capacitor connection for SBRC-CH1 high-side gate driver. LH2 34 I/O Bootstrap capacitor connection for SBRC-CH2 high-side gate driver. LH3 20 I/O Bootstrap capacitor connection for SBRC-CH3 high-side gate driver. LL1 44 I/O SBRC-CH1 high-side gate driving return.
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www.ti.com SLVS426 − MAY 2002 FUNCTIONAL BLOCK DIAGRAM PWM_SEL SBRC−CH1 SOFTSTART /STBY SS_STBY1 Duplicate for CH2 and CH3. SKIP Comp. − 0.85 V + FB1 LH1 ERROR Amp. INV1 − Oscillator CT OUT1_u PWM Comp. + + + − LL1 0.85 V OUT1_d OUTGND1 Phase Inverter Current Comp. 1 OVP Comp. − + + Current Protection Trigger 0.85 V + 12 % UVP Comp. + SS_STBY − −(VIN_SENSE−TRIP) − − VIN_SENSE12 + TRIP1 Current Comp. 2 0.
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www.ti.com SLVS426 − MAY 2002 DETAILED DESCRIPTION PWM OPERATION The SBRC block has a high-speed error amplifier to regulate the output voltage of the synchronous buck converter. The output voltage of the SBRC is fed back to the inverting input (INVx (x=1,2,3)) of the error amplifier. The noninverting input is internally connected to a 0.85-V precise band gap reference circuit. The unity gain bandwidth of the amplifier is 2.5 MHz.
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www.ti.com SLVS426 − MAY 2002 DEAD-TIME The internally defined dead-time prevents shoot-through-current flowing through the main power MOSFETs during switching transitions. Typical value of the dead-time is 100 ns. STANDBY The SBRC controller, the LDO controller, and the internal regulators can be switched into standby mode separately as shown in Table 1. The standby mode current, when both controllers and regulators are off, can be as low as 1 nA. Table 1.
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www.ti.com SLVS426 − MAY 2002 OVER CURRENT PROTECTION Over current protection (OCP) is achieved by comparing the drain-to-source voltage of the high-side and low-side MOSFET to a set-point voltage, which is defined by both the internal current source, I(TRIP), and the external resistor connected between the VIN_SENSEx and the TRIPx pins. I(TRIP) has a typical value of 13 µA at 25°C.
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www.ti.com SLVS426 − MAY 2002 UNDER VOLTAGE LOCK OUT (UVLO) When the output voltage of the internal 5-V regulator or the REG5V_IN voltage decreases below about 4 V, the output stages of all the SBRCs and the LDO are turned off. This state is not latched, and the operation recovers immediately after the input voltage becomes higher than the turnon value again. The typical hysteresis voltage is 100 mV. UVLO FOR LDO The LDO_IN voltage is monitored with a hysteretic comparator.
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www.ti.com SLVS426 − MAY 2002 5-V REGULATOR An internal linear voltage regulator is used for the high-side driver bootstrap. Since the input voltage ranges from 4.5 V to 28 V, this feature offers a fixed bootstrap voltage to simplify the drive design. It is active if the STBY_VREF5 is HIGH and has a tolerance of 4%. The 5-V regulator is used for powering the low-side driver and the VREF. When this regulator is disconnected from the MOSFET drivers, it is used only for the source of VREF. 3.
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www.ti.com SLVS426 − MAY 2002 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs JUNCTION TEMPERATURE SUPPLY CURRENT (SHUTDOWN) vs JUNCTION TEMPERATURE 3 250 I CC − Supply Current (Shutdown) − nA I CC − Supply Current − mA V(LDO_IN) = V(LDO_CUR) = 3.6 V, V(PWM_ESL) = V(FLT) = V(CT) = 0 V 2.5 2 1.5 1 V(LDO_IN) = V(LDO_CUR) = 3.6 V, V(INX) = V(INV_LDO) = 0 V V(SS_STBYx) = 0 V V(STBY_VREF 3.
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www.ti.com SLVS426 − MAY 2002 TYPICAL CHARACTERISTICS SOURCE CURRENT (LDO_GATE) vs OUTPUT VOLTAGE 955 V(INV_LDO) = 0 V V(LDO_IN) = V(LDO_CUR) = 3.3 V Threshold Voltage (OVP) − mV Source Current (LDO_GATE) − mA −2 THRESHOLD VOLTAGE (OVP) vs JUNCTION TEMPERATURE −1.5 −1 −0.
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www.ti.com SLVS426 − MAY 2002 TYPICAL CHARACTERISTICS CURRENT LIMIT THRESHOLD VOLTAGE FOR LDO vs JUNCTION TEMPERATURE 100000 TJ = 25°C Soft Start Time − µ s 10000 1000 100 10 1 1 10 100 1000 10000 C − Capacitance − pF 100000 Current Limit Threshold Voltage For LDO − mV SOFT START TIME vs CAPACITANCE 60 50 40 30 20 V(LDO_IN) = 3.3 V V(INV_LDO) = 0.
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www.ti.com SLVS426 − MAY 2002 APPLICATION INFORMATION The design shown is a reference design for a notebook PC application. An evaluation module (EVM) is available for customer testing and evaluation. The following key design procedures aid in the design of the notebook PC power supply using TPS5130.
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www.ti.com SLVS426 − MAY 2002 calculated to achieve the desired output voltage. In the EVM design, the value of R1 is determined as R01A = 27 kΩ and R01B = 1.8 kΩ for VO1, R03A = 47 kΩ and R03B = 1.8 kΩ for VO2, R14A = 10 kΩ and R14B = 1.2 kΩ for VO3, and R18 = 6.8 k + 820 Ω for VO4 considering stability. For VO1: R05 + (27 k ) 1.8 k) 0.85 + 9.99 kW 3.3 * 0.85 Therefore, use 10 kΩ. In a same manner, R07 = R11 = R19 = 10 kΩ as follows. R07 + (47 k ) 1.8 k) 0.85 + 10.00 kW 5 * 0.
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www.ti.com SLVS426 − MAY 2002 OUTPUT CAPACITOR SELECTION Selection of the output capacitor is basically dependent on the amount of peak-to-peak ripple voltage allowed on the output and the ability of the capacitor to dissipate the RMS ripple current. Assuming that the ESR of the output filter sees the entire inductor ripple current then: V pp + I (ripple) R(esr) And a suitable capacitor must be chosen so that the peak-to-peak output ripple is within the limits allowable for the application.
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www.ti.com SLVS426 − MAY 2002 SOFT START The soft start timing can be adjusted by selecting the soft-start capacitor value. The equation is; C(soft) + 2.3 10–6 T(soft) 0.85 where C(soft) is the soft-start capacitor (µF) (C05, C07 and C10 in EVM design): T(soft) is the start-up time (s). Example: T(soft) = 5 ms, therefore, C(soft) = 0.0135 µF. CURRENT PROTECTION The current limit in TPS5130 is set using an internal current source and an external resistor (R17, R23 and R24).
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www.ti.com SLVS426 − MAY 2002 Undervoltage Protection The undervoltage comparator circuit continually monitors the voltage at the INV and INV_LDO pins. If the voltage at either pin falls below 65 % of the 0.85 V reference, the timer begins to charge the FLT capacitor. if the fault condition persists beyond the time t(uvplatch), the fault latch is set and both the high-side and low-side drivers, and LDO regulator drivers are forced OFF.
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www.ti.com SLVS426 − MAY 2002 Layout Guidelines Good power supply results only occur when care is given to proper design and layout. Layout affects noise pickup and generation and can cause a good design to perform with less than expected results. With a range of currents from milliamps to tens amps, good power supply layout is much more difficult than most general PCB designs.
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www.ti.com SLVS426 − MAY 2002 Connections D Connections from the drivers to the gate of the power MOSFETs should be as short and wide as possible to reduce stray inductance. This becomes more critical if external gate resistors are not being used. In addition, as for the current limit noise issue, use of a gate resistor on the high-side MOSFET(s) considerably reduces the noise at the LL node, improving the performance of the current limit function.
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www.ti.com SLVS426 − MAY 2002 EFFICIENCY (AUTO SKIP MODE) vs OUTPUT CURRENT EFFICIENCY (AUTO SKIP MODE) vs OUTPUT CURRENT Efficiency (AUTO SKIP MODE) − % Efficiency (AUTO SKIP MODE) − % 80 VIN = 8 V VIN = 12 V VIN = 20 V 60 40 SBRC CH1 External 5 V VO1 = 3.3 V 20 0 0.01 0.1 1 IO − Output Current − A 100 VIN = 8 V VIN = 12 V VIN = 20 V 80 60 40 SBRC CH2 External 5 V VO2 = 5 V 20 0 0.01 10 0.1 1 IO − Output Current − A Figure 22 VIN = 20 V 40 SBRC CH3 External 5 V VO3 = 1.
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www.ti.com SLVS426 − MAY 2002 SBRC CH3 OUTPUT LOAD REGULATION LDO OUTPUT LOAD REGULATION 1.790 1.480 PWM Mode VIN = 12 V V(LDO_IN)= VO3 1.475 VO − Output Voltage − V VO − Output Voltage − V 1.785 1.780 1.775 1.770 1.765 1.760 0 1.470 1.465 1.460 1.455 1.450 1 2 3 4 IO− Output Current − A 5 0 6 Figure 31 SBRC CH1 OUTPUT VOLTAGE RIPPLE 50 mV/div 2 3 Figure 32 SBRC CH2 OUTPUT VOLTAGE RIPPLE SBRC CH3 OUTPUT VOLTAGE RIPPLE 20 mV/div 50 mV/div VIN = 12 V, VO1 = 3.
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www.ti.com SLVS426 − MAY 2002 LDO LOAD TRANSIENT RESPONSE SBRC CH3 LOAD TRANSIENT RESPONSE VIN = 12 V, V(LDO_IN) = VO3 = 1.8 V, V(LDO) = 1.
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www.ti.com SLVS426 − MAY 2002 MECHANICAL DATA PT (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 1,45 1,35 0,05 MIN Seating Plane 1,60 MAX 0°−ā 7° 0,75 0,45 0,10 4040052/ C 11/96 NOTES:A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS5130PTR Package Package Pins Type Drawing LQFP PT 48 SPQ Reel Reel Diameter Width (mm) W1 (mm) 1000 330.0 16.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 9.6 9.6 1.9 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS5130PTR LQFP PT 48 1000 346.0 346.0 33.
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