Datasheet

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BST

PWM

TPS51604

SKIP

VDD

DRVH

GND

DRVL

PWM

SKIP

C2C1

UDG-12234

TPS51604

www.ti.com

SLUSBA6A –DECEMBER 2012–REVISED AUGUST 2013

Synchronous Buck FET Driver Optimized for High-Frequency Applications

Check for Samples: TPS51604

FEATURES

DESCRIPTION

The TPS51604 drivers are optimized for high-

• Reduced Dead-Time Drive Circuit for

frequency CPU V

CORE

applications. Advanced

Optimized CCM

features such as reduced dead-time drive and Auto

• Automatic Zero Crossing Detection for

Zero Crossing are used to optimize efficiency over

Optimized DCM Efficiency

the entire load range.

• Multiple Low-Power Modes for Optimized

The SKIP pin provides immediate CCM operation to

Light-Load Efficiency

support controlled management of the output voltage.

• Optimized Signal Path Delays for High-

In addition, the TPS51604 supports two low-power

Frequency Operation modes. With the PWM input in tri-state, quiescent

current is reduced to 130 µA, with immediate

• Integrated BST Switch Drive Strength

response. When SKIP is held at tri-state, the current

Optimized for Ultrabook FETs

is reduced to 8 µA (typically 20 µs is required to

• Optimized for 5-V FET Drive

resume switching). Paired with the appropriate TI

controller, the drivers deliver an exceptionally high

• Conversion Input Voltage Range (V

): 4.5 V to

performance power supply system.

28 V

• Small, 2 mm x 2 mm, 8-Pin, WSON Power Pad

The TPS51604 is packaged in a space saving,

Package

thermally enhanced 8-pin, 2 mm x 2 mm WSON

package and operates from –40°C to 105°C.

APPLICATIONS

• High Frequency CPU V

CORE

Applications

– Adapter

– Battery

– NVDC

– 5-V or 12-V Rails

TYPICAL APPLICATION

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (19 pages)

PAGE 1
TPS51604 www.ti.com SLUSBA6A – DECEMBER 2012 – REVISED AUGUST 2013 Synchronous Buck FET Driver Optimized for High-Frequency Applications Check for Samples: TPS51604 FEATURES DESCRIPTION • The TPS51604 drivers are optimized for highfrequency CPU VCORE applications. Advanced features such as reduced dead-time drive and Auto Zero Crossing are used to optimize efficiency over the entire load range.
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TPS51604 SLUSBA6A – DECEMBER 2012 – REVISED AUGUST 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) (2) over operating free-air temperature range (unless otherwise noted) Input voltage Output voltage MIN MAX VDD –0.3 6 PWM, SKIP –0.3 6 BST –0.3 35 BST (transient < 20 ns) –0.
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TPS51604 www.ti.com SLUSBA6A – DECEMBER 2012 – REVISED AUGUST 2013 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) Input voltage Output voltage Ground pins VDD MIN TYP MAX 4.5 5.0 5.5 V PWM, SKIP –0.1 BST –0.1 34 BST to SW; DRVH to SW –0.1 5.5 SW –1.0 28 DRVL –0.1 5.5 GND to PAD –0.1 0.1 V –40 105 °C Operating junction temperature, TJ 5.
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TPS51604 SLUSBA6A – DECEMBER 2012 – REVISED AUGUST 2013 www.ti.com ELECTRICAL CHARACTERISTICS These specifications apply for TJ = –40°C to 105°C and VDD = 5.0V unless otherwise specified.
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TPS51604 www.ti.com SLUSBA6A – DECEMBER 2012 – REVISED AUGUST 2013 ELECTRICAL CHARACTERISTICS (continued) These specifications apply for TJ = –40°C to 105°C and VDD = 5.0V unless otherwise specified. PARAMETER CONDITIONS MIN TYP MAX UNITS GATE DRIVER DEAD-TIME tR(DT) Rising edge 0 20 35 ns tF(DT) Falling edge 0 10 25 ns –2.25 0 2.
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TPS51604 SLUSBA6A – DECEMBER 2012 – REVISED AUGUST 2013 www.ti.com DSG 8 PINS (TOP VIEW) BST 1 8 DRVH PWM 2 7 SW TPS51604 SKIP 3 6 GND VDD 4 5 DRVL PIN FUNCTIONS PIN NAME NO. I/O (1) DESCRIPTION BST 1 I High-side N-channel FET bootstrap voltage input; power supply for high-side driver. DRVH 8 O High-side N-channel gate drive output. DRVL 5 O Synchronous low-side N-channel gate drive output GND 6 – Synchronous low-side N-channel gate drive return and IC reference.
PAGE 7
TPS51604 www.ti.com SLUSBA6A – DECEMBER 2012 – REVISED AUGUST 2013 TYPICAL CHARACTERISTICS Figure 1. PWM High to DRVL Low Figure 2. PWM Low to DRVH Low Figure 3. DRVL Low to DRVH High Figure 4. DRVH Low DRVL High Figure 5. PWM Low to Tri-state Figure 6.
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TPS51604 SLUSBA6A – DECEMBER 2012 – REVISED AUGUST 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) 8 Figure 7. SKIP Mode Entry Figure 8. SKIP Mode Exit Figure 9. Very-Low-Power Mode Entry Figure 10. Very-Low-Power Mode Exit Figure 11. SW Node-Ringing at VIN = 8 V Figure 12.
PAGE 9
TPS51604 www.ti.com SLUSBA6A – DECEMBER 2012 – REVISED AUGUST 2013 TYPICAL CHARACTERISTICS 100 100 95 95 90 90 85 85 Efficiency (%) Efficiency (%) Powerblock MOSFET: CSD87330(SLPS284) , Inductor: 0.22 µF, 1.1 mΩ DCR 80 75 70 SKIP = High VIN = 7.4 V VOUT = 1.8 V fSW = 800 kHz FCCM Operation 65 60 55 50 0 2 4 6 8 10 12 14 Output Current (A) 16 18 20 80 75 70 SKIP = Low VIN = 7.4 V VOUT = 1.8 V fSW = 800 kHz Skip Mode Operation 65 60 55 22 50 0 G000 Figure 13. Efficiency vs.
PAGE 10
TPS51604 SLUSBA6A – DECEMBER 2012 – REVISED AUGUST 2013 www.ti.com DETAILED DESCRIPTION The TPS51604 is a synchronous buck MOSFET driver designed to drive both high-side and low-side MOSFETs. It allows high-frequency operation with current driving capability matched to the application. The integrated boost switch is internal. The TPS51604 employs dead-time reduction control and shoot-through protection; which helps avoid simultaneous conduction of high-side and low-side MOSFETs.
PAGE 11
TPS51604 www.ti.com SLUSBA6A – DECEMBER 2012 – REVISED AUGUST 2013 VIH High-Z Window High-Z Window VIL PWM High-Z High-Z HDR LDR t3RD1 tFPD-DRVH tHOLD_OFF1 tFPD-DRVL tR-DT tHOLD_OFF2 t3RD2 tF-DT UDG-12225 Time Figure 16. PWM Tri-State Timing Diagram SKIP Pin The SKIP pin incorporates the input tri-state buffer as PWM. The function is somewhat different.
PAGE 12
TPS51604 SLUSBA6A – DECEMBER 2012 – REVISED AUGUST 2013 www.ti.com Adaptive Deadtime Control and Shoot-Through Protection The driver utilizes an anti-shoot-through and adaptive dead-time control to minimize low-side body diode conduction time and maintain high efficiency. When the PWM input voltage becomes high, the low-side MOSFET gate voltage begins to fall after a propagation delay.
PAGE 13
TPS51604 www.ti.com SLUSBA6A – DECEMBER 2012 – REVISED AUGUST 2013 Layout Guidelines To • • • • • • • improve the switching characteristics and design efficiency, these layout rules must be considered. Locate the driver as close as possible to the MOSFETs. Locate the VDD and bootstrap capacitors as close as possible to the driver. Pay special attention to the GND trace. Use the thermal pad of the package as the GND by connecting it to the GND pin.
PAGE 14
TPS51604 SLUSBA6A – DECEMBER 2012 – REVISED AUGUST 2013 www.ti.com REVISION HISTORY Changes from Original (December 2012) to Revision A Page • Aligned package description throughout datasheet. ............................................................................................................. 1 • Removed Ordering Information table. ...................................................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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