Datasheet

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TPS53114

www.ti.com

SLVS887B –APRIL 2009–REVISED OCTOBER 2010

SINGLE SYNCHRONOUS STEP-DOWN CONTROLLER

FOR LOW VOLTAGE POWER RAILS

Check for Samples: TPS53114

FEATURES

• Pre-Biased Soft Start

• D-CAP2™ Mode Control

• Selectable Switching Frequency

350 kHz / 700 kHz

– Fast Transient Response

• Cycle-By-Cycle Over Current Limiting Control

– No External Parts Required For Loop

Compensation • Thermally Compensated OCP by 4000 ppm/°C

at I

TRIP

– Compatible with Ceramic Output

Capacitors

APPLICATIONS

• High Initial Reference Accuracy (±1%)

• Point-of-Load Regulation in Low Power

• Low Output Ripple

Systems for Wide Range of Applications

• Wide Input Voltage Range: 4.5 V to 24 V

– Digital TV Power Supply

• Output Voltage Range: 0.76 V to 5.5 V

– Networking Home Terminal

• Low-Side R

DS(on)

Loss-Less Current Sensing

– Digital Set Top Box (STB)

• Adaptive Gate Drivers with Integrated Boost

– DVD Player / Recorder

Diode

– Gaming Consoles

• Adjustable Soft Start

DESCRIPTION

The TPS53114 is a single, adaptive on-time D-CAP2™ mode synchronous buck controller. The TPS53114

enables system designers to complete the suite of various end equipment's power bus regulators with cost

effective low external component count and low standby current solution. The main control loop for the

TPS53114 uses the D-CAP2™ mode control which provides a very fast transient response with no external

components. The TPS53114 also has a circuit that enables the device to adapt to both low equivalent series

resistance (ESR) output capacitors such as POSCAP or SP-CAP and ultra-low ESR ceramic capacitors. The

device provides convenient and efficient operation with input voltages from 4.5 V to 24 V and output voltage from

0.76 V to 5.5 V.

The TPS53114 is available in the 16-pin TSSOP and HTSSOP packages, and is specified from –40°C to 85°C

ambient temperature range.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2D-CAP2 is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (27 pages)

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TPS53114 www.ti.com SLVS887B – APRIL 2009 – REVISED OCTOBER 2010 SINGLE SYNCHRONOUS STEP-DOWN CONTROLLER FOR LOW VOLTAGE POWER RAILS Check for Samples: TPS53114 FEATURES 1 • 2 • • • • • • • D-CAP2™ Mode Control – Fast Transient Response – No External Parts Required For Loop Compensation – Compatible with Ceramic Output Capacitors High Initial Reference Accuracy (±1%) Low Output Ripple Wide Input Voltage Range: 4.5 V to 24 V Output Voltage Range: 0.76 V to 5.
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TPS53114 SLVS887B – APRIL 2009 – REVISED OCTOBER 2010 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. TYPICAL APPLICATION CIRCUITS VIN 1 R1 VBST VO 16 R2 SGND 2 VFB 3 SS 4 GND Q1 10uFx2 DRVH 15 VO1 (TSSOP16) C7 SGND C3 C2 0.
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TPS53114 www.ti.com SLVS887B – APRIL 2009 – REVISED OCTOBER 2010 ORDERING INFORMATION (1) TA PACKAGE (3) ORDERING PART NUMBER HTSSOP (Thermal Pad） TPS53114PWPR (3) OUTPUT SUPPLY ECO PLAN Tape-and-Reel 16 TPS53114PWR TSSOP (1) (2) PINS TPS53114PWP –40°C to 85°C (2) TPS53114PW Tube Green (RoHS & no Sb/Br) Tape-and-Reel Tube All packaging options have Cu NIPDAU lead/ball finish.
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TPS53114 SLVS887B – APRIL 2009 – REVISED OCTOBER 2010 www.ti.com RECOMMENDED OPERATING CONDITIONS Supply input voltage range Input voltage range Output Voltage range MIN MAX VIN 4.5 24 V5FILT 4.5 5.5 VBST –0.1 30 VBST - SW –0.1 5.5 VFB, VO, FSEL, CER –0.1 5.5 TRIP –0.1 0.3 EN –0.1 24 DRVH –0.1 30 VBST - SW –0.1 5.5 SW 1.8 24 DRVL, VREG5, SS –0.1 5.5 PGND UNIT V V V –0.1 0.
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TPS53114 www.ti.com SLVS887B – APRIL 2009 – REVISED OCTOBER 2010 ELECTRICAL CHARACTERISTICS (continued) over recommended free-air temperature range, VIN = 12 V (unless otherwise noted) PARAMETER CONDITIONS MIN TYP MAX UNIT ON-TIME TIMER CONTROL TONL On Time SW = 12V, VO = 1.8V, FSEL = 0V 390 ns TONH On Time SW = 12V, VO = 1.8V, FSEL = V5FILT 139 ns TOFFL Min off time SW = 0.7V, TA = 25°C, VFB = 0.7V, FSEL = 0V 285 ns TOFFH Min off time SW = 0.7V, TA = 25°C, VFB = 0.
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TPS53114 SLVS887B – APRIL 2009 – REVISED OCTOBER 2010 www.ti.com PIN FUNCTIONS PIN I/O DESCRIPTION NAME NO. VBST 16 I Supply input for high-side NFET driver. Bypass to SW with a high-quality 0.1-mF ceramic capacitor. An external schottky diode can be added from VREG5 if forward drop is critical to drive the high-side FET. EN 7 I Enable. Pull High to enable SMPS. SS 3 O Soft start programming pin. Connect capacitor from SS pin to GND to program soft start time.
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TPS53114 www.ti.com SLVS887B – APRIL 2009 – REVISED OCTOBER 2010 FUNCTIONAL BLOCK DIAGRAM VIN -30% FSELECT UV VREG5 VBST 16 Control Logic 0.1 mF 15 VO OV 1 XCON 15% 14 13 PGND Ref SS 12 PWM 10 mA VFB 2 SW VO DRVL PGND GND TRIP OCP EN 10x2 mF DRVH EN Logic 7 SS Logic 11 LL PGND VIN VIN SS 9 3 UV GND OV 4 UVLO VREG5 Protection 5VREG 10 Logic 4.
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TPS53114 SLVS887B – APRIL 2009 – REVISED OCTOBER 2010 www.ti.com PWM FREQUENCY AND ADAPTIVE ON-TIME CONTROL TPS53114 employs adaptive on-time control scheme and does not have a dedicated on board oscillator. TPS53114 runs with pseudo-constant frequency by using the input voltage and output voltage to set the on-time one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the output voltage. Therefore, when the duty ratio is VOUT/VIN, the frequency is constant.
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TPS53114 www.ti.com SLVS887B – APRIL 2009 – REVISED OCTOBER 2010 OVER CURRENT PROTECTION TPS53114 has a cycle-by-cycle over current limit feature. The over current limits the inductor valley current by monitoring the voltage drop across the low-side MOSFET RDS(on) during the low-side driver on-time. If the inductor current is larger than the over current limit (OCL), the TPS53114 delays the start of the next switching cycle until the sensed inductor current falls below the OCL current.
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TPS53114 SLVS887B – APRIL 2009 – REVISED OCTOBER 2010 www.ti.com TYPICAL CHARACTERISTICS VIN SUPPLY CURRENT vs JUNCTION TEMPERATURE VIN SHUTDOWN CURRENT vs JUNCTION TEMPERATURE 600 40 IO(sd) − Shutdown Current − µA ICC − Supply Current − µA 500 45 f = 350 kHz VO = 1.05 V 400 300 200 VREG5 = ON FSEL = V5FILT 35 30 FSEL = GND 25 20 15 10 100 5 0 −50 0 50 100 TJ − Junction Temperature − °C 0 −50 150 G001 Figure 6.
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TPS53114 www.ti.com SLVS887B – APRIL 2009 – REVISED OCTOBER 2010 TYPICAL CHARACTERISTICS (continued) VFB VOLTAGE vs TEMPERATURE (VO = 1.05 V, IO = 4 A) VREG5 VOLTAGE vs INPUT VOLTAGE 5.200 0.800 0.795 5.100 5.000 0.785 VFB Voltage - V VREG5 Voltage - V 0.790 4.900 4.800 0.780 0.775 FSEL = GND 0.770 0.765 4.700 FSEL = V5FILT 0.760 4.600 0.755 4.500 0.750 0 5 10 15 20 25 -5 0 0 VIN - Input Voltage - V 50 100 150 Temperature - °C Figure 9. Figure 10.
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TPS53114 SLVS887B – APRIL 2009 – REVISED OCTOBER 2010 www.ti.com APPLICATION INFORMATION VIN R2 10kW VBST 16 1 VO R1 3.69kW C7 SGND 4700 pF 2 VFB (HTSSOP 16) 3 DRV H 15 C3 10uF VO1 SW 14 SS 4 GND SGND Q1 FDS8678 L1 SPM6530T 1.5uH C2 0.1uF TPS53114 PWP THERMAL PAD SGND 5 CER 6 FSEL DRV L Q2 FDS8690 13 PGND 12 C1 22uFx4 R3 3.9k W TRIP 11 PGND 7 EN VREG 5 10 C5 C6 VIN 8 V5FILT SGND 4.7uF VIN 9 C4 10uF 1uF PGND Figure 12.
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TPS53114 www.ti.com SLVS887B – APRIL 2009 – REVISED OCTOBER 2010 TYPICAL APPLICATION PERFORMANCE Typical application performance below was taken from specific application circuits Figure 12 and Figure 13. 800 500 400 VO = 5 V VO = 3.3 V VO = 1.8 V f(SW) − Swithing Frequency − kHz 450 f(SW) − Swithing Frequency − kHz VO = 5 V FSEL = GND f = 350 kHz 350 300 VO = 1.05 V VO = 1.2 V 250 700 600 500 VO = 1.05 V VO = 1.8 V 400 VO = 1.
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TPS53114 SLVS887B – APRIL 2009 – REVISED OCTOBER 2010 www.ti.com 1.10 1.09 1.10 VI = 12 V 1.08 1.07 VO − Output Voltage − V VO − Output Voltage − V 1.08 FSEL = GND 1.06 1.05 1.04 FSEL = V5FILT 1.03 FSEL = V5FILT 1.07 1.06 1.05 1.04 FSEL = GND 1.03 1.02 1.02 1.01 1.01 1.00 0.0 IO = 3 A 1.09 1.00 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.
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TPS53114 www.ti.com SLVS887B – APRIL 2009 – REVISED OCTOBER 2010 100 90 EN 80 η − Efficiency − % 70 SS VO = 1.05 V 60 50 40 30 20 FSEL = GND 350 kHz Selection VI = 12 V 10 CSS = 4700 pF 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 IO − Output Current − A t − Time − 2 ms/div G012 Figure 22. STARTUP WAVEFORM G013 Figure 23. 1.05-V EFFICIENCY vs. OUTPUT CURRENT 100 90 80 η − Efficiency − % 70 60 50 40 30 20 FSEL = V5FILT 700 kHz Selection VI = 12 V 10 0 0.0 0.5 1.0 1.5 2.0 2.5 3.
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TPS53114 SLVS887B – APRIL 2009 – REVISED OCTOBER 2010 www.ti.com COMPONENT SELECTION CHOOSE INDUCTOR The inductance value is selected to provide approximately 30% peak to peak ripple current at maximum load. Larger ripple current increases output ripple voltage, improve S/N ratio and contribute to stable operation. L1 can be calculated using Equation 3.
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TPS53114 www.ti.com SLVS887B – APRIL 2009 – REVISED OCTOBER 2010 CHOOSE BOOTSTRAP CAPACITOR The TPS53114 requires a bootstrap capacitor from SW to VBST to provide the floating supply for the high-side drivers. A minimum 0.1-mF high-quality ceramic capacitor is recommended. The voltage rating should be greater than 10.0 V. CHOOSE VREG5 AND V5FILT CAPACITOR The TPS53114 requires both the VREG5 regulator and V5FILT input are bypassed. A minimum 4.
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TPS53114 SLVS887B – APRIL 2009 – REVISED OCTOBER 2010 www.ti.com LAYOUT SUGGESTIONS • • • • • • Keep the input switching current loop as small as possible. Place the input capacitor (C3, C6) close to the top switching FET. The output current loop should also be kept as small as possible. Keep the SW node as physically small and short as possible as to minimize parasitic capacitance and inductance and to minimize radiated emissions.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) TPS53114PWPR HTSSOP PWP 16 2000 330.0 12.4 TPS53114PWR TSSOP PW 16 2000 330.0 12.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.9 5.6 1.6 8.0 12.0 Q1 6.9 5.6 1.6 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS53114PWPR HTSSOP PWP 16 2000 367.0 367.0 35.0 TPS53114PWR TSSOP PW 16 2000 367.0 367.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.