Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - DC/DC voltage regulator Holder HTSSOP 28

6,4 mm X 9,7 mm

Typical Size

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FEATURES DESCRIPTION

APPLICATIONS

PVIN PH

BOOT

PGND

VSENSE

Output

AGND

VBIAS

Input1

TPS54010

SIMPLIFIED SCHEMATIC

COMP

Compensation

Network

VIN

2.5 V or 3.3 V

3.3 V

Input2

350 F

1 F

0.047 F

0.68 H

200 F

0.1 F

120 pF

3300 pF

4.64 k

14.7 k

10 k

422 

1500 pF

1 F

100

0 2 4 6 8 10 12 14 16

− Output Current − A

Efficiency − %

EFFICIENCY

OUTPUT CURRENT

VIN = 3.3 V,

PVIN = 2.5 V,

= 1.5 V,

= 700 kHz

TPS54010

SLVS509B – MAY 2004 – REVISED JUNE 2005

2.2 – 4 -V, 14-A OUTPUT SYNCHRONOUS BUCK PWM SWITCHER

WITH INTEGRATED FETs (SWIFT™)

• Separate Low-Voltage Power Bus

As a member of the SWIFT™ family of dc/dc regu-

lators, the TPS54010 low-input voltage, high-output

• 8-m Ω MOSFET Switches for High Efficiency at

current synchronous buck PWM converter integrates

14-A Continuous Output

all required active components. Included on the

• Adjustable Output Voltage Down to 0.9 V

substrate with the listed features are a true, high-

• Externally Compensated With 1% Internal

performance, voltage error amplifier that enables

Reference Accuracy

maximum performance under transient conditions

and flexibility in choosing the output filter L and C

• Fast Transient Response

components; an undervoltage-lockout circuit to pre-

• Wide PWM Frequency: Adjustable 280 kHz to

vent start-up until the VIN input voltage reaches 3 V;

700 kHz

an internally and externally set slowstart circuit to limit

• Load Protected by Peak Current Limit and

in-rush currents; and a power-good output useful for

Thermal Shutdown

processor/logic reset, fault signaling, and supply se-

quencing.

• Integrated Solution Reduces Board Area and

Total Cost

The TPS54010 is available in a thermally enhanced

28-pin TSSOP (PWP) PowerPAD™ package, which

• SWIFT Documentation, Application Notes, and

eliminates bulky heatsinks.

Design Software: www.ti.com/swift

• Low-Voltage, High-Density Systems With

Power Distributed at 2.5 V, 3.3 V Available

• Point of Load Regulation for High-

Performance DSPs, FPGAs, ASICs, and

Microprocessors

• Broadband, Networking, and Optical

Communications Infrastructure

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SWIFT, PowerPAD are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (29 pages)

PAGE 1
Typical Size 6,4 mm X 9,7 mm TPS54010 www.ti.com SLVS509B – MAY 2004 – REVISED JUNE 2005 2.2 – 4 -V, 14-A OUTPUT SYNCHRONOUS BUCK PWM SWITCHER WITH INTEGRATED FETs (SWIFT™) FEATURES • • • • • • • • • DESCRIPTION Separate Low-Voltage Power Bus 8-mΩ MOSFET Switches for High Efficiency at 14-A Continuous Output Adjustable Output Voltage Down to 0.
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TPS54010 www.ti.com SLVS509B – MAY 2004 – REVISED JUNE 2005 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) TA OUTPUT VOLTAGE PACKAGE PART NUMBER -40°C to 85°C Adjustible down to 0.9 V Plastic HTSSOP (PWP) (1) TPS54010PWP The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e.
PAGE 3
TPS54010 www.ti.com SLVS509B – MAY 2004 – REVISED JUNE 2005 ELECTRICAL CHARACTERISTICS TJ = -40°C to 125°C, VIN = 3 V to 4 V, PVIN = 2.2 V to 4 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE, VIN VI Input voltage, VIN Supply voltage range, PVIN VIN IQ Quiescent current PVIN Output = 1.8 V 3 4 V 2.2 4 V fs = 350 kHz, RT open, PH pin open, PVIN = 2.5 V, SYNC = 0 V 6.3 10 mA fs = 550 kHz, RT open, PH pin open, SYNC ≥ 2.5 V, PVIN = 2.5 V 8.
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TPS54010 www.ti.com SLVS509B – MAY 2004 – REVISED JUNE 2005 ELECTRICAL CHARACTERISTICS (continued) TJ = -40°C to 125°C, VIN = 3 V to 4 V, PVIN = 2.
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TPS54010 www.ti.com SLVS509B – MAY 2004 – REVISED JUNE 2005 DEVICE INFORMATION PWP PACKAGE (TOP VIEW) AGND VSENSE COMP PWRGD BOOT PH PH PH PH PH PH PH PH PH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 THERMAL 22 PAD 21 20 19 18 17 16 15 RT SYNC SS/ENA VBIAS VIN PVIN PVIN PVIN PVIN PGND PGND PGND PGND PGND TERMINAL FUNCTIONS PIN NAME PIN NUMBER DESCRIPTION AGND 1 Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, and RT resistor.
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TPS54010 www.ti.com SLVS509B – MAY 2004 – REVISED JUNE 2005 FUNCTIONAL BLOCK DIAGRAM VBIAS AGND VIN SS/ENA Falling Edge Deglitch 1.2 V Hysteresis: 0.03 V 2.5 µs VIN UVLO Comparator VIN 2.95 V Hysteresis: 0.11 V VIN REG VBIAS Enable Comparator 3.0 − 4.0 V SHUTDOWN PVIN ILIM Comparator Thermal Shutdown 150°C 2.2 − 4.0 V Leading Edge Blanking Falling and Rising Edge Deglitch 100 ns BOOT 8 mΩ 2.5 µs SS_DIS SHUTDOWN Internal/External Slow-start (Internal Slow-start Time = 3.
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TPS54010 www.ti.com SLVS509B – MAY 2004 – REVISED JUNE 2005 TYPICAL CHARACTERISTICS DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE 10 8 6 4 2 0 −40 −20 8 6 4 2 0 0 20 40 60 80 100 125 −40 −20 0 20 40 60 80 100 125 TJ − Junction Temperature − °C 750 650 SYNC ≥ 2.5 V 550 450 SYNC ≤ 0.8 V 350 250 −40 0 25 85 125 TJ − Junction Temperature − °C Figure 1. Figure 2. Figure 3.
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TPS54010 www.ti.
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TPS54010 www.ti.com SLVS509B – MAY 2004 – REVISED JUNE 2005 tain as much separation as possible while keeping the layout compact. Connect the bias capacitor from the VBIAS pin to analog ground using the isolated analog ground trace. If a slow-start capacitor or RT resistor is used, or if the SYNC pin is used to select 350-kHz operating frequency, connect them to this trace. ted to the largest area available.
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TPS54010 www.ti.com SLVS509B – MAY 2004 – REVISED JUNE 2005 µF µF µF kΩ µF kΩ µF µF kΩ µ µF µF kΩ µF kΩ kΩ Figure 12. Application Circuit, 2.5 V to 1.5 V Figure 12 shows the schematic for a typical TPS54010 application. The TPS54010 can provide up to 14-A output current at a nominal output voltage of 1.5 V. Nominal input voltages are 2.5 V for PVIN and 3.3 V for VIN. For proper thermal performance, the exposed PowerPAD underneath the device must be soldered down to the printed-circuit board.
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TPS54010 www.ti.com SLVS509B – MAY 2004 – REVISED JUNE 2005 I (continued) DESIGN PARAMETER EXAMPLE VALUE Operating frequency 700 kHz I SWITCHING FREQUENCY The switching frequency can be set to either one of two internally programmed frequencies or set to a externally programmed frequency. With the RT pin open, setting the SYNC pin at or above 2.5 V selects 550-kHz operation, whereas grounding or leaving the SYNC pin open selects 350-kHz operation.
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TPS54010 www.ti.com SLVS509B – MAY 2004 – REVISED JUNE 2005 V OUT I I L(PK) OUT(MAX) 1.6 V V V in(MAX) OUT L F sw IN(MAX) OUT (6) For this design, the RMS inductor current is 15.4 A, and the peak inductor current is 15.1 A. For this design, a Vishay IHLP2525CZ-01 style output inductor is specified. The largest value greater than 0.44 µH that meets these current requirements is 0.68 µH.
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TPS54010 www.ti.com SLVS509B – MAY 2004 – REVISED JUNE 2005 of the switching frequency, and the phase margin at crossover must be greater than 45 degrees. The general procedure outlined here produces results consistent with these requirements without going into great detail about the theory of loop compensation. First, calculate the output filter LC corner frequency using Equation 10: 1 ƒ LC 2 L C OUT OUT (10) For the design example, fLC = 19.3 kHz.
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TPS54010 www.ti.com SLVS509B – MAY 2004 – REVISED JUNE 2005 AGND. The value should be 1.0 µF. Both capacitors should be high-quality ceramic types with X7R or X5R grade dielectric for temperature stability. They should be placed as close to the device connection pins as possible. POWER GOOD The TPS54010 is provided with a power-good output pin PWRGD. This output is an open-drain output and is intended to be pulled up to a 3.3-V or 5-V logic supply. A 10-kΩ pullup works well in this application.
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TPS54010 www.ti.com SLVS509B – MAY 2004 – REVISED JUNE 2005 µF µF µF kΩ µF µ µF 10 kΩ µF µF µF 20 kΩ 10 kΩ 10 kΩ 2 kΩ 10 kΩ 14.7 kΩ 10 kΩ 49.9 Ω 10 kΩ 49.9 Ω µF Figure 14. 1.5-V Power Supply With Remote Sense With an output current of 14 A, if the load is located far from the dc/dc converter circuit, it may be beneficial to include a remote sense capability. Figure 14 is an example of a power supply incorporating active differential remote sensing.
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TPS54010 www.ti.com SLVS509B – MAY 2004 – REVISED JUNE 2005 3.6 V 100 nF 330 µF 10 µF 10 µF C17 1 µF 100 nF 0.047 µF 1 µF 10 kΩ 0.68 µH 0.047 µF 2.4 kΩ 100 µF 100 µF 0.1 µF 422 Ω 14.7 kΩ 10 kΩ Figure 15. 2.5 V to 1.5 V Power Supply with Charge Pump If a suitable 3-V to 4-V source is not available for the VIN supply, a charge pump may be used to boost the PVIN voltage. In this circuit, the charge pump is used to boost a 2.5-V source to a nominal 3.6 V.
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TPS54010 www.ti.com SLVS509B – MAY 2004 – REVISED JUNE 2005 PERFORMANCE GRAPHS The performance data for Figure 16 through Figure 24 are for the circuit in Figure 12. Conditions are PVIN = 2.5 V, VIN = 3.3 V, VO = 1.5 V, fs = 700 kHz, and IO = 7 A, TA = 25°C, unless otherwise specified. MEASURED LOOP RESPONSE vs FREQUENCY LOAD REGULATION vs OUTPUT CURRENT 120 60 Gain 0 0 -20 -60 -40 -120 0.5 0.3 0.4 0.25 0.3 3.3 V 0.2 2.5 V 0.1 0 2.2 V -0.1 -0.2 4.0 V -0.3 -0.
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TPS54010 www.ti.com SLVS509B – MAY 2004 – REVISED JUNE 2005 PERFORMANCE GRAPHS The performance data for Figure 25 through Figure 34 are for the circuit in Figure 13. Conditions are PVIN = 2.5 V, VIN = 3.3 V, VO = 1.5 V, fs = 700 kHz, and IO = 7 A, TA = 25°C, unless otherwise specified. FREE-AIR TEMPERATURE vs MAXIMUM OUTPUT CURRENT MEASURED LOOP RESPONSE vs FREQUENCY 60 125 VO = 1.5 V, PVIN = VI = 3.3 V, TJ = 125°C 0.
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TPS54010 www.ti.com SLVS509B – MAY 2004 – REVISED JUNE 2005 PERFORMANCE GRAPHS (continued) OUTPUT VOLTAGE RIPPLE VO(RIPPLE) = 10 mV/div (ac coupled) LOAD TRANSIENT RESPONSE VO = 100 mV/div (ac coupled) START-UP WAVEFORM OUTPUT VOLTAGE RELATIVE TO ENABLE V(SS/ENA) = 1 V/div IO = 5 A/div VO = 1 V/div IO = 14 A V(PH ) = 1 V/div Time = 500 nsec/div Time = 200 sec/div Figure 31. Time = 10 msec/div Figure 32. Figure 33.
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TPS54010 www.ti.com SLVS509B – MAY 2004 – REVISED JUNE 2005 100 kΩ VIN 10 kΩ PVIN VBIAS + − 10 kΩ 27.4 kΩ SS/ENA the UVLO comparator, and a 2.5-ms rising and falling edge deglitch circuit reduce the likelihood of shutting the device down due to noise on VIN. UVLO is with respect to VIN and not PVIN, see the Application Information section. 1/2 LM293 SLOW-START/ENABLE (SS/ENA) Figure 35.
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TPS54010 www.ti.com SLVS509B – MAY 2004 – REVISED JUNE 2005 External loading on VBIAS is allowed, with the caution that internal circuits require a minimum VBIAS of 2.7 V, and external loads on VBIAS with ac or digital-switching noise may degrade performance. The VBIAS pin may be useful as a reference voltage for external circuits. VBIAS is derived from the VIN pin; see the functional block diagram of this data sheet.
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TPS54010 www.ti.com SLVS509B – MAY 2004 – REVISED JUNE 2005 DEAD-TIME CONTROL AND MOSFET DRIVERS Adaptive dead-time control prevents shoot-through current from flowing in both N-channel power MOSFETs during the switching transitions by actively controlling the turn-on times of the MOSFET drivers. The high-side driver does not turn on until the voltage at the gate of the low-side FET is below 2 V. While the low-side driver does not turn on until the voltage at the gate of the high-side MOSFET is below 2 V.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS54010PWPR Package Package Pins Type Drawing SPQ HTSSOP 2000 PWP 28 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 16.4 Pack Materials-Page 1 6.9 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.2 1.8 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS54010PWPR HTSSOP PWP 28 2000 367.0 367.0 38.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.