Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - DC/DC voltage regulator Holder VSON 10

EFFICIENCY

LOADCURRENT

0 0.1 0.2 0.3 0.4

LoadCurrent- A

Efficiency-%

100

0.5

V =12V,

V =5.0V,

f =700kHz

VIN

GND

BOOT

VSENSE

COMP

TPS54040A

RT /CLK

SS /TR

PWRGD

VIN

OUT

TPS54040A

www.ti.com

SLVSB58A –MARCH 2012–REVISED JANUARY 2014

0.5 A, 42 V Step Down DC/DC Converter with Eco-mode™

Check for Samples: TPS54040A

FEATURES

• 3.5 V to 42 V Input Voltage Range

• UV and OV Power Good Output

• 200-mΩ High-Side MOSFET • 0.8-V Internal Voltage Reference

• High Efficiency at Light Loads with a Pulse • Available in MSOP-10 and VSON-10 Packages

Skipping Eco-mode™

• Supported by WEBENCH

and SwitcherPro™

• Tighter Enable Threshold than TPS54040 Software Tool

for More Accurate UVLO Voltage

APPLICATIONS

• Adjustable UVLO Voltage and Hysteresis

• 12-V and 24-V Industrial and Commercial Low

• 116 μA Operating Quiescent Current

Power Systems

• 1.3 μA Shutdown Current

• Aftermarket Auto Accessories: Video, GPS,

• 100 kHz to 2.5 MHz Switching Frequency

Entertainment

• Synchronizes to External Clock

• Adjustable Slow Start/Sequencing

DESCRIPTION

The TPS54040A device is a 42 V, 0.5 A, step down regulator with an integrated high side MOSFET. Current

mode control provides simple external compensation and flexible component selection. A low ripple pulse skip

mode reduces the no load, regulated input supply current to 116 μA. Using the enable pin, shutdown supply

current is nominally 1.3 μA when the enable pin is low.

Under voltage lockout is internally set at 2.5 V, but can be increased using the enable pin. The output voltage

startup ramp is controlled by the slow start pin that can also be configured for sequencing or tracking. An open

drain power good signal indicates when the output is within 94% to 107% of its nominal voltage.

A wide switching frequency range allows efficiency and external component size to be optimized. Frequency fold

back and thermal shutdown protects the part during an overload condition.

SPACER

SIMPLIFIED SCHEMATIC

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2Eco-mode, SwitcherPro are trademarks of Texas Instruments.

3WEBENCH is a registered trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (52 pages)

PAGE 1
TPS54040A www.ti.com SLVSB58A – MARCH 2012 – REVISED JANUARY 2014 0.5 A, 42 V Step Down DC/DC Converter with Eco-mode™ Check for Samples: TPS54040A FEATURES 1 • • • 23 • • • • • • • 3.5 V to 42 V Input Voltage Range 200-mΩ High-Side MOSFET High Efficiency at Light Loads with a Pulse Skipping Eco-mode™ Tighter Enable Threshold than TPS54040 for More Accurate UVLO Voltage Adjustable UVLO Voltage and Hysteresis 116 μA Operating Quiescent Current 1.3 μA Shutdown Current 100 kHz to 2.
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TPS54040A SLVSB58A – MARCH 2012 – REVISED JANUARY 2014 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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TPS54040A www.ti.com SLVSB58A – MARCH 2012 – REVISED JANUARY 2014 THERMAL INFORMATION TPS54040A THERMAL METRIC (1) DGQ (10 PINS) DRC (10 PINS) 62.5 40 83 65 θJA Junction-to-ambient thermal resistance (standard board) θJCtop Junction-to-case (top) thermal resistance θJB Junction-to-board thermal resistance 28 8 ψJT Junction-to-top characterization parameter 1.7 0.6 ψJB Junction-to-board characterization parameter 20.1 7.5 θJCbot Junction-to-case (bottom) thermal resistance 21 7.
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TPS54040A SLVSB58A – MARCH 2012 – REVISED JANUARY 2014 www.ti.com ELECTRICAL CHARACTERISTICS (continued) TJ = –40°C to 150°C, VIN = 3.5 to 42V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 2500 kHz 720 kHz 2200 kHz TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN) Switching Frequency Range using RT mode fSW Switching frequency 100 RT = 200 kΩ 450 Switching Frequency Range using CLK mode 581 300 Minimum CLK input pulse width 40 RT/CLK high threshold 1.
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TPS54040A www.ti.com SLVSB58A – MARCH 2012 – REVISED JANUARY 2014 DEVICE INFORMATION PIN CONFIGURATION MSOP-10 (TOP VIEW) VSON-10 (TOP VIEW) BOOT 1 10 PH VIN 2 EN 3 SS/TR 4 9 GND Thermal Pad (11) RT/CLK 5 8 COMP BOOT 1 VIN 2 10 Thermal Pad (11) PH 9 GND 8 COMP EN 3 7 VSENSE SS/TR 4 7 VSENSE 6 PWRGD RT/CLK 5 6 PWRGD PIN FUNCTIONS PIN I/O DESCRIPTION NAME NO. BOOT 1 O A bootstrap capacitor is required between BOOT and PH.
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TPS54040A SLVSB58A – MARCH 2012 – REVISED JANUARY 2014 www.ti.
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TPS54040A www.ti.com SLVSB58A – MARCH 2012 – REVISED JANUARY 2014 TYPICAL CHARACTERISTICS VOLTAGE REFERENCE vs JUNCTION TEMPERATURE 0.816 500 VI = 12 V VI = 12 V 375 Vref - Voltage Reference - V RDSON - Static Drain-Source On-State Resistance - mW ON RESISTANCE vs JUNCTION TEMPERATURE BOOT-PH = 3 V 250 BOOT-PH = 6 V 125 0 -50 0.808 0.800 0.792 0.784 -50 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 -25 0 150 Figure 1.
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TPS54040A SLVSB58A – MARCH 2012 – REVISED JANUARY 2014 www.ti.com TYPICAL CHARACTERISTICS (continued) EA TRANSCONDUCTANCE DURING SLOW START vs JUNCTION TEMPERATURE EA TRANSCONDUCTANCE vs JUNCTION TEMPERATURE 150 40 VI = 12 V VI = 12 V 130 110 gm - mA/V gm - mA/V 30 90 20 70 10 -50 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 50 -50 150 -25 0 25 50 75 100 125 150 TJ - Junction Temperature - °C Figure 7. Figure 8.
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TPS54040A www.ti.com SLVSB58A – MARCH 2012 – REVISED JANUARY 2014 TYPICAL CHARACTERISTICS (continued) SS/TR DISCHARGE CURRENT vs JUNCTION TEMPERATURE SWITCHING FREQUENCY vs VSENSE 120 100 VI = 12 V VI = 12 V, TJ = 25°C 80 % of Nominal fsw II(SS/TR) - mA 115 110 60 40 105 20 100 -50 0 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 150 0 SHUTDOWN SUPPLY CURRENT vs INPUT VOLTAGE (Vin) 2 TJ = 25°C I(VIN) - mA 1.5 1 0.5 1 0.
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TPS54040A SLVSB58A – MARCH 2012 – REVISED JANUARY 2014 www.ti.com TYPICAL CHARACTERISTICS (continued) PWRGD ON RESISTANCE vs JUNCTION TEMPERATURE PWRGD THRESHOLD vs JUNCTION TEMPERATURE 115 100 VI = 12 V PWRGD Threshold - % of Vref VI = 12 V RDSON - W 80 60 40 20 0 -50 VSENSE Rising 110 VSENSE Falling 105 100 VSENSE Rising 95 VSENSE Falling 90 -25 0 50 25 75 100 125 85 -50 150 -25 0 TJ - Junction Temperature - °C 150 Figure 20.
PAGE 11
TPS54040A www.ti.com SLVSB58A – MARCH 2012 – REVISED JANUARY 2014 OVERVIEW The TPS54040A device is a 42-V, 0.5-A, step-down (buck) regulator with an integrated high side n-channel MOSFET. To improve performance during line and load transients the device implements a constant frequency, current mode control which reduces output capacitance and simplifies external frequency compensation design.
PAGE 12
TPS54040A SLVSB58A – MARCH 2012 – REVISED JANUARY 2014 www.ti.com DETAILED DESCRIPTION Fixed Frequency PWM Control The TPS54040A uses an adjustable fixed frequency, peak current mode control. The output voltage is compared through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives the COMP pin. An internal oscillator initiates the turn on of the high side power switch. The error amplifier output is compared to the high side power switch current.
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TPS54040A www.ti.com SLVSB58A – MARCH 2012 – REVISED JANUARY 2014 DETAILED DESCRIPTION (continued) VOUT(ac) IL PH Figure 25. Pulse Skip Mode Operation Low Dropout Operation and Bootstrap Voltage (BOOT) The TPS54040A has an integrated boot regulator, and requires a small ceramic capacitor between the BOOT and PH pins to provide the gate drive voltage for the high side MOSFET. The BOOT capacitor is refreshed when the high side MOSFET is off and the low side diode conducts.
PAGE 14
TPS54040A SLVSB58A – MARCH 2012 – REVISED JANUARY 2014 www.ti.com DETAILED DESCRIPTION (continued) voltage is greater than 2.1 V, at which point the BOOT UVLO threshold is exceeded, and the device starts switching again until the desired output voltage is reached. This operating condition persists until the input voltage and/or the load current increases.
PAGE 15
TPS54040A www.ti.com SLVSB58A – MARCH 2012 – REVISED JANUARY 2014 DETAILED DESCRIPTION (continued) Enable and Adjusting Undervoltage Lockout The TPS54040A is disabled when the VIN pin voltage falls below 2.5 V. If an application requires a higher undervoltage lockout (UVLO), use the EN pin as shown in Figure 28 to adjust the input voltage UVLO by using the two external resistors.
PAGE 16
TPS54040A SLVSB58A – MARCH 2012 – REVISED JANUARY 2014 www.ti.com DETAILED DESCRIPTION (continued) R2 = VENA VSTART - VENA V + I1 - ENA R1 R3 (5) Do not place a low-impedance voltage source with greater than 5 V directly on the EN pin. Do not place a capacitor directly on the EN pin if VEN > 5 V when using a voltage divider to adjust the start and stop voltage. The node voltage, (see ) must remain equal to or less than 5.8 V. The zener diode can sink up to 100 µA.
PAGE 17
TPS54040A www.ti.com SLVSB58A – MARCH 2012 – REVISED JANUARY 2014 DETAILED DESCRIPTION (continued) EN SS/TR VSENSE VOUT Figure 31. Operation of SS/TR Pin when Starting Overload Recovery Circuit The TPS54040A has an overload recovery (OLR) circuit. The OLR circuit will slow start the output from the overload voltage to the nominal regulation voltage once the fault condition is removed.
PAGE 18
TPS54040A SLVSB58A – MARCH 2012 – REVISED JANUARY 2014 www.ti.com DETAILED DESCRIPTION (continued) TPS54040A EN PWRGD EN EN1 SS /TR SS /TR PWRGD1 PWRGD VOUT1 VOUT2 Figure 32. Schematic for Sequential Start-Up Sequence Figure 33. Sequential Startup using EN and PWRGD TPS54040A 3 EN 4 SS/TR 6 PWRGD EN1, EN2 VOUT1 TPS54040A VOUT2 3 EN 4 SS/TR 6 PWRGD Figure 34. Schematic for Ratiometric Start-Up Sequence Figure 35.
PAGE 19
TPS54040A www.ti.com SLVSB58A – MARCH 2012 – REVISED JANUARY 2014 DETAILED DESCRIPTION (continued) TPS54040A EN VOUT 1 SS/TR PWRGD TPS54040A VOUT 2 EN R1 SS/ TR R2 PWRGD R3 R4 Figure 36. Schematic for Ratiometric and Simultaneous Start-Up Sequence Ratio-metric and simultaneous power supply sequencing can be implemented by connecting the resistor network of R1 and R2 shown in Figure 36 to the output of the power supply that needs to be tracked or another voltage reference source.
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TPS54040A SLVSB58A – MARCH 2012 – REVISED JANUARY 2014 www.ti.com DETAILED DESCRIPTION (continued) R1 > 2800 ´ Vout1 - 180 ´ deltaV (10) spacer EN EN VOUT1 VOUT1 VOUT2 Figure 37. Ratio-metric Startup with Tracking Resistors VOUT2 Figure 38. Ratiometric Startup with Tracking Resistors EN VOUT1 VOUT2 Figure 39.
PAGE 21
TPS54040A www.ti.com SLVSB58A – MARCH 2012 – REVISED JANUARY 2014 DETAILED DESCRIPTION (continued) Constant Switching Frequency and Timing Resistor (RT/CLK Pin) The switching frequency of the TPS54040A is adjustable over a wide range from approximately 100kHz to 2500kHz by placing a resistor on the RT/CLK pin. The RT/CLK pin voltage is typically 0.5V and must have a resistor to ground to set the switching frequency.
PAGE 22
TPS54040A SLVSB58A – MARCH 2012 – REVISED JANUARY 2014 www.ti.com DETAILED DESCRIPTION (continued) Selecting the Switching Frequency The switching frequency that is selected should be the lower value of the two equations, Equation 12 and Equation 13. Equation 12 is the maximum switching frequency limitation set by the minimum controllable on time. Setting the switching frequency above this value will cause the regulator to skip switching pulses.
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TPS54040A www.ti.com SLVSB58A – MARCH 2012 – REVISED JANUARY 2014 DETAILED DESCRIPTION (continued) How to Interface to RT/CLK Pin The RT/CLK pin can be used to synchronize the regulator to an external system clock. To implement the synchronization feature connect a square wave to the RT/CLK pin through the circuit network shown in Figure 43. The square wave amplitude must transition lower than 0.5V and higher than 2.
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TPS54040A SLVSB58A – MARCH 2012 – REVISED JANUARY 2014 www.ti.com DETAILED DESCRIPTION (continued) PH PH EXT EXT IL IL Figure 44. Plot of Synchronizing in ccm Figure 45. Plot of Synchronizing in dcm PH EXT IL Figure 46.
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TPS54040A www.ti.com SLVSB58A – MARCH 2012 – REVISED JANUARY 2014 DETAILED DESCRIPTION (continued) Power Good (PWRGD Pin) The PWRGD pin is an open drain output. Once the VSENSE pin is between 94% and 107% of the internal voltage reference the PWRGD pin is de-asserted and the pin floats. It is recommended to use a pull-up resistor between the values of 10 and 100kΩ to a voltage source that is 5.5 V or less. The PWRGD is in a defined state once the VIN input voltage is greater than 1.
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TPS54040A SLVSB58A – MARCH 2012 – REVISED JANUARY 2014 www.ti.com DETAILED DESCRIPTION (continued) PH VO Power Stage gmps 1.9 A/V a b R1 RESR RL COMP c 0.8 V CO R3 C2 RO VSENSE COUT gmea 97 mA/V R2 C1 Figure 47. Small Signal Model for Loop Response Simple Small Signal Model for Peak Current Mode Control Figure 48 describes a simple small signal model that can be used to understand how to design the frequency compensation.
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TPS54040A www.ti.com SLVSB58A – MARCH 2012 – REVISED JANUARY 2014 DETAILED DESCRIPTION (continued) VO Adc VC RESR fp RL gmps COUT fz Figure 48.
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TPS54040A SLVSB58A – MARCH 2012 – REVISED JANUARY 2014 www.ti.com DETAILED DESCRIPTION (continued) VO R1 VSENSE gmea Type 2A COMP Type 2B Type 1 Vref R2 RO R3 CO C2 C1 R3 C2 C1 Figure 49. Types of Frequency Compensation Aol A0 P1 Z1 P2 A1 BW Figure 50.
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TPS54040A www.ti.com SLVSB58A – MARCH 2012 – REVISED JANUARY 2014 DETAILED DESCRIPTION (continued) Z1 = 1 2p ´ R3 ´ C1 P2 = (24) 1 2p ´ R3 | | RO ´ (C2 + CO ) type 2a (25) 1 P2 = type 2b 2p ´ R3 | | RO ´ CO P2 = (26) 1 type 1 2 p ´ R O ´ (C2 + C O ) (27) APPLICATION INFORMATION Design Guide — Step-By-Step Design Procedure This example details the design of a high frequency switching regulator design using ceramic output capacitors.
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TPS54040A SLVSB58A – MARCH 2012 – REVISED JANUARY 2014 www.ti.com U1 TPS4040ADGQ Figure 51. High Frequency, 5V Output Power Supply Design with Adjusted UVLO. Output Inductor Selection (LO) To calculate the minimum value of the output inductor, use Equation 28. KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. The inductor ripple current will be filtered by the output capacitor.
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TPS54040A www.ti.com IL(rms) = SLVSB58A – MARCH 2012 – REVISED JANUARY 2014 (IO ) 2 1 æ VOUT ´ (Vinmax - VOUT ) ö + ´ç ÷ ÷ 12 çè Vinmax ´ LO ´ fSW ø 2 (30) Iripple ILpeak = Iout + 2 (31) Output Capacitor There are three primary considerations for selecting the value of the output capacitor. The output capacitor will determine the modulator pole, the output voltage ripple, and how the regulators responds to a large change in load current.
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TPS54040A SLVSB58A – MARCH 2012 – REVISED JANUARY 2014 www.ti.com Capacitors generally have limits to the amount of ripple current they can handle without failing or producing excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor data sheets specify the Root Mean Square (RMS) value of the maximum ripple current. Equation 36 can be used to calculate the RMS ripple current the output capacitor needs to support.
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TPS54040A www.ti.com SLVSB58A – MARCH 2012 – REVISED JANUARY 2014 Input Capacitor The TPS54040A requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least 3 μF of effective capacitance and in some applications a bulk capacitance. The effective capacitance includes any dc bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage.
PAGE 34
TPS54040A SLVSB58A – MARCH 2012 – REVISED JANUARY 2014 www.ti.com The slow start time must be long enough to allow the regulator to charge the output capacitor up to the output voltage without drawing excessive current. Equation 40 can be used to find the minimum slow start time, tss, necessary to charge the output capacitor, Cout, from 10% to 90% of the output voltage, Vout, with an average slow start current of Issavg.
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TPS54040A www.ti.com SLVSB58A – MARCH 2012 – REVISED JANUARY 2014 ¦ z mod = 1 2 ´ p ´ Resr × Cout (42) fco = f p mod ´ f z mod (43) fco = f f p mod ´ sw 2 (44) To determine the compensation resistor, R4, use Equation 45. Assume the power stage transconductance, gmps, is 1.9A/V. The output voltage, VO, reference voltage, VREF, and amplifier transconductance, gmea, are 5 V, 0.8 V and 92 μA/V, respectively. R4 is calculated to be 77.1 kΩ, use the nearest standard value of 76.8kΩ.
PAGE 36
TPS54040A SLVSB58A – MARCH 2012 – REVISED JANUARY 2014 www.ti.com Figure 54. Output Ripple CCM Figure 55. Output Ripple, DCM Figure 56. Output Ripple, PSM Figure 57. Input Ripple CCM 100 90 80 VIN = 24 V Efficiency - % 70 VIN = 15 V VIN = 12 V VIN = 34 V 60 VIN = 42 50 40 30 20 10 VOUT = 5.0 V 0 0 Figure 58. Input Ripple DCM 36 0.05 0.10 0.15 0.20 0.25 0.30 0.35 IO - Output Current - A 0.40 0.45 0.50 Figure 59.
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TPS54040A www.ti.com SLVSB58A – MARCH 2012 – REVISED JANUARY 2014 100 60 180 40 120 150 90 80 Phase 90 70 Vin = 15 V Vin = 34 V 50 Vin = 12 V 30 Gain - dB Efficiency - % 20 60 Vin = 24 V Vin = 42 V 40 Gain 0 0 -30 -60 -20 30 Phase - o 60 -90 20 -40 -120 -60 -180 VOUT = 5.0 V 10 0 0 0.02 0.04 0.06 IO - Output Current - A -150 0.10 0.08 Figure 60. Light Load Efficiency 1-106 0.08 VI = 24 V IO = 0.2 A 0.06 0.04 0.04 Regulation (%) Regulation (%) 1-105 0.1 0.
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TPS54040A SLVSB58A – MARCH 2012 – REVISED JANUARY 2014 www.ti.com Power Dissipation Estimate The following formulas show how to estimate the IC power dissipation under continuous conduction mode (CCM) operation. These equations should not be used if the device is working in discontinuous conduction mode (DCM). The power dissipation of the IC includes conduction loss (Pcon), switching loss (Psw), gate drive loss (Pgd) and supply current (Pq).
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TPS54040A www.ti.com SLVSB58A – MARCH 2012 – REVISED JANUARY 2014 Layout Layout is a critical portion of good power supply design. There are several signals paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help eliminate these problems, the VIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor with X5R or X7R dielectric.
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TPS54040A SLVSB58A – MARCH 2012 – REVISED JANUARY 2014 VIN www.ti.com + CIN Cboot Lo BOOT VIN PH GND R1 Cd + Co GND R2 VOUT VSENSE EN SS/TR COMP Rcomp RT/CLK Css Cpole RT Czero Figure 65.
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TPS54040A www.ti.com SLVSB58A – MARCH 2012 – REVISED JANUARY 2014 REVISION HISTORY Changes from Original (March 2012) to Revision A Page • Deleted SWIFT from the data sheet Title and Features ....................................................................................................... 1 • Changed the values of the Hysteresis current in the Electrical Characteristics table .......................................................... 3 • Added paragraph and Figure 30 regarding node voltage ..
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 31-Oct-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 16-Apr-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS54040ADGQR MSOPPower PAD DGQ 10 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 TPS54040ADRCR SON DRC 10 3000 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2 TPS54040ADRCT SON DRC 10 250 180.0 12.4 3.3 3.3 1.0 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 16-Apr-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS54040ADGQR MSOP-PowerPAD DGQ 10 2500 346.0 346.0 35.0 TPS54040ADRCR SON DRC 10 3000 346.0 346.0 35.0 TPS54040ADRCT SON DRC 10 250 203.0 203.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.