Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - DC/DC voltage regulator Holder SON 8

VOUT

BOOT

VIN

RT /CLK

PowerPAD

VIN

VSNS

GND

VIN

TPS54061

COMP

100

0.001 0.010 0.100

Efficiency (%)

Load Current (A)

V = 12 V

V = 5 V, = 50 kHz

OUT SW

V = 5 V, = 400 kHz

V = 3.3 V, = 400 kHz

OUT SW

TPS54061

www.ti.com

SLVSBB7C –MAY 2012–REVISED JANUARY 2014

Wide Input 60V, 200mA Synchronous Step-Down DC-DC Converter with Low IQ

Check for Samples: TPS54061

FEATURES

DESCRIPTION

The TPS54061 device is a 60-V, 200-mA,

• Integrated High Side and Low Side MOSFET

synchronous step-down DC-DC converter with

• Diode Emulation for Improved Light Load

integrated high side and low side MOSFETs. Current

Efficiency

mode control provides simple external compensation

• Peak Current Mode Control

and flexible component selection. The non-switching

supply current is 90 µA. Using the enable pin,

• 90 µA Operating Quiescent Current

shutdown supply current is reduced to 1.4 µA.

• 1.4 µA Shutdown Supply Current

To increase light load efficiency the low side

• 50 kHz to 1100 kHz Adjustable Switching

MOSFET emulates a diode when the inductor current

Frequency

reaches zero.

• Synchronizes to External Clock

Under voltage lockout is internally set at 4.5 V, but

• Internal Slow Start

can be increased using two resistors on the enable

• 0.8 V ±1% Voltage Reference

pin. The output voltage startup ramp is controlled by

the internal slow start time.

• Stable with Ceramic Output Capacitors or Low

Cost Aluminum Electrolytic

The adjustable switching frequency range allows

• Cycle-by-Cycle Current Limit, Thermal, OVP

efficiency and external component size to be

optimized. Frequency foldback and thermal shutdown

and Frequency Fold Back Protection

protects the part during an overload condition.

• VSON-8 Package, 3 mm X 3 mm With Thermal

Pad

The TPS54061 enables small designs by integrating

the MOSFETs, boot recharge diode, and minimizing

• –40°C to 150°C Operating Junction

the IC footprint with a small 3mm x 3mm thermally

Temperature

enhanced VSON package

APPLICATIONS

The TPS54061 is supported in the Webench™

Designer at www.ti.com.

• 4-20 mA Current-Loop Powered Sensors

• Low Power Standby or Bias Voltage Supplies

Efficiency vs Load Current

• Industrial Process Control, Metering, and

Security Systems

• High Efficiency Replacement for High Voltage

Linear Regulators

SIMPLIFIED SCHEMATIC

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2Webench is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (38 pages)

PAGE 1
TPS54061 www.ti.com SLVSBB7C – MAY 2012 – REVISED JANUARY 2014 Wide Input 60V, 200mA Synchronous Step-Down DC-DC Converter with Low IQ Check for Samples: TPS54061 FEATURES DESCRIPTION • • The TPS54061 device is a 60-V, 200-mA, synchronous step-down DC-DC converter with integrated high side and low side MOSFETs. Current mode control provides simple external compensation and flexible component selection. The non-switching supply current is 90 µA.
PAGE 2
TPS54061 SLVSBB7C – MAY 2012 – REVISED JANUARY 2014 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Table 1.
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TPS54061 www.ti.
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TPS54061 SLVSBB7C – MAY 2012 – REVISED JANUARY 2014 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VALUE MAX VIN –0.3 62 V EN (2) –0.3 8 V 8 V BOOT-PH BOOT Voltage 70 V VSENSE –0.3 6 V COMP –0.3 3 V PH –0.6 62 V –2 62 V –0.
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TPS54061 www.ti.com SLVSBB7C – MAY 2012 – REVISED JANUARY 2014 ELECTRICAL CHARACTERISTICS (1) TEST CONDITIONS: TJ = –40°C to 150°C, VIN = 4.7 To 60 V ( (unless otherwise noted) PARAMETER CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE (VIN PIN) Operating input voltage VIN Shutdown supply current EN = 0V 4.7 1.4 60 V Iq Operating – Non switching VSENSE = 0.9V, VIN = 12V 90 110 µA 1.23 1.4 V µA ENABLE AND UVLO (EN PIN) Enable threshold Rising 1.18 V Enable threshold +50 mV –4.
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TPS54061 SLVSBB7C – MAY 2012 – REVISED JANUARY 2014 www.ti.com ELECTRICAL CHARACTERISTICS(1) (continued) TEST CONDITIONS: TJ = –40°C to 150°C, VIN = 4.7 To 60 V ( (unless otherwise noted) PARAMETER CONDITIONS PLL frequency range MIN TYP 300 MAX UNIT 1100 kHz PH Minimum On time Measured at 50% to 50%, IOUT = 200mA 120 ns Dead time VIN = 12V, IOUT = 200mA, One transition 30 ns VIN = 12V 6.0 V 2.9 V 2.
PAGE 7
TPS54061 www.ti.com SLVSBB7C – MAY 2012 – REVISED JANUARY 2014 TYPICAL CHARACTERISTICS SPACER 3 1.4 VIN = 12 V VIN = 12 V 1.2 Rdson - On Resistance - W Rdson - On Resistance - W 2.5 2 1.5 1 0.5 1 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 0 -50 150 -25 Figure 1. High Side RDS(on) vs Temperature 25 50 75 100 TJ - Junction Temperature - °C 125 150 Figure 2. Low Side RDS(on) vs Temperature 120 0.803 VIN = 12 V, RT = 120 kW TJ = 25°C 0.801 100 0.
PAGE 8
TPS54061 SLVSBB7C – MAY 2012 – REVISED JANUARY 2014 www.ti.com TYPICAL CHARACTERISTICS (continued) 1.26 140 VIN = 12 V VIN = 12 V VENA - Enable Voltage - V 120 Transconductance - mA/V VEN Rising 1.24 100 80 60 40 20 1.22 1.20 VEN Falling 1.18 1.16 1.14 1.12 0 -50 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 1.10 -50 150 -25 Figure 7. Error Amp Transconductance vs Temperature 0 25 50 75 100 TJ - Junction Temperature - °C 125 150 Figure 8.
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TPS54061 www.ti.com SLVSBB7C – MAY 2012 – REVISED JANUARY 2014 TYPICAL CHARACTERISTICS (continued) 98 2 EN = Open VSENSE = 0.83 V 96 EN = 0 V 1.75 Supply Current (µA) Supply Current (µA) 94 92 90 88 86 TJ = 150°C TJ = −40°C TJ = 25°C 84 82 80 0 5 10 15 20 25 30 35 40 Input Voltage (V) 45 50 55 TJ = 150°C TJ = −40°C TJ = 25°C 1.5 1.25 1 0.75 0.5 0.25 0 60 0 Figure 13. Supply Current (VIN pin) vs Input Voltage 4 5 G004 2.48 EN = Open TJ = 150°C 140 2.
PAGE 10
TPS54061 SLVSBB7C – MAY 2012 – REVISED JANUARY 2014 www.ti.com OVERVIEW The TPS54061 device is a 60 V, 200 mA, step-down (buck) regulator with an integrated high side and low side n-channel MOSFET. To improve performance during line and load transients the device implements a constant frequency, current mode control which reduces output capacitance and simplifies external frequency compensation design.
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TPS54061 www.ti.com SLVSBB7C – MAY 2012 – REVISED JANUARY 2014 DETAILED DESCRIPTION Fixed Frequency PWM Control The TPS54061 uses adjustable fixed frequency, peak current mode control. The output voltage is sensed through external resistors on the VSENSE pin and compared to an internal voltage reference by an error amplifier which drives the COMP pin. An internal oscillator initiates the turn on of the high side power switch. The error amplifier output is compared to the high side power switch current.
PAGE 12
TPS54061 SLVSBB7C – MAY 2012 – REVISED JANUARY 2014 www.ti.com VIN TPS54061 i1 ihys Ruvlo1 EN Optional VEN Ruvlo2 Figure 18.
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TPS54061 www.ti.com SLVSBB7C – MAY 2012 – REVISED JANUARY 2014 To enable higher switching frequency at high input voltages, the TPS54061 implements a frequency shift. The switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8 volts on VSENSE pin. The device implements a digital frequency shift to enable synchronizing to an external clock during normal startup and fault conditions.
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TPS54061 SLVSBB7C – MAY 2012 – REVISED JANUARY 2014 www.ti.com TPS54061 TPS54061 RT/CLK RT/CLK PLL PLL RT Clock Source Hi-Z Clock Source RT Figure 19. Synchronizing to a System Clock Overvoltage Protection The TPS54061 incorporates an output over-voltage transient protection (OVP) circuit to minimize voltage overshoot when recovering from output fault conditions or strong unload transients on power supply designs with low value output capacitance.
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TPS54061 www.ti.com SLVSBB7C – MAY 2012 – REVISED JANUARY 2014 DESIGN GUIDE – STEP-BY-STEP DESIGN PROCEDURE No.1 CBOOT 0.01 μF LO U1 TPS54061 100 μH 1 8 2 7 RUVLO1 3 6 CIN 196 kΩ 4 2.2 μF RUVLO2 8 V to 60 V * 36.5 kΩ RCOMP 143 kΩ RHS 31.6 kΩ CO 5 RT 3.3 V 200 mA 2 1 26.1 kΩ CPOLE CCOMP 33 pF 4700 pF 10 μF RLS 10 kΩ * See Enable and Adjusting Undervoltage Lockout section Figure 20.
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TPS54061 SLVSBB7C – MAY 2012 – REVISED JANUARY 2014 www.ti.com Output Inductor Selection (LO) To calculate the minimum value of the output inductor, use Equation 8. KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. The inductor ripple current will be filtered by the output capacitor.
PAGE 17
TPS54061 www.ti.com SLVSBB7C – MAY 2012 – REVISED JANUARY 2014 Using these values gives a minimum capacitance of 3.79 µF. This does not take the ESR of the output capacitor into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in this calculation. Aluminum electrolytic and tantalum capacitors have higher ESR that should be taken into account.
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TPS54061 SLVSBB7C – MAY 2012 – REVISED JANUARY 2014 www.ti.com because they have a high capacitance to volume ratio and are fairly stable over temperature. The effective value of a capacitor decreases as the dc bias across a capacitor increases. For this example design, a ceramic capacitor with at least a 60 V voltage rating is required to support the maximum input voltage. The input capacitance value determines the input ripple voltage of the regulator.
PAGE 19
TPS54061 www.ti.com SLVSBB7C – MAY 2012 – REVISED JANUARY 2014 RCOMP is calculated to be 25.9 kΩ, use the nearest standard value of 26.1 kΩ. Use Equation 24 to set the compensation zero equal to the modulator pole frequency. Equation 24 yields a 3790 pF for capacitor CCOMP and a 4700 pF is chosen. Use the larger value of Equation 25 and Equation 26 to calculate the CPOLE value, to set the compensation pole. Equation 26 yields 30.5 pF so the nearest standard of 33 pF is selected.
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TPS54061 SLVSBB7C – MAY 2012 – REVISED JANUARY 2014 www.ti.com Characteristics SPACER 90 90 80 80 70 70 Efficiency (%) 100 Efficiency (%) 100 60 50 40 30 VOUT = 3.3 V, FSW = 400 kHz 60 50 40 30 VIN = 8 V VIN = 12 V VIN = 24 V VIN = 36 V VIN = 60 V 20 VOUT = 3.3 V, FSW = 400 kHz 10 10 0 0 0.025 0.05 0.075 0.1 0.125 0.15 0.175 VIN = 8 V VIN = 12 V VIN = 24 V VIN = 36 V VIN = 60 V 20 0 0.001 0.2 0.
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TPS54061 www.ti.com SLVSBB7C – MAY 2012 – REVISED JANUARY 2014 Characteristics (continued) SPACER 0.50 VIN = 24 V, VOUT = 3.3 V, FSW = 400 kHz Output Voltage Normalized (%) 0.40 0.30 IOUT = 100 mA /div 0.20 0.10 0 –0.10 –0.20 –0.30 VOUT = 50 mV /div ac coupled –0.40 –0.50 0 0.025 0.05 0.075 0.1 0.125 0.15 0.175 0.2 500 μs /div Load Current (A) Figure 27. Output Voltage vs Output Current spacer Figure 28.
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TPS54061 SLVSBB7C – MAY 2012 – REVISED JANUARY 2014 www.ti.com Characteristics (continued) SPACER PH = 20 V /div PH = 20 V /div Inductor Current = 200 mA /div Inductor Current = 200 mA /div VIN = 50 mV /div ac coupled VIN = 10 mV /div ac coupled 2 μs /div 2 μs /div Figure 33. Input Ripple in CCM spacer Figure 34.
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TPS54061 www.ti.com SLVSBB7C – MAY 2012 – REVISED JANUARY 2014 DESIGN GUIDE – STEP-BY-STEP PROCEDURE Number 2 CBOOT 1 8 V to 40 V RUVLO1 CIN 2.2 µF 255 kΩ RUVLO2 45.3 kΩ 0.01 µF U1 LO TPS54061 220 µH 8 2 7 3 6 4 1 744 053 221 RCOMP 5 RT 1240 kΩ 5.0 V 2 RHS CO 35.7 kΩ CPOLE CCOMP 220 pF 0.33 µF 52.3 kΩ 22 µF RLS 10 kΩ Figure 38. DCM Application Schematic It is most desirable to have a power supply that is efficient and has a fixed switching frequency at low output currents.
PAGE 24
TPS54061 SLVSBB7C – MAY 2012 – REVISED JANUARY 2014 www.ti.com Use Equation 29, to make sure the minimum current limit on the high side power switch is not exceeded at the maximum output current. The peak current is calculated as 244 mA and is lower than the 350 mA current limit. To determine the rms current for the inductor and output capacitor, it is necessary to calculate the duty cycle. The duty cycle, D1, for a step down regulator in DCM is calculated in Equation 30.
PAGE 25
TPS54061 www.ti.com SLVSBB7C – MAY 2012 – REVISED JANUARY 2014 Closing the Feedback Loop The method presented here is easy to calculate and includes the effect of the slope compensation that is internal to the TPS54061. This method assumes the crossover frequency is between the modulator pole and the ESR zero and the ESR zero is at least 10 times greater than the modulator pole. Once the output components are determined, use the equations below to close the feedback loop.
PAGE 26
TPS54061 SLVSBB7C – MAY 2012 – REVISED JANUARY 2014 www.ti.com Characteristics SPACER 90 90 80 80 70 70 Efficiency (%) 100 Efficiency (%) 100 60 50 40 VOUT = 5 V, FSW = 50 kHz 60 50 40 30 30 VIN = 8 V VIN = 12 V VIN = 24 V VIN = 36 V 20 VOUT = 5 V, FSW = 50 kHz 10 10 0 0.001 0 0 0.025 0.05 0.075 VIN = 8 V VIN = 12 V VIN = 24 V VIN = 36 V 20 0.1 0.01 Load Current (A) Load Current (A) Figure 39. Efficiency vs Load Current Figure 40.
PAGE 27
TPS54061 www.ti.com SLVSBB7C – MAY 2012 – REVISED JANUARY 2014 Characteristics (continued) SPACER 0.25 VOUT = 100 mV /div ac coupled IOUT = 37.5 mA, FSW = 50 kHz 0.2 Output Voltage Normalized (%) 0.15 0.1 0.05 0 –0.05 –0.1 IOUT = 20 mA/div –0.15 –0.2 2 ms /div –0.25 0 10 20 30 40 50 60 Input Voltage (V) Figure 45. Output Voltage Normalized vs Input Voltage Figure 46.
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TPS54061 SLVSBB7C – MAY 2012 – REVISED JANUARY 2014 www.ti.com Characteristics (continued) SPACER PH = 20 V /div VIN = 10 V /div VIN = 100 nV /div ac coupled VOUT = 2 V /div VOUT = 50 mV /div ac coupled EN = 5 V /div IOUT = 50 mA/div Inductor current = 100 mA/div 10 ms /div 4 µs /div Figure 51. Prebias Startup With VIN spacer Figure 52.
PAGE 29
TPS54061 www.ti.com SLVSBB7C – MAY 2012 – REVISED JANUARY 2014 Layout Layout is a critical portion of good power supply design. There are several signals paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help eliminate these problems, the VIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor with X5R or X7R dielectric.
PAGE 30
TPS54061 SLVSBB7C – MAY 2012 – REVISED JANUARY 2014 www.ti.com REVISION HISTORY NOTE: Page numbers of current version may differ from previous versions. Changes from Original (May 2012) to Revision A Page • Changed title from "4.7V to 60V Input....." to "Wide Input...." and removed "Product Preview" banner .............................. 1 • Added Characteristics and Design Guide sections ............................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS54061DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS54061DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS54061DRBR SON DRB 8 3000 367.0 367.0 35.0 TPS54061DRBT SON DRB 8 250 210.0 185.0 35.
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