Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - DC/DC voltage regulator Holder SOIC 8

VIN

ENA

GND

VSENSE

BOOT

TPS5410

VIN VOUT

100

0 0.2 0.4 0.6 1 1.2 1.4

Efficiency − %

I OutputCurrent A

EfficiencyvsOutputCurrent

SimplifiedSchematic

=20V

V =12V

f =500kHz

T =25 C

0.8

TPS5410

www.ti.com

SLVS675C –AUGUST 2006–REVISED SEPTEMBER 2013

1-A, WIDE INPUT RANGE, STEP-DOWN CONVERTER

Check for Samples: TPS5410

FEATURES

APPLICATIONS

• Wide Input Voltage Range: 5.5 V to 36 V • Consumer: Set-top Box, DVD, LCD Displays

• Up to 1-A Continuous (1.2-A Peak) Output • Industrial and Car Audio Power Supplies

Current

• Battery Chargers, High Power LED Supply

• High Efficiency up to 95% Enabled by 110-mΩ

• 12-V/24-V Distributed Power Systems

Integrated MOSFET Switch

• Wide Output Voltage Range: Adjustable Down DESCRIPTION

to 1.22 V with 1.5% Initial Accuracy

The TPS5410 is a high-output-current PWM

converter that integrates a low resistance high side

• Internal Compensation Minimizes External

N-channel MOSFET. Included on the substrate with

Parts Count

the listed features is a high performance voltage error

• Fixed 500-kHz Switching Frequency for Small

amplifier that provides tight voltage regulation

Filter Size

accuracy under transient conditions; an undervoltage-

• Improved Line Regulation and Transient

lockout circuit to prevent start-up until the input

voltage reaches 5.5 V; an internally set slow-start

Response by Input Voltage Feed Forward

circuit to limit inrush currents; and a voltage feed-

• System Protected by Over Current Limiting,

forward circuit to improve the transient response.

Over Voltage Protection and Thermal

Using the ENA pin, shutdown supply current is

Shutdown

reduced to 18 μA typically. Other features include an

• –40°C to 125°C Operating Junction

active high enable, overcurrent limiting, overvoltage

Temperature Range

protection and thermal shutdown. To reduce design

complexity and external component count, the

• Available in Small 8-Pin SOIC Package

TPS5410 feedback loop is internally compensated.

The TPS5410 device is available in an easy to use 8-

pin SOIC package. TI provides evaluation modules

and software tools to aid in quickly achieving high-

performance power supply designs to meet

aggressive equipment development cycles.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (26 pages)

PAGE 1
TPS5410 www.ti.com SLVS675C – AUGUST 2006 – REVISED SEPTEMBER 2013 1-A, WIDE INPUT RANGE, STEP-DOWN CONVERTER Check for Samples: TPS5410 FEATURES APPLICATIONS • • • • • • 1 • • • • • • • • Wide Input Voltage Range: 5.5 V to 36 V Up to 1-A Continuous (1.2-A Peak) Output Current High Efficiency up to 95% Enabled by 110-mΩ Integrated MOSFET Switch Wide Output Voltage Range: Adjustable Down to 1.22 V with 1.
PAGE 2
TPS5410 SLVS675C – AUGUST 2006 – REVISED SEPTEMBER 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) (2) TJ INPUT VOLTAGE OUTPUT VOLTAGE PACKAGE (1) PART NUMBER –40°C to 125°C 5.5 V to 36 V Adjustable to 1.
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TPS5410 www.ti.com SLVS675C – AUGUST 2006 – REVISED SEPTEMBER 2013 RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT VI Input voltage range, VIN 5.5 36 V TJ Operating junction temperature –40 125 °C TYP MAX UNIT 3 4.4 mA 18 50 μA Start threshold voltage, UVLO 5.3 5.5 Hysteresis voltage, UVLO 330 ELECTRICAL CHARACTERISTICS TJ = –40°C to 125°C, VIN = 5.
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TPS5410 SLVS675C – AUGUST 2006 – REVISED SEPTEMBER 2013 www.ti.com PIN ASSIGNMENTS D PACKAGE (TOP VIEW) BOOT 1 8 PH NC 2 7 VIN NC 3 6 GND VSENSE 4 5 ENA TERMINAL FUNCTIONS TERMINAL NAME DESCRIPTION NO. BOOT 1 NC 2, 3 Boost capacitor for the high-side FET gate driver. Connect 0.01 μF low ESR capacitor from BOOT pin to PH pin. Not connected internally. VSENSE 4 Feedback voltage for the regulator. Connect to output voltage divider. ENA 5 On/off control. Below 0.
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TPS5410 www.ti.com SLVS675C – AUGUST 2006 – REVISED SEPTEMBER 2013 TYPICAL CHARACTERISTICS OSCILLATOR FREQUENCY vs JUNCTION TEMPERATURE OPERATING QUIESCENT CURRENT vs JUNCTION TEMPERATURE 530 f − Oscillator Frequency − kHz 510 500 490 480 470 460 -50 180 VI = 12 V 170 Minimum Controllable On Time − ns IQ − Operating Quiescent Current − mA 3.5 520 3.25 3 2.75 2.
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TPS5410 SLVS675C – AUGUST 2006 – REVISED SEPTEMBER 2013 www.ti.com APPLICATION INFORMATION FUNCTIONAL BLOCK DIAGRAM VIN VIN 1.221 V Bandgap Reference UVLO VREF SHDN Slow Start Boot Regulator BOOT HICCUP 5 µA ENABLE ENA SHDN SHDN VSENSE Z1 Thermal Protection NC SHDN VIN Ramp Generator NC SHDN VSENSE HICCUP PWM Comparator Overcurrent Protection Oscillator OVP Z2 Feed Forward Gain = 25 SHDN GND Error Amplifier SHDN SHDN Gate Drive Control 112.
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TPS5410 www.ti.com SLVS675C – AUGUST 2006 – REVISED SEPTEMBER 2013 Undervoltage Lockout (UVLO) The TPS5410 incorporates an undervoltage lockout circuit to keep the device disabled when VIN (the input voltage) is below the UVLO start voltage threshold. During power up, internal circuits are held inactive and the internal slow start is grounded until VIN exceeds the UVLO start threshold voltage. Once the UVLO start threshold voltage is reached, the internal slow start is released and device start-up begins.
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TPS5410 SLVS675C – AUGUST 2006 – REVISED SEPTEMBER 2013 www.ti.com Overvoltage Protection The TPS5410 has an overvoltage protection (OVP) circuit to minimize voltage overshoot when recovering from output fault conditions. The OVP circuit includes an overvoltage comparator to compare the VSENSE pin voltage and a threshold of 112.5% x VREF. Once the VSENSE pin voltage is higher than the threshold, the high-side MOSFET will be forced off.
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TPS5410 www.ti.com SLVS675C – AUGUST 2006 – REVISED SEPTEMBER 2013 PH BOOT CAPACITOR OUTPUT INDUCTOR RESISTOR DIVIDER VOUT BOOT PH NC VIN NC GND VSENSE ENA OUTPUT FILTER CAPACITOR Route feedback trace under the output filter capacitor or on the other layer. CATCH DIODE INPUT INPUT BULK BYPASS CAPACITOR FILTER Vin TOPSIDE GROUND AREA VIA to Ground Plane Signal VIA Figure 9.
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TPS5410 www.ti.com 0.050 SLVS675C – AUGUST 2006 – REVISED SEPTEMBER 2013 0.026 0.220 0.080 All dimensions in inches Figure 10. TPS5410 Land Pattern Application Circuits Figure 11 shows the schematic for a typical TPS5410 application. The TPS5410 can provide up to 1-A output current at a nominal output voltage of 12 V. U1 TPS5410D 14.5 V - 36 V 7 VIN ENA C1 4.7 mF VIN 5 ENA 2 NC 3 NC 6 GND C2 0.01 mF BOOT 1 PH 8 VSNS 4 L1 68 mH 12 V VOUT + D1 B340A C3 47 mF (See Note A) R1 10 kW R2 1.
PAGE 11
TPS5410 www.ti.com SLVS675C – AUGUST 2006 – REVISED SEPTEMBER 2013 Design Procedure The following design procedure can be used to select component values for the TPS5410. Alternately, see the TI Web site at www.ti.com for any available software tools to aid in the design process. This section presents a simplified discussion of the design process. To • • • • • • begin the design process, a few parameters must be determined.
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TPS5410 SLVS675C – AUGUST 2006 – REVISED SEPTEMBER 2013 www.ti.com CAUTION The maximum ratings for voltage and current are not to be exceeded under any circumstance. Additionally, some bulk capacitance may be needed, especially if the TPS5410 circuit is not located within approximately 2 inches from the input voltage source.
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TPS5410 www.ti.com SLVS675C – AUGUST 2006 – REVISED SEPTEMBER 2013 design of the internal compensation, it is recommended to keep the closed loop crossover frequency in the range 3 kHz to 30 kHz as this frequency range has adequate phase boost to allow for stable operation. For this design example, the intended closed loop crossover frequency is between 2590 Hz and 24 kHz, and below the ESR zero of the output capacitor.
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TPS5410 SLVS675C – AUGUST 2006 – REVISED SEPTEMBER 2013 www.ti.com Output Voltage Setpoint The output voltage of the TPS5410 is set by a resistor divider (R1 and R2) from the output to the VSENSE pin. Calculate the R2 resistor value for the output voltage of 12 V using Equation 12: R1 1.221 R2 + V * 1.221 OUT (12) For any TPS5410 design, start with an R1 value of 10 kΩ. R2 is then 1.13 kΩ. Boot Capacitor The boot capacitor should be 0.01 μF.
PAGE 15
TPS5410 www.ti.com SLVS675C – AUGUST 2006 – REVISED SEPTEMBER 2013 The minimum capacitor value is calculated to be 7.6 μF. For this circuit a larger value of capacitor will yield better transient response. Two output capacitors are used for C3 and C4 with a value of 47 uF each. It is important to note that the actual capacitance of ceramic capacitors decreases with applied voltage. In this case the effective value used for the calculations is approximately 70 % of the rated value or 70 μF.
PAGE 16
TPS5410 SLVS675C – AUGUST 2006 – REVISED SEPTEMBER 2013 www.ti.com ADVANCED INFORMATION Output Voltage Limitations Due to the internal design of the TPS5410, there are both upper and lower output voltage limits for any given input voltage. The upper limit of the output voltage set point is constrained by the maximum duty cycle of 87% and is given by: V OUTMAX + 0.87 ǒǒVINMIN * I OMAX Ǔ Ǔ ǒ 0.
PAGE 17
TPS5410 www.ti.com SLVS675C – AUGUST 2006 – REVISED SEPTEMBER 2013 Thermal Calculations The following formulas show how to estimate the device power dissipation under continuous conduction mode operations. They should not be used if the device is working at light loads in the discontinuous conduction mode. Conduction Loss: Pcon = IOUT 2 x Rds(on) x VOUT / VIN Switching Loss: Psw = VIN x IOUT x 0.01 Quiescent Current Loss: Pq = VIN x 0.
PAGE 18
TPS5410 SLVS675C – AUGUST 2006 – REVISED SEPTEMBER 2013 www.ti.com VI = 10 V/div ENA = 2 V/div VO = 5 V/div VO = 5 V/div t - Time - 5 ms / Div t - Time - 5 ms / Div Figure 19. Startup Waveform, VI and VO Figure 20. Startup Waveform, ENA and VO PERFORMANCE GRAPHS The performance graphs in Figure 21 - Figure 26 are applicable to the circuit in Figure 12. TA = 25 °C. unless otherwise specified. 0.1 100 0.08 VI = 15 V Efficiency - % 95 90 85 VI = 30 V 80 VI = 35 V 0.2 0.4 0.6 0.
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TPS5410 www.ti.com SLVS675C – AUGUST 2006 – REVISED SEPTEMBER 2013 REVISION HISTORY Changes from Original (August 2006) to Revision A Page • Changed the Efficiency vs Output Current graph ................................................................................................................. 1 • Changed the Functional Block Diagram ...............................................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 5-Sep-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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PACKAGE MATERIALS INFORMATION www.ti.com 5-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS5410DR Package Package Pins Type Drawing SOIC D 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 6.4 B0 (mm) K0 (mm) P1 (mm) 5.2 2.1 8.0 W Pin1 (mm) Quadrant 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 5-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS5410DR SOIC D 8 2500 367.0 367.0 35.
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