Datasheet

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TPS54110−Q1

SLVS837 − JULY 2008

3-V TO 6-V INPUT, 1.5-A OUTPUT SYNCHRONOUS-BUCK PWM

SWITCHER WITH INTEGRATED FETs (SWIFT)

(6,3 mm x 6,4 mm)

Typical Size

FEATURES

D Qualified for Automotive Applications

D Integrated MOSFET Switches for High

Efficiency at 1.5-A Continuous Output Source

or Sink Current

D 0.9-V to 3.3-V Adjustable Output Voltage With

1% Accuracy

D Externally Compensated for Design Flexibility

D Fast Transient Response

D Wide PWM Frequency: Fixed 350 kHz,

550 kHz, or Adjustable 280 kHz to 700 kHz

D Load Protected by Peak Current Limit and

Thermal Shutdown

D Integrated Solution Reduces Board Area and

Total Cost

APPLICATIONS

D Low-Voltage, High-Density Systems With

Power Distributed at 5 V or 3.3 V

D Point of Load Regulation for High

Performance DSPs, FPGAs, ASICs, and

Microprocessors

D Broadband, Networking, and Optical

Communications Infrastructure

D Portable Computing/Notebook PCs

DESCRIPTION

As members of the SWIFT family of dc/dc regulators, the

TPS54110 low-input-voltage high-output-current

synchronous-buck PWM converter integrates all required

active components. Included on the substrate with the

listed features are a true, high-performance, voltage error

amplifier that provides high performance under transient

conditions; an undervoltage-lockout circuit to prevent

start-up until the input voltage reaches 3 V; an internally

and externally set slow-start circuit to limit in-rush currents;

and a power-good output useful for processor/logic reset,

fault signaling, and supply sequencing.

The TPS54110 device is available in a thermally enhanced

20-pin TSSOP (PWP) PowerPAD package, which

eliminates bulky heatsinks. TI provides evaluation

modules and the SWIFT

designer software tool to aid in

quickly achieving high-performance power supply designs

to meet aggressive equipment development cycles.

VIN

TPS54110

BOOT

PGND

COMP

VSENSE

AGND

VBIAS

Compensation

Network

Input Output

Simplified Schematic

100

0 0.25 0.5 0.75 1 1.25 1.5

− Output Current − A

Efficiency − %

EFFICIENCY

OUTPUT CURRENT

100 mF

2200 pF

0.047 mF

0.1 mF

10 mF

3.92 kW

2.05 kW

3.92 kW

19.1 kW

6.8 mH

2700 pF

33 pF

PRODUCTION DATA information is current as of publication date. Products

conform to specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all parameters.

PowerPAD and SWIFT are trademarks of Texas Instruments.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

www.ti.com

Summary of content (27 pages)

PAGE 1
Typical Size (6,3 mm x 6,4 mm) TPS54110−Q1 www.ti.com SLVS837 − JULY 2008 3-V TO 6-V INPUT, 1.5-A OUTPUT SYNCHRONOUS-BUCK PWM SWITCHER WITH INTEGRATED FETs (SWIFT) FEATURES D Qualified for Automotive Applications D Integrated MOSFET Switches for High D D D D D D DESCRIPTION As members of the SWIFT family of dc/dc regulators, the TPS54110 low-input-voltage high-output-current synchronous-buck PWM converter integrates all required active components.
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TPS54110−Q1 www.ti.com SLVS837 − JULY 2008 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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TPS54110−Q1 www.ti.com SLVS837 − JULY 2008 ELECTRICAL CHARACTERISTICS TJ = −40°C to 125°C, VIN = 3 V to 6 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX fs = 350 kHz, SYNC ≤ 0.8 V, RT open 4.5 9.6 fs = 550 kHz, Phase pin open, SYNC 2.5 V, RT open, 5.8 12.8 1 1.4 2.95 3 UNIT SUPPLY VOLTAGE, VIN VIN input voltage range Quiescent current 3 Shutdown, SS/ENA = 0 V 6 V mA UNDER VOLTAGE LOCK OUT Start threshold voltage, UVLO Stop threshold voltage, UVLO 2.
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TPS54110−Q1 www.ti.
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TPS54110−Q1 www.ti.com SLVS837 − JULY 2008 PIN ASSIGNMENTS PWP PACKAGE (TOP VIEW) AGND VSENSE COMP PWRGD BOOT PH PH PH PH PH 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 RT SYNC SS/ENA VBIAS VIN VIN VIN PGND PGND PGND Terminal Functions TERMINAL NAME DESCRIPTION NO. AGND 1 Analog ground—internally connected to the sensitive analog-ground circuitry. Connect to PGND and PowerPAD. BOOT 5 Bootstrap input. 0.022-µF to 0.
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TPS54110−Q1 www.ti.com SLVS837 − JULY 2008 FUNCTIONAL BLOCK DIAGRAM VBIAS AGND VIN Enable Comparator SS/ENA Falling Edge Deglitch 1.2 V Hysteresis: 0.03 V 2.5 µs VIN UVLO Comparator VIN 2.95 V Hysteresis: 0.16 V REG VBIAS SHUTDOWN VIN ILIM Comparator Thermal Shutdown 150°C 3−6V Leading Edge Blanking Falling and Rising Edge Deglitch 100 ns BOOT 2.5 µs SS_DIS SHUTDOWN Internal/External Slow-start (Internal Slow-start Time = 3.35 ms PH + − R Q Error Amplifier Reference VREF = 0.
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TPS54110−Q1 www.ti.com SLVS837 − JULY 2008 TYPICAL CHARACTERISTICS IO = 1.5 A 0.5 VI = 5 V 0.4 0.3 0.2 0.1 IO = 1.5 A 0.3 0.2 0.1 0 −40 0 −40 0 25 85 125 0 125 85 TJ − Junction Temperature − °C TJ − Junction Temperature − °C Figure 1 600 RT = 100 k 500 400 RT = 180 k 300 25 85 125 0.893 0.891 0.889 0.887 SYNC ≤ 0.8 V 350 250 −40 0 0 Figure 4 25 85 125 0.8910 0.8890 fS = 350 kHz 0.8870 3 3.
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TPS54110−Q1 www.ti.com SLVS837 − JULY 2008 APPLICATION INFORMATION Figure 9 shows the schematic diagram for a typical TPS54110 application. The TPS54110 can provide up to 1.5 A of output current at a nominal output voltage of 3.3 V. For proper thermal performance, the exposed PowerPAD under the device must be soldered down to the printed-circuit board. R7 10 kW VIN (4.5 − 5.5 V) C8 2200 pF PWRGD + R4 71.5 kW C1 10 mF U2 TPS54110PWP 20 19 18 17 16 15 14 C5 .047 mF C4 0.
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TPS54110−Q1 www.ti.com SLVS837 − JULY 2008 INPUT CAPACITORS The TPS54110 requires an input decoupling capacitor and, depending on the application, a bulk input capacitor. The minimum value for the decoupling capacitor, C9, is 10 µF. A high-quality ceramic type X5R or X7R with a voltage rating greater than the maximum input voltage is recommended. A bulk input capacitor may be needed, especially if the TPS54110 circuit is not located within approximately 2 inches from the input voltage source.
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TPS54110−Q1 www.ti.com SLVS837 − JULY 2008 where K is the frequency multiplier for the spread between fLC and fCO. K should be between 5 and 15, typically 10 for one decade of difference. For a desired crossover of 60 kHz, K=10 and a 6.8 µH inductor, the minimum value for the output capacitor is 100 µF. The selected output capacitor must be rated for a voltage greater than the desired output voltage plus one half the ripple voltage. Any derating factors must also be included.
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TPS54110−Q1 www.ti.com SLVS837 − JULY 2008 C6 + 1 2pR1ƒ INT (17) Since C6 is calculated to be 2900 pF, and the location of the integrator crossover frequency is important in setting the overall loop crossover, adjust the value of R1 so that C6 is a standard value of 2700 pF, using equation 18: R1 + 1 2pC6ƒ LC (18) The value for R1 is 10.
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TPS54110−Q1 www.ti.com SLVS837 − JULY 2008 GROUNDING AND PowerPAD LAYOUT The TPS54110 has two internal grounds (analog and power). Inside the TPS54110, the analog ground connects all noise-sensitive signals, while the power ground connects the noisier power signals. The PowerPAD must be tied directly to AGND. Noise injected between the two grounds can degrade the performance of the TPS54110, particularly at higher output currents.
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TPS54110−Q1 www.ti.com SLVS837 − JULY 2008 PERFORMANCE GRAPHS All performance data shown for VI = 5 V, VO = 3.3 V, fs = 700 kHz, TA = 25°C, Figure 9 EFFICIENCY vs OUTPUT CURRENT POWER DISSIPATION vs OUTPUT CURRENT 1.2 100 LOAD REGULATION vs OUTPUT CURRENT 0.05 95 Efficiency − % 85 80 75 70 65 60 1 Output Voltage Varistion − % P D − Power Dissipation − W 0.04 90 0.8 0.6 0.4 0.2 0.03 0.02 0.01 0 −0.01 −0.02 −0.03 −0.04 55 50 0 0.25 0.5 0.75 1 1.25 1.5 −0.05 0 0 0.25 0.5 0.
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TPS54110−Q1 www.ti.com SLVS837 − JULY 2008 Very−small form-factor application R7 10 kW VIN C8 560 pF PWRGD + R4 71.5 kW C1 OPEN U2 TPS54110PWP 20 19 18 17 16 15 14 C5 OPEN C4 0.1 mF C9 10 mF 13 12 11 RT AGND SYNC SS/ENA VSENSE COMP VBIAS PWRGD VIN BOOT VIN PH VIN PH PGND PH PGND PH R3 1.74 kW 1 C6 1000 pF 2 3 4 5 R5 432 W R1 10.0 kW R2 14.7 kW C7 47 pF C3 0.047 mF 6 7 8 10 PGND PH PwrPd 21 L1 1 mH 9 1 2 1.5 V at 1.5 A C2 10 mF Figure 20.
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TPS54110−Q1 www.ti.com SLVS837 − JULY 2008 All performance data shown for VI = 5 V, VO = 1.5 V, FS = 700 kHz, TA = 25_C, Figure 20 POWER DISSIPATION vs OUTPUT CURRENT EFFICIENCY vs OUTPUT CURRENT 0.1 95 0.08 85 VI = 5 V 80 75 70 65 60 1.2 Output Voltage Varistion − % P D − Power Dissipation − W 100 90 Efficiency − % LOAD REGULATION vs OUTPUT CURRENT 1 0.8 0.6 VI = 5 V 0.4 VI = 3.3 V 0.2 55 0 0 0.25 0.5 0.75 1 1.25 0 1.5 0.04 0.02 VI = 3.3 V 0 −0.02 −0.04 VI = 5 V −0.06 −0.
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TPS54110−Q1 www.ti.com SLVS837 − JULY 2008 TWO-OUTPUT SEQUENCED-STARTUP APPLICATION PWRGD_3P3 VI 5 V R7 C8 560 pF 10 kΩ + C1 470 µF R4 71.5 kΩ U1 TPS54110PWP 20 19 18 17 16 C4 0.1 µF C9 10 µF 15 14 13 12 11 RT AGND SYNC VSENSE SS/ENA COMP VBIAS PWRGD VIN BOOT VIN PH VIN PH PGND PH PH PGND PGND PH PWPD 21 1 2 3 4 5 6 C6 R3 1.74 kΩ 1000 pF R1 10 kΩ R2 3.74 kΩ C7 47 pF C3 0.047 µF 7 8 9 L1 1 µH 10 1 C2 10 µF PWRGD_1P5 C13 560 pF 10 kΩ U2 TPS54110PWP 20 19 18 17 16 C10 0.
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TPS54110−Q1 www.ti.com SLVS837 − JULY 2008 DETAILED DESCRIPTION Under Voltage Lock Out (UVLO) The TPS54110 incorporates an under voltage lockout circuit to keep the device disabled when the input voltage (VIN) is insufficient. During power up, internal circuits are held inactive until VIN exceeds the nominal UVLO threshold voltage of 2.95 V. Once the UVLO start threshold is reached, device start-up begins. The device operates until VIN falls below the nominal UVLO stop threshold of 2.8 V.
PAGE 18
TPS54110−Q1 www.ti.com SLVS837 − JULY 2008 range of output L- and C-filter components to suit the particular application needs. Type-2 or type-3 compensation can be employed using external compensation components. PWM Control Signals from the error-amplifier output, oscillator, and current-limit circuit are processed by the PWM control logic.
PAGE 19
TPS54110−Q1 www.ti.com SLVS837 − JULY 2008 PCB LAYOUT CONSIDERATIONS pins, and minimize the area of the conductor to prevent excessive capacitive coupling. Connect the boot capacitor between the phase node and the BOOT pin as shown. Keep the boot capacitor close to the IC and minimize the conductor trace lengths. Connect the output-filter capacitor(s) as shown between the VOUT trace and PGND. It is important to keep the loop formed by the PH pins, Lout, Cout, and PGND as small as is practical.
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PACKAGE OPTION ADDENDUM www.ti.com 24-Jan-2013 PACKAGING INFORMATION Orderable Device Status (1) TPS54110QPWPRQ1 ACTIVE Package Type Package Pins Package Qty Drawing HTSSOP PWP 20 2000 Eco Plan Lead/Ball Finish (2) Green (RoHS & no Sb/Br) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) CU NIPDAU Level-3-260C-168 HR (4) -40 to 125 54110Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS54110QPWPRQ1 Package Package Pins Type Drawing SPQ HTSSOP 2000 PWP 20 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 16.4 Pack Materials-Page 1 6.95 B0 (mm) K0 (mm) P1 (mm) 7.1 1.6 8.0 W Pin1 (mm) Quadrant 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS54110QPWPRQ1 HTSSOP PWP 20 2000 367.0 367.0 38.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.