Datasheet

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EFFICIENCY

LOADCURRENT

0 0.25 0.50 0.75 1 1.25 1.50 1.75 2

LoadCurrent- A

Efficiency-%

V =12V,

V =3.3V,

f =1200kHz

VIN

GND

BOOT

VSENSE

COMP

TPS54140A

RT /CLK

SS /TR

PWRGD

VIN

OUT

TPS54140A

www.ti.com

SLVSB55B –MAY 2012–REVISED JANUARY 2014

1.5-A, 42 V Step Down DC/DC Converter with Eco-mode™

Check for Samples: TPS54140A

FEATURES

• 3.5 V to 42 V Input Voltage Range

• UV and OV Power Good Output

• 200-mΩ High-Side MOSFET • 0.8-V Internal Voltage Reference

• High Efficiency at Light Loads with a Pulse • MSOP10 and 3mm x 3mm VSON-10 Package

Skipping Eco-mode™ With PowerPAD™

• Tighter Enable Threshold than TPS54140 for • Supported by WEBENCH

and SwitcherPro™

More Accurate UVLO Voltage Software Tool

• Adjustable UVLO Voltage and Hysteresis

APPLICATIONS

• 116 μA Operating Quiescent Current

• 12-V and 24-V Industrial and Commercial Low

• 1.3 μA Shutdown Current

Power Systems

• 100 kHz to 2.5 MHz Switching Frequency

• Aftermarket Auto Accessories: Video, GPS,

• Synchronizes to External Clock

Entertainment

• Adjustable Slow Start/Sequencing

DESCRIPTION

The TPS54140A device is a 42 V, 1.5 A, step down regulator with an integrated high side MOSFET. Current

mode control provides simple external compensation and flexible component selection. A low ripple pulse skip

mode reduces the no load, regulated output supply current to 116 μA. Using the enable pin, shutdown supply

current is reduced to 1.3 μA.

Under voltage lockout is internally set at 2.5 V, but can be increased using the enable pin. The output voltage

startup ramp is controlled by the slow start pin that can also be configured for sequencing/tracking. An open

drain power good signal indicates the output is within 94% to 107% of its nominal voltage.

A wide switching frequency range allows efficiency and external component size to be optimized. Frequency fold

back and thermal shutdown protects the part during an overload condition.

spacer

SIMPLIFIED SCHEMATIC

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2Eco-mode, PowerPAD, SwitcherPro are trademarks of Texas Instruments.

3WEBENCH is a registered trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (52 pages)

PAGE 1
TPS54140A www.ti.com SLVSB55B – MAY 2012 – REVISED JANUARY 2014 1.5-A, 42 V Step Down DC/DC Converter with Eco-mode™ Check for Samples: TPS54140A FEATURES 1 • • • 23 • • • • • • • 3.5 V to 42 V Input Voltage Range 200-mΩ High-Side MOSFET High Efficiency at Light Loads with a Pulse Skipping Eco-mode™ Tighter Enable Threshold than TPS54140 for More Accurate UVLO Voltage Adjustable UVLO Voltage and Hysteresis 116 μA Operating Quiescent Current 1.3 μA Shutdown Current 100 kHz to 2.
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TPS54140A SLVSB55B – MAY 2012 – REVISED JANUARY 2014 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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TPS54140A www.ti.com SLVSB55B – MAY 2012 – REVISED JANUARY 2014 THERMAL INFORMATION TPS54140A THERMAL METRIC (1) (2) DGQ (10-PIN) DRC (10 PINS) 62.5 40 83 65 θJA Junction-to-ambient thermal resistance (standad board) θJCtop Junction-to-case (top) thermal resistance θJB Junction-to-board thermal resistance 28 8 ψJT Junction-to-top characterization parameter 1.7 0.6 ψJB Junction-to-board characterization parameter 20.1 7.5 θJCbot Junction-to-case (bottom) thermal resistance 21 7.
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TPS54140A SLVSB55B – MAY 2012 – REVISED JANUARY 2014 www.ti.com ELECTRICAL CHARACTERISTICS (continued) TJ = –40°C to 150°C, VIN = 3.5 to 42V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 1.8 2.
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TPS54140A www.ti.com SLVSB55B – MAY 2012 – REVISED JANUARY 2014 DEVICE INFORMATION PIN CONFIGURATION MSOP-10 (TOP VIEW) VSON-10 (TOP VIEW) BOOT 1 10 PH VIN 2 9 GND Thermal Pad (11) EN 3 SS/TR 4 RT/CLK 5 8 COMP BOOT 1 VIN 2 10 Thermal Pad (11) PH 9 GND 8 COMP EN 3 7 VSENSE SS/TR 4 7 VSENSE 6 PWRGD RT/CLK 5 6 PWRGD PIN FUNCTIONS PIN I/O DESCRIPTION NAME NO. BOOT 1 O A bootstrap capacitor is required between BOOT and PH.
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TPS54140A SLVSB55B – MAY 2012 – REVISED JANUARY 2014 www.ti.
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TPS54140A www.ti.com SLVSB55B – MAY 2012 – REVISED JANUARY 2014 TYPICAL CHARACTERISTICS VOLTAGE REFERENCE vs JUNCTION TEMPERATURE 0.816 500 VI = 12 V VI = 12 V 375 Vref - Voltage Reference - V RDSON - Static Drain-Source On-State Resistance - mW ON RESISTANCE vs JUNCTION TEMPERATURE BOOT-PH = 3 V 250 BOOT-PH = 6 V 125 0 -50 0.808 0.800 0.792 0.784 -50 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 -25 0 150 Figure 1.
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TPS54140A SLVSB55B – MAY 2012 – REVISED JANUARY 2014 www.ti.com TYPICAL CHARACTERISTICS (continued) EA TRANSCONDUCTANCE DURING SLOW START vs JUNCTION TEMPERATURE EA TRANSCONDUCTANCE vs JUNCTION TEMPERATURE 150 40 VI = 12 V VI = 12 V 130 110 gm - mA/V gm - mA/V 30 90 20 70 10 -50 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 50 -50 150 -25 0 25 50 75 100 125 150 TJ - Junction Temperature - °C Figure 7. Figure 8.
PAGE 9
TPS54140A www.ti.com SLVSB55B – MAY 2012 – REVISED JANUARY 2014 TYPICAL CHARACTERISTICS (continued) SS/TR DISCHARGE CURRENT vs JUNCTION TEMPERATURE SWITCHING FREQUENCY vs VSENSE 120 100 VI = 12 V VI = 12 V, TJ = 25°C 80 % of Nominal fsw II(SS/TR) - mA 115 110 60 40 105 20 100 -50 0 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 150 0 SHUTDOWN SUPPLY CURRENT vs INPUT VOLTAGE (Vin) 2 TJ = 25°C I(VIN) - mA 1.5 1 0.5 1 0.
PAGE 10
TPS54140A SLVSB55B – MAY 2012 – REVISED JANUARY 2014 www.ti.com TYPICAL CHARACTERISTICS (continued) PWRGD ON RESISTANCE vs JUNCTION TEMPERATURE PWRGD THRESHOLD vs JUNCTION TEMPERATURE 115 100 VI = 12 V PWRGD Threshold - % of Vref VI = 12 V RDSON - W 80 60 40 20 0 -50 VSENSE Rising 110 VSENSE Falling 105 100 VSENSE Rising 95 VSENSE Falling 90 -25 0 50 25 75 100 125 85 -50 150 -25 0 125 150 Figure 20.
PAGE 11
TPS54140A www.ti.com SLVSB55B – MAY 2012 – REVISED JANUARY 2014 OVERVIEW The TPS54140A device is a 42-V, 1.5-A, step-down (buck) regulator with an integrated high side n-channel MOSFET. To improve performance during line and load transients the device implements a constant frequency, current mode control which reduces output capacitance and simplifies external frequency compensation design.
PAGE 12
TPS54140A SLVSB55B – MAY 2012 – REVISED JANUARY 2014 www.ti.com DETAILED DESCRIPTION Fixed Frequency PWM Control The TPS54140A uses an adjustable fixed frequency, peak current mode control. The output voltage is compared through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives the COMP pin. An internal oscillator initiates the turn on of the high side power switch. The error amplifier output is compared to the high side power switch current.
PAGE 13
TPS54140A www.ti.com SLVSB55B – MAY 2012 – REVISED JANUARY 2014 DETAILED DESCRIPTION (continued) Bootstrap Voltage (BOOT) The TPS54140A has an integrated boot regulator and requires a small ceramic capacitor between the BOOT and PH pin to provide the gate drive voltage for the high side MOSFET. The value of the ceramic capacitor should be 0.1 μF. A ceramic capacitor with an X7R or X5R grade dielectric is recommended because of the stable characteristics over temperature and voltage.
PAGE 14
TPS54140A SLVSB55B – MAY 2012 – REVISED JANUARY 2014 www.ti.com DETAILED DESCRIPTION (continued) Error Amplifier The TPS54140A has a transconductance amplifier for the error amplifier. The error amplifier compares the VSENSE voltage to the lower of the SS/TR pin voltage or the internal 0.8 V voltage reference. The transconductance (gm) of the error amplifier is 97 μA/V during normal operation. During the slow start operation, the transconductance is a fraction of the normal operating gm.
PAGE 15
TPS54140A www.ti.com SLVSB55B – MAY 2012 – REVISED JANUARY 2014 DETAILED DESCRIPTION (continued) Another technique to add input voltage hysteresis is shown in Figure 29. This method may be used, if the resistance values are high from the previous method and a wider voltage hysteresis is needed. The resistor R3 sources additional hysteresis current into the EN pin. TPS54140A VIN R1 Ihys I1 0.9 mA 2.9 mA + R2 EN 1.25 V R3 - VOUT Figure 29.
PAGE 16
TPS54140A SLVSB55B – MAY 2012 – REVISED JANUARY 2014 www.ti.com DETAILED DESCRIPTION (continued) Slow Start/Tracking Pin (SS/TR) The TPS54140A effectively uses the lower voltage of the internal voltage reference or the SS/TR pin voltage as the power-supply's reference voltage and regulates the output accordingly. A capacitor on the SS/TR pin to ground implements a slow start time. The TPS54140A has an internal pull-up current source of 2μA that charges the external slow start capacitor.
PAGE 17
TPS54140A www.ti.com SLVSB55B – MAY 2012 – REVISED JANUARY 2014 DETAILED DESCRIPTION (continued) Sequencing Many of the common power supply sequencing methods can be implemented using the SS/TR, EN and PWRGD pins. The sequential method can be implemented using an open drain output of a power on reset pin of another device. The sequential method is illustrated in Figure 32 using two TPS54140A devices.
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TPS54140A SLVSB55B – MAY 2012 – REVISED JANUARY 2014 www.ti.com DETAILED DESCRIPTION (continued) TPS54140A 3 EN EN1, EN2 4 SS/TR 6 PWRGD VOUT1 VOUT2 TPS54140A 3 EN 4 SS/TR 6 PWRGD Figure 34. Schematic for Ratiometric Start-Up Sequence Figure 35. Ratio-Metric Startup using Coupled SS/TR pins Figure 34 shows a method for ratio-metric start up sequence by connecting the SS/TR pins together. The regulator outputs will ramp up and reach regulation at the same time.
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TPS54140A www.ti.com SLVSB55B – MAY 2012 – REVISED JANUARY 2014 DETAILED DESCRIPTION (continued) TPS54140A EN VOUT 1 SS/TR PWRGD TPS54140A VOUT 2 EN R1 SS/ TR R2 PWRGD R3 R4 Figure 36. Schematic for Ratiometric and Simultaneous Start-Up Sequence Ratio-metric and simultaneous power supply sequencing can be implemented by connecting the resistor network of R1 and R2 shown in Figure 36 to the output of the power supply that needs to be tracked or another voltage reference source.
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TPS54140A SLVSB55B – MAY 2012 – REVISED JANUARY 2014 www.ti.com DETAILED DESCRIPTION (continued) R1 > 2800 ´ VOUT1 - 180 ´ DV (10) EN EN VOUT1 VOUT1 VOUT2 Figure 37. Ratio-metric Startup with Tracking Resistors VOUT2 Figure 38. Ratiometric Startup with Tracking Resistors EN VOUT1 VOUT2 Figure 39.
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TPS54140A www.ti.com SLVSB55B – MAY 2012 – REVISED JANUARY 2014 DETAILED DESCRIPTION (continued) Constant Switching Frequency and Timing Resistor (RT/CLK Pin) The switching frequency of the TPS54140A is adjustable over a wide range from approximately 100 kHz to 2500 kHz by placing a resistor on the RT/CLK pin. The RT/CLK pin voltage is typically 0.5 V and must have a resistor to ground to set the switching frequency.
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TPS54140A SLVSB55B – MAY 2012 – REVISED JANUARY 2014 www.ti.com DETAILED DESCRIPTION (continued) Selecting the Switching Frequency The switching frequency that is selected should be the lower value of the two equations, Equation 12 and Equation 13. Equation 12 is the maximum switching frequency limitation set by the minimum controllable on time. Setting the switching frequency above this value will cause the regulator to skip switching pulses.
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TPS54140A www.ti.com SLVSB55B – MAY 2012 – REVISED JANUARY 2014 DETAILED DESCRIPTION (continued) How to Interface to RT/CLK Pin The RT/CLK pin can be used to synchronize the regulator to an external system clock. To implement the synchronization feature connect a square wave to the RT/CLK pin through the circuit network shown in Figure 43. The square wave amplitude must transition lower than 0.5V and higher than 2.
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TPS54140A SLVSB55B – MAY 2012 – REVISED JANUARY 2014 www.ti.com DETAILED DESCRIPTION (continued) EXT EXT VOUT IL PH PH IL Figure 44. Plot of Synchronizing in ccm Figure 45. Plot of Synchronizing in dcm EXT IL PH Figure 46. Plot of Synchronizing in PSM Power Good (PWRGD Pin) The PWRGD pin is an open drain output. Once the VSENSE pin is between 94% and 107% of the internal voltage reference the PWRGD pin is de-asserted and the pin floats.
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TPS54140A www.ti.com SLVSB55B – MAY 2012 – REVISED JANUARY 2014 DETAILED DESCRIPTION (continued) The PWRGD pin is pulled low when the VSENSE is lower than 92% or greater than 109% of the nominal internal reference voltage. Also, the PWRGD is pulled low, if the UVLO or thermal shutdown are asserted or the EN pin pulled low.
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TPS54140A SLVSB55B – MAY 2012 – REVISED JANUARY 2014 www.ti.com DETAILED DESCRIPTION (continued) Simple Small Signal Model for Peak Current Mode Control Figure 48 describes a simple small signal model that can be used to understand how to design the frequency compensation. The TPS54140A power stage can be approximated to a voltage-controlled current source (duty cycle modulator) supplying current to the output capacitor and load resistor.
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TPS54140A www.ti.com SLVSB55B – MAY 2012 – REVISED JANUARY 2014 DETAILED DESCRIPTION (continued) Small Signal Model for Frequency Compensation The TPS54140A uses a transconductance amplifier for the error amplifier and readily supports three of the commonly-used frequency compensation circuits. Compensation circuits Type 2A, Type 2B, and Type 1 are shown in Figure 49. Type 2 circuits most likely implemented in high bandwidth power-supply designs using low ESR output capacitors.
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TPS54140A SLVSB55B – MAY 2012 – REVISED JANUARY 2014 www.ti.
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TPS54140A www.ti.com SLVSB55B – MAY 2012 – REVISED JANUARY 2014 APPLICATION INFORMATION Design Guide — Step-By-Step Design Procedure This example details the design of a high frequency switching regulator design using ceramic output capacitors. A few parameters must be known in order to start the design process. These parameters are typically determined at the system level. For this example, we will start with the following known parameters: Output Voltage 3.3V Transient Response 0 to 1.
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TPS54140A SLVSB55B – MAY 2012 – REVISED JANUARY 2014 www.ti.com Output Inductor Selection (LO) To calculate the minimum value of the output inductor, use Equation 28. KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. The inductor ripple current will be filtered by the output capacitor.
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TPS54140A www.ti.com SLVSB55B – MAY 2012 – REVISED JANUARY 2014 to see the change in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor must be sized to supply the extra current to the load until the control loop responds to the load change. The output capacitance must be large enough to supply the difference in current for 2 clock cycles while only allowing a tolerable amount of droop in the output voltage.
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TPS54140A SLVSB55B – MAY 2012 – REVISED JANUARY 2014 www.ti.com VOUT(ripple ) RESR = IRIPPLE ICOUT(rms) = (35) ( VOUT ´ VIN(max ) - VOUT ) 12 ´ VIN(max ) ´ LO ´ fSW (36) Catch Diode The TPS54140A requires an external catch diode between the PH pin and GND. The selected diode must have a reverse voltage rating equal to or greater than Vinmax. The peak current rating of the diode must be greater than the maximum inductor current. The diode should also have a low forward voltage.
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TPS54140A www.ti.com SLVSB55B – MAY 2012 – REVISED JANUARY 2014 For this example design, a ceramic capacitor with at least a 20 V voltage rating is required to support the maximum input voltage. Common standard ceramic capacitor voltage ratings include 4 V, 6.3 V, 10 V, 16V, 25 V, 50 V or 100V so a 25 V capacitor should be selected. For this example, two 2.2 μF, 25 V capacitors in parallel have been selected. Table 2 shows a selection of high voltage capacitors.
PAGE 34
TPS54140A SLVSB55B – MAY 2012 – REVISED JANUARY 2014 www.ti.com Bootstrap Capacitor Selection A 0.1-μF ceramic capacitor must be connected between the BOOT and PH pins for proper operation. It is recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have a 10V or higher voltage rating. Under Voltage Lock Out Set Point The Under Voltage Lock Out (UVLO) can be adjusted using an external voltage divider on the EN pin of the TPS54140A.
PAGE 35
TPS54140A www.ti.com SLVSB55B – MAY 2012 – REVISED JANUARY 2014 To compensate the TPS54140A using this method, first calculate the modulator pole and zero using the following equations: IOUT(max ) fP(mod) = 2 ´ p ´ VOUT ´ COUT where • • • IOUT(max) is the maximum output current COUT is the output capacitance VOUT is the nominal output voltage f Z(mod) = (41) 1 2 ´ p ´ RESR ´ COUT (42) For the example design, the modulator pole is located at 1.5 kHz and the ESR zero is located at 338 kHz.
PAGE 36
TPS54140A SLVSB55B – MAY 2012 – REVISED JANUARY 2014 www.ti.com For the example problem, the gain of the modulator at the cross over frequency is 0.542. Next, the compensation components are calculated. A resistor in series with a capacitor is used to create a compensating zero. A capacitor in parallel to these two components forms the compensating pole. However, calculating the values of these components varies depending on if the ESR zero is located above or below the cross over frequency.
PAGE 37
TPS54140A www.ti.com SLVSB55B – MAY 2012 – REVISED JANUARY 2014 VOUT VOUT IL PH VIN IL Figure 54. VIN Power Up Figure 55. Output Ripple CCM VOUT VOUT IL IL PH Figure 56. Output Ripple, DCM PH Figure 57. Output Ripple, PSM VIN VIN IL IL PH PH Figure 58. Input Ripple CCM Figure 59.
PAGE 38
TPS54140A SLVSB55B – MAY 2012 – REVISED JANUARY 2014 www.ti.com 95 VO = 3.3 V, fsw = 1200 kHz VI = 8 V 90 85 VIN Efficiency - % 80 IL VI = 12 V VI = 16 V 75 70 65 PH 60 55 50 0 Figure 60. Input Ripple PSM 0.25 0.50 0.75 1 1.25 IL - Load Current - A 1.5 1.75 2 Figure 61. Efficiency vs Load Current 1.015 60 150 VI = 12 V 1.010 40 100 1.005 Phase - o Gain - dB 50 20 0 Gain 0 -50 Regulation (%) Phase 1.000 0.995 -100 -20 0.
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TPS54140A www.ti.com SLVSB55B – MAY 2012 – REVISED JANUARY 2014 Power Dissipation Estimate The following formulas show how to estimate the device power dissipation under continuous conduction mode (CCM) operation. These equations should not be used if the device is working in discontinuous conduction mode (DCM). The power dissipation of the device includes conduction loss (Pcon), switching loss (Psw), gate drive loss (Pgd) and supply current (Pq).
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TPS54140A SLVSB55B – MAY 2012 – REVISED JANUARY 2014 www.ti.com Layout Layout is a critical portion of good power supply design. There are several signals paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help eliminate these problems, the VIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor with X5R or X7R dielectric.
PAGE 41
TPS54140A www.ti.com SLVSB55B – MAY 2012 – REVISED JANUARY 2014 REVISION HISTORY Changes from Original (May 2012) to Revision A Page • Changed Description text From: "within 93% to 107% of its nominal voltage." To: "within 94% to 107% of its nominal voltage." ................................................................................................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 17-May-2014 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 31-May-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS54140ADGQR MSOPPower PAD DGQ 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TPS54140ADGQR MSOPPower PAD DGQ 10 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 TPS54140ADRCR SON DRC 10 3000 330.0 12.4 3.3 3.3 1.0 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 31-May-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS54140ADGQR MSOP-PowerPAD DGQ 10 2500 364.0 364.0 27.0 TPS54140ADGQR MSOP-PowerPAD DGQ 10 2500 346.0 346.0 35.0 TPS54140ADRCR SON DRC 10 3000 346.0 346.0 35.0 TPS54140ADRCT SON DRC 10 250 203.0 203.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.