TPS54140 www.ti.com SLVS889B – OCTOBER 2008 – REVISED SEPTEMBER 2013 1.5-A, 42V STEP DOWN DC/DC CONVERTER WITH ECO-MODE™ Check for Samples: TPS54140 FEATURES 1 • • • 2 • • • • • • • 3.5V to 42V Input Voltage Range 200-mΩ High-Side MOSFET High Efficiency at Light Loads with a Pulse Skipping Eco-mode™ 116μA Operating Quiescent Current 1.3μA Shutdown Current 100kHz to 2.
TPS54140 SLVS889B – OCTOBER 2008 – REVISED SEPTEMBER 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Table 1.
TPS54140 www.ti.com SLVS889B – OCTOBER 2008 – REVISED SEPTEMBER 2013 PACKAGE DISSIPATION RATINGS (1) (1) PACKAGE THERMAL IMPEDANCE JUNCTION TO AMBIENT MSOP 57 °C/W Test board conditions: A. 3 inches × 3 inches, 2 layers, thickness: 0.062 inch B. 2-ounce copper traces located on the top and bottom of the PCB C. 6 (13 mil diameters) THERMAL VIAS LOCATED UNDER THE DEVICE PACKAGE ELECTRICAL CHARACTERISTICS TJ = –40°C to 150°C, VIN = 3.
TPS54140 SLVS889B – OCTOBER 2008 – REVISED SEPTEMBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) TJ = –40°C to 150°C, VIN = 3.5 to 42V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 2500 kHz 720 kHz 2200 kHz TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN) Switching Frequency Range using RT mode fSW Switching frequency 100 RT = 200 kΩ 450 Switching Frequency Range using CLK mode 581 300 Minimum CLK pulse width 40 RT/CLK high threshold 1.
TPS54140 www.ti.com SLVS889B – OCTOBER 2008 – REVISED SEPTEMBER 2013 DEVICE INFORMATION PIN CONFIGURATION MSOP10 (TOP VIEW) BOOT 1 VIN 2 10 Thermal Pad (11) PH 9 GND 8 COMP EN 3 SS/TR 4 7 VSENSE RT/CLK 5 6 PWRGD PIN FUNCTIONS PIN I/O DESCRIPTION NAME NO. BOOT 1 O A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the minimum required by the device, the output is forced to switch off until the capacitor is refreshed.
TPS54140 SLVS889B – OCTOBER 2008 – REVISED SEPTEMBER 2013 www.ti.
TPS54140 www.ti.com SLVS889B – OCTOBER 2008 – REVISED SEPTEMBER 2013 TYPICAL CHARACTERISTICS VOLTAGE REFERENCE vs JUNCTION TEMPERATURE 0.816 500 VI = 12 V VI = 12 V 375 Vref - Voltage Reference - V RDSON - Static Drain-Source On-State Resistance - mW ON RESISTANCE vs JUNCTION TEMPERATURE BOOT-PH = 3 V 250 BOOT-PH = 6 V 125 0 -50 0.808 0.800 0.792 0.784 -50 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 -25 0 150 Figure 1.
TPS54140 SLVS889B – OCTOBER 2008 – REVISED SEPTEMBER 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) EA TRANSCONDUCTANCE DURING SLOW START vs JUNCTION TEMPERATURE EA TRANSCONDUCTANCE vs JUNCTION TEMPERATURE 150 40 VI = 12 V VI = 12 V 130 110 gm - mA/V gm - mA/V 30 90 20 70 10 -50 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 50 -50 150 -25 0 25 50 75 100 125 150 TJ - Junction Temperature - °C Figure 7. Figure 8.
TPS54140 www.ti.com SLVS889B – OCTOBER 2008 – REVISED SEPTEMBER 2013 TYPICAL CHARACTERISTICS (continued) SS/TR DISCHARGE CURRENT vs JUNCTION TEMPERATURE SWITCHING FREQUENCY vs VSENSE 120 100 VI = 12 V VI = 12 V, TJ = 25°C 80 % of Nominal fsw II(SS/TR) - mA 115 110 60 40 105 20 100 -50 0 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 150 0 SHUTDOWN SUPPLY CURRENT vs INPUT VOLTAGE (Vin) 2 TJ = 25°C I(VIN) - mA 1.5 1 0.5 1 0.
TPS54140 SLVS889B – OCTOBER 2008 – REVISED SEPTEMBER 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) PWRGD ON RESISTANCE vs JUNCTION TEMPERATURE PWRGD THRESHOLD vs JUNCTION TEMPERATURE 115 100 VI = 12 V PWRGD Threshold - % of Vref VI = 12 V RDSON - W 80 60 40 20 0 -50 VSENSE Rising 110 VSENSE Falling 105 100 VSENSE Rising 95 VSENSE Falling 90 -25 0 50 25 75 100 125 85 -50 150 -25 0 125 150 Figure 20.
TPS54140 www.ti.com SLVS889B – OCTOBER 2008 – REVISED SEPTEMBER 2013 OVERVIEW The TPS54140 device is a 42-V, 1.5-A, step-down (buck) regulator with an integrated high side n-channel MOSFET. To improve performance during line and load transients the device implements a constant frequency, current mode control which reduces output capacitance and simplifies external frequency compensation design.
TPS54140 SLVS889B – OCTOBER 2008 – REVISED SEPTEMBER 2013 www.ti.com DETAILED DESCRIPTION Fixed Frequency PWM Control The TPS54140 uses an adjustable fixed frequency, peak current mode control. The output voltage is compared through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives the COMP pin. An internal oscillator initiates the turn on of the high side power switch. The error amplifier output is compared to the high side power switch current.
TPS54140 www.ti.com SLVS889B – OCTOBER 2008 – REVISED SEPTEMBER 2013 DETAILED DESCRIPTION (continued) Bootstrap Voltage (BOOT) The TPS54140 has an integrated boot regulator and requires a small ceramic capacitor between the BOOT and PH pin to provide the gate drive voltage for the high side MOSFET. The value of the ceramic capacitor should be 0.1μF. A ceramic capacitor with an X7R or X5R grade dielectric is recommended because of the stable characteristics over temperature and voltage.
TPS54140 SLVS889B – OCTOBER 2008 – REVISED SEPTEMBER 2013 www.ti.com DETAILED DESCRIPTION (continued) Error Amplifier The TPS54140 has a transconductance amplifier for the error amplifier. The error amplifier compares the VSENSE voltage to the lower of the SS/TR pin voltage or the internal 0.8V voltage reference. The transconductance (gm) of the error amplifier is 97μA/V during normal operation. During the slow start operation, the transconductance is a fraction of the normal operating gm.
TPS54140 www.ti.com SLVS889B – OCTOBER 2008 – REVISED SEPTEMBER 2013 DETAILED DESCRIPTION (continued) Another technique to add input voltage hysteresis is shown in Figure 29. This method may be used, if the resistance values are high from the previous method and a wider voltage hysteresis is needed. The resistor R3 sources additional hysteresis current into the EN pin. TPS54140 VIN R1 Ihys I1 0.9 mA 2.9 mA + R2 EN 1.25 V R3 - VOUT Figure 29.
TPS54140 SLVS889B – OCTOBER 2008 – REVISED SEPTEMBER 2013 www.ti.com DETAILED DESCRIPTION (continued) Slow Start and Tracking Pin (SS/TR) The TPS54140 effectively uses the lower voltage of the internal voltage reference or the SS/TR pin voltage as the power-supply's reference voltage and regulates the output accordingly. A capacitor on the SS/TR pin to ground implements a slow start time. The TPS54140 has an internal pull-up current source of 2 μA that charges the external slow start capacitor.
TPS54140 www.ti.com SLVS889B – OCTOBER 2008 – REVISED SEPTEMBER 2013 DETAILED DESCRIPTION (continued) Sequencing Many of the common power supply sequencing methods can be implemented using the SS/TR, EN and PWRGD pins. The sequential method can be implemented using an open drain output of a power on reset pin of another device. The sequential method is illustrated in Figure 31 using two TPS54140 devices.
TPS54140 SLVS889B – OCTOBER 2008 – REVISED SEPTEMBER 2013 www.ti.com DETAILED DESCRIPTION (continued) Figure 33 shows a method for ratio-metric start up sequence by connecting the SS/TR pins together. The regulator outputs will ramp up and reach regulation at the same time. When calculating the slow start time the pull up current source must be doubled in Equation 6. Figure 34 shows the results of Figure 33. TPS54140 EN VOUT 1 SS/TR PWRGD TPS54140 VOUT 2 EN R1 SS/ TR R2 PWRGD R3 R4 Figure 35.
TPS54140 www.ti.com SLVS889B – OCTOBER 2008 – REVISED SEPTEMBER 2013 DETAILED DESCRIPTION (continued) VREF ´ R1 R2 = VOUT2 + DV - VREF (8) DV = VOUT1 - VOUT2 R1 > 2800 ´ VOUT1 - 180 ´ DV (9) (10) EN EN VOUT1 VOUT1 VOUT2 Figure 36. Ratio-metric Startup with Tracking Resistors VOUT2 Figure 37. Ratiometric Startup with Tracking Resistors EN VOUT1 VOUT2 Figure 38.
TPS54140 SLVS889B – OCTOBER 2008 – REVISED SEPTEMBER 2013 www.ti.com DETAILED DESCRIPTION (continued) Constant Switching Frequency and Timing Resistor (RT/CLK Pin) The switching frequency of the TPS54140 is adjustable over a wide range from approximately 100kHz to 2500kHz by placing a resistor on the RT/CLK pin. The RT/CLK pin voltage is typically 0.5V and must have a resistor to ground to set the switching frequency.
TPS54140 www.ti.com SLVS889B – OCTOBER 2008 – REVISED SEPTEMBER 2013 DETAILED DESCRIPTION (continued) Selecting the Switching Frequency The switching frequency that is selected should be the lower value of the two equations, Equation 12 and Equation 13. Equation 12 is the maximum switching frequency limitation set by the minimum controllable on time. Setting the switching frequency above this value will cause the regulator to skip switching pulses.
TPS54140 SLVS889B – OCTOBER 2008 – REVISED SEPTEMBER 2013 www.ti.com DETAILED DESCRIPTION (continued) How to Interface to RT/CLK Pin The RT/CLK pin can be used to synchronize the regulator to an external system clock. To implement the synchronization feature connect a square wave to the RT/CLK pin through the circuit network shown in Figure 42. The square wave amplitude must transition lower than 0.5V and higher than 2.
TPS54140 www.ti.com SLVS889B – OCTOBER 2008 – REVISED SEPTEMBER 2013 DETAILED DESCRIPTION (continued) EXT EXT VOUT IL PH PH IL Figure 43. Plot of Synchronizing in ccm Figure 44. Plot of Synchronizing in dcm EXT IL PH Figure 45. Plot of Synchronizing in PSM Power Good (PWRGD Pin) The PWRGD pin is an open drain output. Once the VSENSE pin is between 94% and 107% of the internal voltage reference the PWRGD pin is de-asserted and the pin floats.
TPS54140 SLVS889B – OCTOBER 2008 – REVISED SEPTEMBER 2013 www.ti.com DETAILED DESCRIPTION (continued) The PWRGD pin is pulled low when the VSENSE is lower than 92% or greater than 109% of the nominal internal reference voltage. Also, the PWRGD is pulled low, if the UVLO or thermal shutdown are asserted or the EN pin pulled low.
TPS54140 www.ti.com SLVS889B – OCTOBER 2008 – REVISED SEPTEMBER 2013 DETAILED DESCRIPTION (continued) PH VO Power Stage gmps 6 A/V a b RESR R1 RL COMP c 0.8 V R3 CO C2 RO VSENSE COUT gmea 97 mA/V R2 C1 Figure 46. Small Signal Model for Loop Response Simple Small Signal Model for Peak Current Mode Control Figure 47 describes a simple small signal model that can be used to understand how to design the frequency compensation.
TPS54140 SLVS889B – OCTOBER 2008 – REVISED SEPTEMBER 2013 www.ti.com DETAILED DESCRIPTION (continued) VO Adc VC RESR fp RL gmps COUT fz Figure 47.
TPS54140 www.ti.com SLVS889B – OCTOBER 2008 – REVISED SEPTEMBER 2013 DETAILED DESCRIPTION (continued) VO R1 VSENSE gmea Type 2A COMP Type 2B Type 1 Vref R2 RO R3 CO C2 C1 R3 C2 C1 Figure 48. Types of Frequency Compensation Aol A0 P1 Z1 P2 A1 BW Figure 49.
TPS54140 SLVS889B – OCTOBER 2008 – REVISED SEPTEMBER 2013 www.ti.
TPS54140 www.ti.com SLVS889B – OCTOBER 2008 – REVISED SEPTEMBER 2013 APPLICATION INFORMATION Design Guide — Step-By-Step Design Procedure This example details the design of a high frequency switching regulator design using ceramic output capacitors. A few parameters must be known in order to start the design process. These parameters are typically determined at the system level. For this example, we will start with the following known parameters: Output Voltage 3.3V Transient Response 0 to 1.
TPS54140 SLVS889B – OCTOBER 2008 – REVISED SEPTEMBER 2013 www.ti.com Output Inductor Selection (LO) To calculate the minimum value of the output inductor, use Equation 28. KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. The inductor ripple current will be filtered by the output capacitor.
TPS54140 www.ti.com SLVS889B – OCTOBER 2008 – REVISED SEPTEMBER 2013 to see the change in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor must be sized to supply the extra current to the load until the control loop responds to the load change. The output capacitance must be large enough to supply the difference in current for 2 clock cycles while only allowing a tolerable amount of droop in the output voltage.
TPS54140 SLVS889B – OCTOBER 2008 – REVISED SEPTEMBER 2013 www.ti.com VOUT(ripple ) RESR = IRIPPLE ICOUT(rms) = (35) ( VOUT ´ VIN(max ) - VOUT ) 12 ´ VIN(max ) ´ LO ´ fSW (36) Catch Diode The TPS54140 requires an external catch diode between the PH pin and GND. The selected diode must have a reverse voltage rating equal to or greater than Vinmax. The peak current rating of the diode must be greater than the maximum inductor current. The diode should also have a low forward voltage.
TPS54140 www.ti.com SLVS889B – OCTOBER 2008 – REVISED SEPTEMBER 2013 For this example design, a ceramic capacitor with at least a 20V voltage rating is required to support the maximum input voltage. Common standard ceramic capacitor voltage ratings include 4V, 6.3V, 10V, 16V, 25V, 50V or 100V so a 25V capacitor should be selected. For this example, two 2.2μF, 25V capacitors in parallel have been selected. Table 2 shows a selection of high voltage capacitors.
TPS54140 SLVS889B – OCTOBER 2008 – REVISED SEPTEMBER 2013 www.ti.com Bootstrap Capacitor Selection A 0.1-μF ceramic capacitor must be connected between the BOOT and PH pins for proper operation. It is recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have a 10V or higher voltage rating. Under Voltage Lock Out Set Point The Under Voltage Lock Out (UVLO) can be adjusted using an external voltage divider on the EN pin of the TPS54140.
TPS54140 www.ti.com SLVS889B – OCTOBER 2008 – REVISED SEPTEMBER 2013 To compensate the TPS54140 using this method, first calculate the modulator pole and zero using the following equations: IOUT(max ) fP(mod) = 2 ´ p ´ VOUT ´ COUT where • • • IOUT(max) is the maximum output current COUT is the output capacitance VOUT is the nominal output voltage f Z(mod) = (41) 1 2 ´ p ´ RESR ´ COUT (42) For the example design, the modulator pole is located at 1.5 kHz and the ESR zero is located at 338 kHz.
TPS54140 SLVS889B – OCTOBER 2008 – REVISED SEPTEMBER 2013 www.ti.com For the example problem, the gain of the modulator at the cross over frequency is 0.542. Next, the compensation components are calculated. A resistor in series with a capacitor is used to create a compensating zero. A capacitor in parallel to these two components forms the compensating pole. However, calculating the values of these components varies depending on if the ESR zero is located above or below the cross over frequency.
TPS54140 www.ti.com SLVS889B – OCTOBER 2008 – REVISED SEPTEMBER 2013 VOUT VOUT IL PH VIN IL Figure 53. VIN Power Up Figure 54. Output Ripple CCM VOUT VOUT IL IL PH PH Figure 55. Output Ripple, DCM Figure 56. Output Ripple, PSM VIN VIN IL IL PH PH Figure 57. Input Ripple CCM Figure 58.
TPS54140 SLVS889B – OCTOBER 2008 – REVISED SEPTEMBER 2013 www.ti.com 95 VO = 3.3 V, fsw = 1200 kHz VI = 8 V 90 85 VIN Efficiency - % 80 IL VI = 12 V VI = 16 V 75 70 65 PH 60 55 50 0 Figure 59. Input Ripple PSM 0.25 0.50 0.75 1 1.25 IL - Load Current - A 1.5 1.75 2 Figure 60. Efficiency vs Load Current 1.015 60 150 VI = 12 V 1.010 40 100 1.005 Phase - o Gain - dB 50 20 0 Gain 0 -50 Regulation (%) Phase 1.000 0.995 -100 -20 0.
TPS54140 www.ti.com SLVS889B – OCTOBER 2008 – REVISED SEPTEMBER 2013 Power Dissipation Estimate The following formulas show how to estimate the device power dissipation under continuous conduction mode (CCM) operation. These equations should not be used if the device is working in discontinuous conduction mode (DCM). The power dissipation of the device includes conduction loss (Pcon), switching loss (Psw), gate drive loss (Pgd) and supply current (Pq).
TPS54140 SLVS889B – OCTOBER 2008 – REVISED SEPTEMBER 2013 www.ti.com Layout Layout is a critical portion of good power supply design. There are several signals paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help eliminate these problems, the VIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor with X5R or X7R dielectric.
TPS54140 www.ti.com SLVS889B – OCTOBER 2008 – REVISED SEPTEMBER 2013 REVISION HISTORY Changes from Original (October 2008) to Revision A Page • Changed Features Item From: 300kHz to 2.5MHz Switching Frequency To: 100kHz to 2.5MHz Switching Frequency ..... 1 • Changed Description text From: "within 93% to 107% of its nominal voltage." To: "within 94% to 107% of its nominal voltage." ........................................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE MATERIALS INFORMATION www.ti.com 6-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS54140DGQR Package Package Pins Type Drawing MSOPPower PAD DGQ 10 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 5.3 B0 (mm) K0 (mm) P1 (mm) 3.4 1.4 8.0 W Pin1 (mm) Quadrant 12.
PACKAGE MATERIALS INFORMATION www.ti.com 6-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS54140DGQR MSOP-PowerPAD DGQ 10 2500 364.0 364.0 27.
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