TPS54160 www.ti.com SLVS795E – OCTOBER 2008 – REVISED SEPTEMBER 2013 1.5-A, 60-V, STEP-DOWN DC/DC CONVERTER WITH ECO-MODE™ Check for Samples: TPS54160 FEATURES 1 • • • 2 • • • • • • • 3.5-V to 60-V Input Voltage Range 200-mΩ High-Side MOSFET High Efficiency at Light Loads with a Pulse Skipping Eco-mode™ 116-μA Operating Quiescent Current 1.3-μA Shutdown Current 100-kHz to 2.
TPS54160 SLVS795E – OCTOBER 2008 – REVISED SEPTEMBER 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
TPS54160 www.ti.com SLVS795E – OCTOBER 2008 – REVISED SEPTEMBER 2013 THERMAL INFORMATION TPS54160 THERMAL METRIC (1) (2) DGQ (10 PINS) DRC (10 PINS) θJA Junction-to-ambient thermal resistance (standard board) 62.5 40 θJA Junction-to-ambient thermal resistance (custom board) (3) 57 56.5 ψJT Junction-to-top characterization parameter 1.7 0.6 ψJB Junction-to-board characterization parameter 20.1 7.
TPS54160 SLVS795E – OCTOBER 2008 – REVISED SEPTEMBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) TJ = –40°C to 150°C, VIN = 3.5 to 60V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 1.8 2.
TPS54160 www.ti.com SLVS795E – OCTOBER 2008 – REVISED SEPTEMBER 2013 DEVICE INFORMATION PIN CONFIGURATION TM DGQ PowerPAD PACKAGE (Top View) DRC PACKAGE (Top View) BOOT 1 10 PH VIN 2 9 GND BOOT 1 VIN 2 10 Thermal Pad (11) PH 9 GND 8 COMP EN 3 8 COMP EN 3 SS/TR 4 7 VSENSE SS/TR 4 7 VSENSE RT/CLK 5 6 PWRGD RT/CLK 5 6 PWRGD PIN FUNCTIONS PIN I/O DESCRIPTION NAME NO. BOOT 1 O A bootstrap capacitor is required between BOOT and PH.
TPS54160 SLVS795E – OCTOBER 2008 – REVISED SEPTEMBER 2013 www.ti.
TPS54160 www.ti.com SLVS795E – OCTOBER 2008 – REVISED SEPTEMBER 2013 TYPICAL CHARACTERISTICS VOLTAGE REFERENCE vs JUNCTION TEMPERATURE 0.816 500 VI = 12 V VI = 12 V 375 Vref - Voltage Reference - V RDSON - Static Drain-Source On-State Resistance - mW ON RESISTANCE vs JUNCTION TEMPERATURE BOOT-PH = 3 V 250 BOOT-PH = 6 V 125 0 -50 0.808 0.800 0.792 0.784 -50 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 -25 0 150 Figure 1.
TPS54160 SLVS795E – OCTOBER 2008 – REVISED SEPTEMBER 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) EA TRANSCONDUCTANCE DURING SLOW START vs JUNCTION TEMPERATURE EA TRANSCONDUCTANCE vs JUNCTION TEMPERATURE 150 40 VI = 12 V VI = 12 V 130 110 gm - mA/V gm - mA/V 30 90 20 70 10 -50 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 50 -50 150 -25 0 25 50 75 100 125 150 TJ - Junction Temperature - °C Figure 7. Figure 8.
TPS54160 www.ti.com SLVS795E – OCTOBER 2008 – REVISED SEPTEMBER 2013 TYPICAL CHARACTERISTICS (continued) SS/TR DISCHARGE CURRENT vs JUNCTION TEMPERATURE SWITCHING FREQUENCY vs VSENSE 120 100 VI = 12 V VI = 12 V, TJ = 25°C 80 % of Nominal fsw II(SS/TR) - mA 115 110 60 40 105 20 100 -50 0 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 150 0 SHUTDOWN SUPPLY CURRENT vs INPUT VOLTAGE (Vin) 2 TJ = 25°C I(VIN) - mA 1.5 1 0.5 1 0.
TPS54160 SLVS795E – OCTOBER 2008 – REVISED SEPTEMBER 2013 www.ti.
TPS54160 www.ti.com SLVS795E – OCTOBER 2008 – REVISED SEPTEMBER 2013 OVERVIEW The TPS54160 device is a 60-V, 1.5-A, step-down (buck) regulator with an integrated high-side n-channel MOSFET. To improve performance during line and load transients the device implements a constant frequency, current mode control which reduces output capacitance and simplifies external frequency compensation design.
TPS54160 SLVS795E – OCTOBER 2008 – REVISED SEPTEMBER 2013 www.ti.com DETAILED DESCRIPTION Fixed Frequency PWM Control The TPS54160 uses an adjustable fixed frequency, peak current mode control. The output voltage is compared through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives the COMP pin. An internal oscillator initiates the turn on of the high-side power switch. The error amplifier output is compared to the high-side power switch current.
TPS54160 www.ti.com SLVS795E – OCTOBER 2008 – REVISED SEPTEMBER 2013 DETAILED DESCRIPTION (continued) Low Dropout Operation and Bootstrap Voltage (BOOT) The TPS54160 has an integrated boot regulator, and requires a small ceramic capacitor between the BOOT and PH pins to provide the gate drive voltage for the high-side MOSFET. The BOOT capacitor is refreshed when the high-side MOSFET is off and the low-side diode conducts. The value of this ceramic capacitor should be 0.1μF.
TPS54160 SLVS795E – OCTOBER 2008 – REVISED SEPTEMBER 2013 www.ti.com DETAILED DESCRIPTION (continued) Error Amplifier The TPS54160 has a transconductance amplifier for the error amplifier. The error amplifier compares the VSENSE voltage to the lower of the SS/TR pin voltage or the internal 0.8-V voltage reference. The transconductance (gM) of the error amplifier is 97μA/V during normal operation. During the slow start operation, the transconductance is a fraction of the normal operating transconductance.
TPS54160 www.ti.com SLVS795E – OCTOBER 2008 – REVISED SEPTEMBER 2013 DETAILED DESCRIPTION (continued) Another technique to add input voltage hysteresis is shown in Figure 29. This method may be used, if the resistance values are high from the previous method and a wider voltage hysteresis is needed. The resistor R3 sources additional hysteresis current into the EN pin. TPS54160 VIN R1 Ihys I1 0.9 mA 2.9 mA + R2 EN 1.25 V R3 - VOUT Figure 29.
TPS54160 SLVS795E – OCTOBER 2008 – REVISED SEPTEMBER 2013 www.ti.com DETAILED DESCRIPTION (continued) Slow Start and Tracking Pin (SS/TR) The TPS54160 effectively uses the lower voltage of the internal voltage reference or the SS/TR pin voltage as the power-supply's reference voltage and regulates the output accordingly. A capacitor on the SS/TR pin to ground implements a slow start time. The TPS54160 has an internal pull-up current source of 2μA that charges the external slow start capacitor.
TPS54160 www.ti.com SLVS795E – OCTOBER 2008 – REVISED SEPTEMBER 2013 DETAILED DESCRIPTION (continued) Sequencing Many of the common power supply sequencing methods can be implemented using the SS/TR, EN and PWRGD pins. The sequential method can be implemented using an open drain output of a power on reset pin of another device. The sequential method is illustrated in Figure 32 using two TPS54160 devices.
TPS54160 SLVS795E – OCTOBER 2008 – REVISED SEPTEMBER 2013 www.ti.com DETAILED DESCRIPTION (continued) Figure 34 shows a method for ratio-metric start up sequence by connecting the SS/TR pins together. The regulator outputs ramp up to reach regulation at the same time. When calculating the slow start time the pull up current source must be doubled in Equation 6. Figure 35 shows the results of Figure 34. TPS54160 EN VOUT 1 SS/TR PWRGD TPS54160 VOUT 2 EN R1 SS/ TR R2 PWRGD R3 R4 Figure 36.
TPS54160 www.ti.com SLVS795E – OCTOBER 2008 – REVISED SEPTEMBER 2013 DETAILED DESCRIPTION (continued) VREF ´ R1 R2 = VOUT2 + DV - VREF (8) DV = VOUT1 - VOUT2 R1 > 2800 ´ VOUT1 - 180 ´ DV (9) (10) EN EN VOUT1 VOUT1 VOUT2 Figure 37. Ratiometric Startup with VOUT2 Leading VOUT1 VOUT2 Figure 38. Ratiometric Startup with VOUT1 Leading VOUT2 EN VOUT1 VOUT2 Figure 39.
TPS54160 SLVS795E – OCTOBER 2008 – REVISED SEPTEMBER 2013 www.ti.com DETAILED DESCRIPTION (continued) Constant Switching Frequency and Timing Resistor (RT/CLK Pin) The switching frequency of the TPS54160 is adjustable over a wide range from approximately 100kHz to 2500kHz by placing a resistor on the RT/CLK pin. The RT/CLK pin voltage is typically 0.5V and must have a resistor to ground to set the switching frequency.
TPS54160 www.ti.com SLVS795E – OCTOBER 2008 – REVISED SEPTEMBER 2013 DETAILED DESCRIPTION (continued) Selecting the Switching Frequency The switching frequency that is selected should be the lower value of the two equations, Equation 12 and Equation 13. Equation 12 is the maximum switching frequency limitation set by the minimum controllable on time. Setting the switching frequency above this value causes the regulator to skip switching pulses.
TPS54160 SLVS795E – OCTOBER 2008 – REVISED SEPTEMBER 2013 www.ti.com DETAILED DESCRIPTION (continued) How to Interface to RT/CLK Pin The RT/CLK pin can be used to synchronize the regulator to an external system clock. To implement the synchronization feature connect a square wave to the RT/CLK pin through the circuit network shown in Figure 43. The square wave amplitude must transition lower than 0.5V and higher than 2.
TPS54160 www.ti.com SLVS795E – OCTOBER 2008 – REVISED SEPTEMBER 2013 DETAILED DESCRIPTION (continued) EXT EXT VOUT IL PH PH IL Figure 44. Plot of Synchronizing in ccm Figure 45. Plot of Synchronizing in dcm EXT IL PH Figure 46. Plot of Synchronizing in PSM Power Good (PWRGD Pin) The PWRGD pin is an open drain output. Once the VSENSE pin is between 94% and 107% of the internal voltage reference the PWRGD pin is de-asserted and the pin floats.
TPS54160 SLVS795E – OCTOBER 2008 – REVISED SEPTEMBER 2013 www.ti.com DETAILED DESCRIPTION (continued) Overvoltage Transient Protection The TPS54160 incorporates an overvoltage transient protection (OVTP) circuit to minimize voltage overshoot when recovering from output fault conditions or strong unload transients on power supply designs with low value output capacitance.
TPS54160 www.ti.com SLVS795E – OCTOBER 2008 – REVISED SEPTEMBER 2013 DETAILED DESCRIPTION (continued) Simple Small Signal Model for Peak Current Mode Control Figure 48 describes a simple small signal model that can be used to understand how to design the frequency compensation. The TPS54160 power stage can be approximated to a voltage-controlled current source (duty cycle modulator) supplying current to the output capacitor and load resistor.
TPS54160 SLVS795E – OCTOBER 2008 – REVISED SEPTEMBER 2013 www.ti.com DETAILED DESCRIPTION (continued) Equation 18 through Equation 27 are provided as a reference for those who prefer to compensate using the preferred methods. Those who prefer to use prescribed method use the method outlined in the application section or use switched information. VO R1 VSENSE gmea Type 2A COMP Type 2B Type 1 Vref R2 RO R3 CO C2 C1 R3 C2 C1 Figure 49.
TPS54160 www.ti.
TPS54160 SLVS795E – OCTOBER 2008 – REVISED SEPTEMBER 2013 www.ti.com APPLICATION INFORMATION Design Guide — Step-By-Step Design Procedure This example details the design of a high frequency switching regulator design using ceramic output capacitors. A few parameters must be known in order to start the design process. These parameters are typically determined at the system level. For this example, we will start with the following known parameters: Output Voltage 3.3 V Transient Response 0 to 1.
TPS54160 www.ti.com SLVS795E – OCTOBER 2008 – REVISED SEPTEMBER 2013 Output Inductor Selection (LO) To calculate the minimum value of the output inductor, use Equation 28. KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. The inductor ripple current will be filtered by the output capacitor.
TPS54160 SLVS795E – OCTOBER 2008 – REVISED SEPTEMBER 2013 www.ti.com to see the change in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor must be sized to supply the extra current to the load until the control loop responds to the load change. The output capacitance must be large enough to supply the difference in current for twoclock cycles while only allowing a tolerable amount of droop in the output voltage.
TPS54160 www.ti.com SLVS795E – OCTOBER 2008 – REVISED SEPTEMBER 2013 VOUT(ripple ) RESR = IRIPPLE ICOUT(rms) = (35) ( VOUT ´ VIN(max ) - VOUT ) 12 ´ VIN(max ) ´ LO ´ fSW (36) Catch Diode The TPS54160 requires an external catch diode between the PH pin and GND. The selected diode must have a reverse voltage rating equal to or greater than Vinmax. The peak current rating of the diode must be greater than the maximum inductor current. The diode should also have a low forward voltage.
TPS54160 SLVS795E – OCTOBER 2008 – REVISED SEPTEMBER 2013 www.ti.com For this example design, a ceramic capacitor with at least a 20 V voltage rating is required to support the maximum input voltage. Common standard ceramic capacitor voltage ratings include 4 V, 6.3 V, 10 V, 16 V, 25 V, 50 V or 100 V, so a 25 V capacitor should be selected. For this example, two 2.2 μF, 25 V capacitors in parallel have been selected. Table 2 shows a selection of high voltage capacitors.
TPS54160 www.ti.com SLVS795E – OCTOBER 2008 – REVISED SEPTEMBER 2013 Once the slow start time is known, the slow start capacitor value can be calculated using Equation 6. For the example circuit, the slow start time is not too critical since the output capacitor value is 47μF which does not require much current to charge to 3.3V. The example circuit has the slow start time set to an arbitrary value of 1ms which requires a 3.3 nF capacitor. ´ VOUT ´ 0.
TPS54160 SLVS795E – OCTOBER 2008 – REVISED SEPTEMBER 2013 www.ti.com To compensate the TPS54160 using this method, first calculate the modulator pole and zero using the following equations: fP(mod) = IOUT(max ) 2 ´ p ´ VOUT ´ COUT where • • • IOUT(max) is the maximum output current COUT is the output capacitance VOUT is the nominal output voltage f Z(mod) = (41) 1 2 ´ p ´ RESR ´ COUT (42) For the example design, the modulator pole is located at 1.5 kHz and the ESR zero is located at 338 kHz.
TPS54160 www.ti.com SLVS795E – OCTOBER 2008 – REVISED SEPTEMBER 2013 For the example problem, the gain of the modulator at the crossover frequency is 0.542. Next, the compensation components are calculated. A resistor in series with a capacitor is used to create a compensating zero. A capacitor in parallel to these two components forms the compensating pole. However, calculating the values of these components varies depending on if the ESR zero is located above or below the crossover frequency.
TPS54160 SLVS795E – OCTOBER 2008 – REVISED SEPTEMBER 2013 www.ti.com APPLICATION CURVES VIN VO VOUT EN IO IL Figure 52. Load Transmit Figure 53. Startup With EN VOUT VOUT IL PH VIN IL Figure 54. VIN Power Up Figure 55. Output Ripple CCM VOUT VOUT IL IL PH PH Figure 56. Output Ripple, DCM 36 Figure 57.
TPS54160 www.ti.com SLVS795E – OCTOBER 2008 – REVISED SEPTEMBER 2013 VIN VIN IL IL PH PH Figure 58. Input Ripple CCM Figure 59. Input Ripple DCM 95 VO = 3.3 V, fsw = 1200 kHz VI = 8 V 90 85 VIN Efficiency - % 80 IL VI = 12 V 75 VI = 16 V 70 65 PH 60 55 50 0 Figure 60. Input Ripple PSM 0.25 0.50 0.75 1 1.25 IL - Load Current - A 1.5 1.75 2 Figure 61. Efficiency vs Load Current 1.015 60 150 VI = 12 V 1.010 40 100 1.
TPS54160 SLVS795E – OCTOBER 2008 – REVISED SEPTEMBER 2013 www.ti.com 1.015 IO = 0.5 A 1.010 Regulation (%) 1.005 1.000 0.995 0.990 0.985 5 10 15 20 VI - Input Voltage - V Figure 64.
TPS54160 www.ti.com SLVS795E – OCTOBER 2008 – REVISED SEPTEMBER 2013 Power Dissipation Estimate The following formulas show how to estimate the device power dissipation under continuous conduction mode (CCM) operation. These equations should not be used if the device is working in discontinuous conduction mode (DCM). The power dissipation of the device includes conduction loss (Pcon), switching loss (Psw), gate drive loss (Pgd) and supply current (Pq).
TPS54160 SLVS795E – OCTOBER 2008 – REVISED SEPTEMBER 2013 www.ti.com Layout Layout is a critical portion of good power supply design. There are several signals paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help eliminate these problems, the VIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor with X5R or X7R dielectric.
TPS54160 www.ti.com SLVS795E – OCTOBER 2008 – REVISED SEPTEMBER 2013 Figure 66.
TPS54160 SLVS795E – OCTOBER 2008 – REVISED SEPTEMBER 2013 www.ti.com REVISION HISTORY Changes from Revision B (October 2009) to Revision C Page • Added Note 2 ........................................................................................................................................................................ 2 • Changed Updated characterization data ............................................................................................................................
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PACKAGE MATERIALS INFORMATION www.ti.com 5-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS54160DGQR Package Package Pins Type Drawing MSOPPower PAD DGQ 10 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 5.3 B0 (mm) K0 (mm) P1 (mm) 3.4 1.4 8.0 W Pin1 (mm) Quadrant 12.
PACKAGE MATERIALS INFORMATION www.ti.com 5-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS54160DGQR MSOP-PowerPAD DGQ 10 2500 364.0 364.0 27.
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