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FEATURES

APPLICATIONS

DESCRIPTION/ORDERING INFORMATION

TPS5420-EP

SLVS717 – DECEMBER 2006

2-A WIDE-INPUT-RANGE STEP-DOWN SWIFT™ CONVERTER

• Fixed 500-kHz Switching Frequency for Small

Filter Size

• Controlled Baseline

• Improved Line Regulation and Transient

– One Assembly/Test Site, One Fabrication

Response by Input Voltage Feed Forward

Site

• System Protected by Overcurrent Limiting and

• Enhanced Diminishing Manufacturing Sources

Thermal Shutdown

(DMS) Support

• -55 ° C to 125 ° C Operating Junction

• Enhanced Product-Change Notification

Temperature Range

• Qualification Pedigree

(1)

• Available in Small 8-Pin SOIC Package

• Wide Input Voltage Range: 5.5 V to 35 V

• For SWIFT™ Documentation, Application

• Up to 2-A Continuous (3-A Peak) Output

Reports, and Design Software, See the TI

Current

Website at www.ti.com/swift

• High Efficiency up to 95% Enabled by 110-m Ω

Integrated MOSFET Switch

• Wide Output Voltage Range: Adjustable Down

• Consumer: Set-Top Boxes, DVDs, LCD

to 1.22 V with 1.5% Initial Accuracy

Displays

• Internal Compensation Minimizes External

• Industrial and Car Audio Power Supplies

Parts Count

• Battery Chargers, High-Power LED Supplies

(1) Component qualification in accordance with JEDEC and

• 12-V/24-V Distributed Power Systems

industry standards to ensure reliable operation over an

extended temperature range. This includes, but is not limited

to, Highly Accelerated Stress Test (HAST) or biased 85/85,

temperature cycle, autoclave or unbiased HAST,

electromigration, bond intermetallic life, and mold compound

life. Such qualification testing should not be viewed as

justifying use of this component beyond specified

performance and environmental limits.

As a member of the SWIFT™ family of dc/dc regulators, the TPS5420 is a high-output-current PWM converter

that integrates a low-resistance high-side N-channel MOSFET. Included on the substrate with the listed features

is a high-performance voltage error amplifier that provides tight voltage regulation accuracy under transient

conditions, an undervoltage-lockout circuit to prevent start-up until the input voltage reaches 5.5 V, an internally

set slow-start circuit to limit inrush currents, and a voltage feed-forward circuit to improve the transient response.

Using the ENA pin, shutdown supply current is reduced to 18 µ A, typically. Other features include an active high

enable, overcurrent protection, and thermal shutdown. To reduce design complexity and external component

count, the TPS5420 feedback loop is internally compensated.

The TPS5420 device is available in an easy to use 8-pin SOIC package. TI provides evaluation modules and the

SWIFT Designer Software tool to aid in quickly achieving high-performance power-supply designs to meet

aggressive equipment development cycles.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SWIFT is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (23 pages)

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TPS5420-EP www.ti.com SLVS717 – DECEMBER 2006 2-A WIDE-INPUT-RANGE STEP-DOWN SWIFT™ CONVERTER FEATURES • • • • • • • • • (1) Controlled Baseline – One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree (1) Wide Input Voltage Range: 5.
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TPS5420-EP www.ti.com SLVS717 – DECEMBER 2006 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION TJ INPUT VOLTAGE –55°C to 125°C (1) (2) PACKAGE (1) OUTPUT VOLTAGE 5.5 V to 35 V Adjustable to 1.
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TPS5420-EP www.ti.com SLVS717 – DECEMBER 2006 Dissipation Ratings (1) (2) THERMAL IMPEDANCE JUNCTION-TO-AMBIENT PACKAGE 8-pin D (1) (2) (3) (3) 75°C/W Maximum power dissipation may be limited by overcurrent protection. Power rating at a specific ambient temperature TA should be determined with a junction temperature of 125°C. This is the point where distortion starts to substantially increase.
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TPS5420-EP www.ti.com SLVS717 – DECEMBER 2006 PIN ASSIGNMENTS D PACKAGE (TOP VIEW) BOOT 1 8 PH NC 2 7 VIN NC 3 6 GND VSENSE 4 5 ENA TERMINAL FUNCTIONS TERMINAL NAME NO. BOOT 1 NC 4 2, 3 DESCRIPTION Boost capacitor for the high-side FET gate driver. Connect 0.01-µF low-ESR capacitor from BOOT pin to PH pin. Not connected internally VSENSE 4 Feedback voltage for the regulator. Connect to output voltage divider. ENA 5 On/off control. Below 0.5 V, the device stops switching.
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TPS5420-EP www.ti.com SLVS717 – DECEMBER 2006 TYPICAL CHARACTERISTICS OSCILLATOR FREQUENCY vs JUNCTION TEMPERATURE 3.5 f − Oscillator Frequency − kHz 520 510 500 490 480 470 460 -50 180 VI = 12 V 170 Minimum Controllable On Time − ns IQ − Operating Quiescent Current − mA 530 3.25 3 2.75 2.5 -25 0 50 25 75 100 -50 125 -25 0 50 25 75 100 160 150 140 130 120 -50 125 -25 o TJ − Junction Temperature − oC TJ − Junction Temperature − C 0 25 50 75 100 Figure 2.
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TPS5420-EP www.ti.com SLVS717 – DECEMBER 2006 APPLICATION INFORMATION FUNCTIONAL BLOCK DIAGRAM VIN VIN 1.
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TPS5420-EP www.ti.com SLVS717 – DECEMBER 2006 APPLICATION INFORMATION (continued) Undervoltage Lockout (UVLO) The TPS5420 incorporates an undervoltage lockout circuit to keep the device disabled when VIN (the input voltage) is below the UVLO start voltage threshold. During power up, internal circuits are held inactive until VIN exceeds the UVLO start threshold voltage. Once the UVLO start threshold voltage is reached, device start-up begins.
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TPS5420-EP www.ti.com SLVS717 – DECEMBER 2006 APPLICATION INFORMATION (continued) If the sensed current continues increasing, even with the cycle-by-cycle current limiting that may happen during short circuit or under other circumstances, the hiccup-mode overcurrent protection is triggered instead of the cycle-by-cycle current limiting. During the hiccup-mode overcurrent protection, the voltage reference is grounded and the high-side MOSFET is turned off for the hiccup time.
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TPS5420-EP www.ti.com SLVS717 – DECEMBER 2006 APPLICATION INFORMATION (continued) PH BOOT CAPACITOR OUTPUT INDUCTOR RESISTOR DIVIDER VOUT BOOT PH NC VIN NC GND VSENSE ENA OUTPUT FILTER CAPACITOR Route feedback trace under the output filter capacitor or on the other layer. CATCH DIODE INPUT INPUT BULK BYPASS CAPACITOR FILTER Vin TOPSIDE GROUND AREA VIA to Ground Plane Signal VIA Figure 9.
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TPS5420-EP www.ti.com SLVS717 – DECEMBER 2006 0.050 APPLICATION INFORMATION (continued) 0.026 0.220 0.080 All dimensions in inches Figure 10. TPS5420 Land Pattern Application Circuits Figure 11 shows the schematic for a typical TPS5420 application. The TPS5420 can provide up to 2-A output current at a nominal output voltage of 5 V. U1 TPS5420D 10 V - 35 V 7 VIN ENA C1 4.7 mF C4 4.7 mF VIN BOOT 5 ENA 2 NC 1 C2 0.
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TPS5420-EP www.ti.com SLVS717 – DECEMBER 2006 APPLICATION INFORMATION (continued) Design Procedure The following design procedure can be used to select component values for the TPS5420. Alternately, the SWIFT Designer Software may be used to generate a complete design. The SWIFT Designer Software uses an iterative design procedure and accesses a comprehensive database of components when generating a design. This section presents a simplified discussion of the design process.
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TPS5420-EP www.ti.com SLVS717 – DECEMBER 2006 The maximum RMS ripple current also needs to be checked. For worst-case conditions, this is approximated by Equation 3: I OUT(MAX) I + CIN 2 (3) In this example, the calculated input ripple voltage is 118 mV and the RMS ripple current is 1.0 A. The maximum voltage across the input capacitors would be VIN max plus delta VIN/2.
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TPS5420-EP www.ti.com SLVS717 – DECEMBER 2006 Capacitor Selection The important design factors for the output capacitor are dc voltage rating, ripple current rating, and equivalent series resistance (ESR). The dc voltage and ripple current ratings cannot be exceeded. The ESR is important because, along with the inductor ripple current, it determines the amount of output ripple voltage. The actual value of the output capacitor is not critical, but some practical limits do exist.
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TPS5420-EP www.ti.com SLVS717 – DECEMBER 2006 For this design example, a single 100-µF output capacitor is chosen for C3. The calculated RMS ripple current is 143 mA, and the maximum ESR required is 88 mΩ. A capacitor that meets these requirements is an AVX TPSD107M010R0080, rated at 10 V, with a maximum ESR of 80 mΩ and a ripple current rating of 1.369 A. This capacitor results in a peak-to-peak output ripple of 26 mV using Equation 10. An additional small 0.
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TPS5420-EP www.ti.com SLVS717 – DECEMBER 2006 ADVANCED INFORMATION Output Voltage Limitations Due to the internal design of the TPS5420, there are both upper and lower output voltage limits for any given input voltage. The upper limit of the output voltage set point is constrained by the maximum duty cycle of 87% and is given by: V OUTMAX + 0.87 ƪǒVINMIN * I OMAX Ǔ ƫ ǒ 0.
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TPS5420-EP www.ti.com SLVS717 – DECEMBER 2006 ADVANCED INFORMATION (continued) Thermal Calculations The following formulas show how to estimate the device power dissipation under continuous conduction mode operations. They should not be used if the device is working at light loads in the discontinuous conduction mode. Conduction loss: Pcon = IOUT2× rDS(on)× VOUT/VIN Switching loss: Psw = VIN× IOUT× 0.01 Quiescent current loss: Pq = VIN× 0.
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TPS5420-EP www.ti.com SLVS717 – DECEMBER 2006 PERFORMANCE GRAPHS The performance graphs in Figure 13 through Figure 19 are applicable to the circuit in Figure 11. TA = 25°C (unless otherwise specified). 100 VI = 10.8 V 0.3 0.2 0.2 VI = 12 V IO = 2 A Output Regulation - % VI = 15 V 90 85 VI = 18 V VI = 19.8 V 80 Output Regulation - % 95 Efficiency - % 0.3 0.1 0 -0.1 -0.2 0 0.5 1 1.5 2 IO - Output Current - A 2.5 3 IO = 0 A 0 -0.1 IO = 1 A -0.2 -0.3 75 0.1 -0.3 0 0.5 1 1.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS5420MDREP Package Package Pins Type Drawing SOIC D 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 6.4 B0 (mm) K0 (mm) P1 (mm) 5.2 2.1 8.0 W Pin1 (mm) Quadrant 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS5420MDREP SOIC D 8 2500 367.0 367.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.