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V -50mA/div

OUT

I -1 A/div

OUT

100 s/divm

TPS54226

www.ti.com

SLVSA14E –OCTOBER 2009–REVISED JULY 2011

4.5V to 18V Input, 2-A Synchronous Step-Down SWIFT

Converter with Eco-Mode™

Check for Samples: TPS54226

FEATURES

APPLICATIONS

• D-CAP2™ Mode Enables Fast Transient

• Wide Range of Applications for Low Voltage

Response System

• Low Output Ripple and Allows Ceramic Output – Digital TV Power Supply

Capacitor

– High Definition Blu-ray Disc™ Players

• Wide V

Input Voltage Range: 4.5 V to 18 V

– Networking Home Terminal

• Wide V

Input Voltage Range: 2 V to 18 V

– Digital Set Top Box (STB)

• Output Voltage Range: 0.76 V to 5.5 V

DESCRIPTION

• Highly Efficient Integrated FET’s Optimized

The TPS54226 is a adaptive on-time D-CAP2™

for Lower Duty Cycle Applications

mode synchronous buck converter. TheTPS54226

– 160 mΩ (High Side) and 110 mΩ (Low Side)

enables system designers to complete the suite of

• High Efficiency, less than 10 μA at shutdown

various end equipment’s power bus regulators with a

• Auto-Skip Eco-Mode™ for High Efficiency at

cost effective, low component count, low standby

Light Load

current solution. The main control loop for the

TPS54226 uses the D-CAP2™ mode control which

• High Initial Bandgap Reference Accuracy

provides a fast transient response with no external

• Adjustable Soft Start

compensation components. The adoptive on-time

• Pre-Biased Soft Start

control supports seamless operation between PWM

mode at heavy load condition and reduced frequency

• 700-kHz Switching Frequency (f

)

Eco-Mode™ operation at light load for high efficiency.

• Cycle By Cycle Over Current Limit

The TPS54226 also has a proprietary circuit that

• Power Good Output

enables the device to adopt to both low equivalent

series resistance (ESR) output capacitors, such as

• Auto-Skip Mode

POSCAP or SP-CAP, and ultra-low ESR ceramic

capacitors. The device operates from 4.5-V to 18-V

VCC input, and from 2-V to 18-V VIN input power

supply voltage. The output voltage can be

programmed between 0.76 V and 5.5 V. The device

also features an adjustable slow start time and a

power good function. The TPS54226 is available in

the 14 pin HTSSOP or 16 pin QFN package, and

designed to operate from –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2D-CAP2, Eco-Mode, PowerPAD are trademarks of Texas Instruments.

3Blu-ray Disc is a trademark of Blu-ray Disc Association.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (30 pages)

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TPS54226 SLVSA14E – OCTOBER 2009 – REVISED JULY 2011 www.ti.com TM 4.5V to 18V Input, 2-A Synchronous Step-Down SWIFT Converter with Eco-Mode™ Check for Samples: TPS54226 FEATURES APPLICATIONS • • 1 23 • • • • • • • • • • • • • • D-CAP2™ Mode Enables Fast Transient Response Low Output Ripple and Allows Ceramic Output Capacitor Wide VCC Input Voltage Range: 4.5 V to 18 V Wide VIN Input Voltage Range: 2 V to 18 V Output Voltage Range: 0.76 V to 5.
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TPS54226 SLVSA14E – OCTOBER 2009 – REVISED JULY 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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TPS54226 SLVSA14E – OCTOBER 2009 – REVISED JULY 2011 www.ti.com RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply input voltage range 4.5 18 V VIN Power input voltage range 2 18 V VBST –0.1 24 VBST (vs SW1, SW2) –0.1 5.7 SS, PG –0.1 5.7 EN –0.1 18 VO, VFB –0.1 5.5 SW1, SW2 –1.8 18 VI Input voltage range –3 18 PGND1, PGND2 –0.1 0.
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TPS54226 SLVSA14E – OCTOBER 2009 – REVISED JULY 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range, VCC,VIN = 12V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT THERMAL SHUTDOWN TSDN Shutdown temperature Thermal shutdown threshold Hysteresis (2) 150 (2) °C 25 ON-TIME TIMER CONTROL TON On time VIN = 12 V, VO = 1.05 V 145 TOFF(MIN) Minimum off time TA = 25°C, VFB = 0.7 V 260 310 ns 2.
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TPS54226 SLVSA14E – OCTOBER 2009 – REVISED JULY 2011 www.ti.com VFB VREG5 VO VCC VIN2 VIN1 RGT PACKAGE (TOP VIEW) 16 15 14 13 1 2 12 VBST 11 SW3 EXPOSED THERMAL PAD SW2 GND 4 9 SW1 PG 5 6 7 8 PGND2 10 PGND1 3 EN SS PIN FUNCTIONS PIN NAME DESCRIPTION PWP 14 RGT 16 VO 1 16 Connect to output of converter. This pin is used for On-Time Adjustment. VFB 2 1 Converter feedback input. Connect with feedback resistor divider. VREG5 3 2 5.5 V power supply output.
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TPS54226 SLVSA14E – OCTOBER 2009 – REVISED JULY 2011 www.ti.com FUNCTIONAL BLOCK DIAGRAM -30% UV 14 VO VIN VIN OV 1 VCC 13 +20% VREG5 12 Control logic VBST Ref SS 1 shot SW VFB SGND 10 XCON VREG5 VREG5 Ceramic Capacitor 3 1mF VO 11 2 SS 9 4 8 SW Softstart ZC SS PGND 5 PGND PGND GND SW OCP SGND PG Ref 6 PGND VCC -10% UV VREG5 EN 7 A. EN Logic OV UVLO UVLO Protection Logic TSD REF Ref Block diagram shown is for PWP 14 pin package.
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TPS54226 SLVSA14E – OCTOBER 2009 – REVISED JULY 2011 www.ti.com shot timer expires. This one shot is set by the converter input voltage, VIN, and the output voltage, VO, to maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the reference voltage.
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TPS54226 SLVSA14E – OCTOBER 2009 – REVISED JULY 2011 www.ti.com Current Protection The output over-current protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit. The switch current is monitored by measuring the low-side FET switch voltage between the SW pin and GND. This voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature compensated.
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TPS54226 SLVSA14E – OCTOBER 2009 – REVISED JULY 2011 www.ti.com TYPICAL CHARACTERISTICS 8 1200 IVCCSDN - Shutdown Current - mA ICC - Supply Current - mA 1000 800 600 400 200 0 -50 0 50 100 TJ - Junction Temperature -° C 6 4 2 0 -50 150 Figure 1. VCC CURRENT vs JUNCTION TEMPERATURE 0 50 100 TJ - Junction Temperature -° C Figure 2. VCC SHUTDOWN CURRENT vs JUNCTION TEMPERATURE 100 1.1 80 VI = 18 V VO - Output Voltage - V 1.075 EN Input Current - mA 150 60 40 VI = 12 V 1.
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TPS54226 SLVSA14E – OCTOBER 2009 – REVISED JULY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) 1.1 VO - Output Voltage - V VOUT - 50 mV/div IO = 10 mA 1.075 1.05 IO = 1 A IOUT - 1 A/div 1.025 100 ms/div 1 0 5 10 15 VI - Input Voltage - V 20 Figure 5. 1.05-V OUTPUT VOLTAGE vs INPUT VOLTAGE Figure 6. 1.05 V 50 mA TO 2A LOAD TRANSIENT RESPONSE 100 VO = 3.3 V EN - 10 V/div 90 VO = 1.8 V VOUT - 0.5 V/div Efficiency - % 80 VO = 2.5 V 70 60 PG - 5 V/div 50 400 ms/div 40 Figure 7.
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TPS54226 SLVSA14E – OCTOBER 2009 – REVISED JULY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) 100 900 VO = 2.5 V Efficiency - % 60 fsw - Switching Frequency - kHz VO = 3.3 V 80 VO = 1.8 V 40 20 0 0.001 0.01 IO - Output Current - A 0.1 Figure 9. LIGHT LOAD EFFICIENCY vs OUTPUT CURRENT 800 VO = 1.8 V 700 600 VO = 3.3 V 500 0 5 10 15 VI - Input Voltage - V 20 Figure 10. SWITCHING FREQUENCY vs INPUT VOLTAGE (IO=1 A) 800 VO = 1.
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TPS54226 SLVSA14E – OCTOBER 2009 – REVISED JULY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) VI - 50 mV/div SW - 5 V/div Figure 13.
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TPS54226 SLVSA14E – OCTOBER 2009 – REVISED JULY 2011 www.ti.com DESIGN GUIDE Step By Step Design Procedure To • • • • • begin the design process, the following application parameters must be known: Input voltage range Output voltage Output current Output voltage ripple Input voltage ripple Figure 14 shows the schematic diagram for this design example. Figure 14. Schematic Diagram Output Voltage Resistors Selection The output voltage is set with a resistor divider from the output node to the VFB pin.
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TPS54226 SLVSA14E – OCTOBER 2009 – REVISED JULY 2011 www.ti.com Output Filter Selection The output filter used with the TPS54226 is an LC circuit. This LC filter has double pole at: FP = 1 2p LOUT ´ COUT (5) At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal gain of the TPS54226. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls off at a -40 dB per decade rate and the phase drops rapidly.
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TPS54226 SLVSA14E – OCTOBER 2009 – REVISED JULY 2011 www.ti.com Input Capacitor Selection The TPS54226 requires an input decoupling capacitor and a bulk capacitor is needed depending on the application. A ceramic capacitor over 10 μF is recommended for the decoupling capacitor. An additional 0.1 µF capacitor from pin 14 to ground is recommended to improve the stability of the over-current limit function. The capacitor voltage rating needs to be greater than the maximum input voltage.
PAGE 16
TPS54226 SLVSA14E – OCTOBER 2009 – REVISED JULY 2011 www.ti.com LAYOUT CONSIDERATIONS The following layout guidelines are provided using the PWP 14 pin package as an example. The general guidelines and routing are also applicable to the QFN 16 pin package. Allowance should be made for the differences in the package pin configurations. 1. Keep the input switching current loop as small as possible. 2.
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TPS54226 SLVSA14E – OCTOBER 2009 – REVISED JULY 2011 www.ti.com REVISION HISTORY Changes from Original (October 2009) to Revision A • Page Changed the device from Product Preview to Production .................................................................................................... 1 Changes from Revision A (October 2009) to Revision B Page • Changed the title to include Eco-Mode ..............................................................................................................
PAGE 18
TPS54226 SLVSA14E – OCTOBER 2009 – REVISED JULY 2011 www.ti.com Changes from Revision D (February 2011) to Revision E Page • Changed EN high-level input voltage min from 2 V to 1.5 V ................................................................................................ 3 • Changed EN low-level input voltage max from 0.48 V to 0.4 V ...........................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 30-Jan-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) TPS54226PWPR HTSSOP PWP 14 2000 330.0 12.4 TPS54226PWPR HTSSOP PWP 14 2000 330.0 TPS54226RGTR QFN RGT 16 3000 330.0 TPS54226RGTT QFN RGT 16 250 180.0 6.9 5.6 1.6 8.0 12.0 Q1 12.4 6.9 5.6 1.6 8.0 12.0 Q1 12.4 3.3 3.3 1.1 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 30-Jan-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS54226PWPR HTSSOP PWP 14 2000 367.0 367.0 35.0 TPS54226PWPR HTSSOP PWP 14 2000 367.0 367.0 35.0 TPS54226RGTR QFN RGT 16 3000 367.0 367.0 35.0 TPS54226RGTT QFN RGT 16 250 210.0 185.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.