Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - DC/DC voltage regulator Buck, Split-rail MSOP 10

VIN

GND

BOOT

VSENSE

COMP

TPS54240

RT /CLK

SS /TR

PWRGD

VIN

OUT

100

0 0.5 1.0 1.5 2.0

I - Output Current - A

Efficiency - %

2.5 3.0

VIN=12V

VOUT=3.3V

fsw=300kHz

DRCDGQ

TPS54240

www.ti.com

SLVSAA6A –APRIL 2010–REVISED DECEMBER 2012

3.5V to 42V STEP DOWN SWIFT™ DC/DC CONVERTER WITH ECO-MODE™

Check for Samples: TPS54240

FEATURES

• 0.8-V Internal Voltage Reference

• 10-Pin MSOP and 10-Pin 3mm × 3mm SON

• 3.5V to 42V Input Voltage Range

Packages with PowerPAD™

• 200-mΩ High-Side MOSFET

• Supported by WEBENCH™ Software Tool

• High Efficiency at Light Loads with a Pulse

• For SWIFT™ Documentation, See the TI

Skipping Eco-Mode™

Website at http://www.ti.com/swift

• 138μA Operating Quiescent Current

• 1.3μA Shutdown Current

APPLICATIONS

• 100kHz to 2.5MHz Switching Frequency

• 12-V and 24-V Industrial and Commercial Low

• Synchronizes to External Clock

Power Systems

• Adjustable Slow Start/Sequencing

• GSM, GPRS Modules in Fleet Management, E-

• UV and OV Power Good Output

Meters, and Security Systems

• Adjustable UVLO Voltage and Hysteresis

DESCRIPTION

The TPS54240 device is a 42V, 2.5A, step down regulator with an integrated high side MOSFET. Current mode

control provides simple external compensation and flexible component selection. A low ripple pulse skip mode

reduces the no load, regulated output supply current to 138μA. Using the enable pin, shutdown supply current is

reduced to 1.3μA, when the enable pin is low.

Under voltage lockout is internally set at 2.5V, but can be increased using the enable pin. The output voltage

startup ramp is controlled by the slow start pin that can also be configured for sequencing/tracking. An open

drain power good signal indicates the output is within 94% to 107% of its nominal voltage.

A wide switching frequency range allows efficiency and external component size to be optimized. Frequency fold

back and thermal shutdown protects the part during an overload condition.

The TPS54240 is available in 10 pin thermally enhanced MSOP and 10-pin 3mm x 3mm SON Power Pad™

package.

SIMPLIFIED SCHEMATIC EFFICIENCY vs LOAD CURRENT

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2Eco-Mode, PowerPAD, WEBENCH, SWIFT are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (53 pages)

PAGE 1
TPS54240 DGQ DRC www.ti.com SLVSAA6A – APRIL 2010 – REVISED DECEMBER 2012 3.5V to 42V STEP DOWN SWIFT™ DC/DC CONVERTER WITH ECO-MODE™ Check for Samples: TPS54240 FEATURES • • 1 • • • 2 • • • • • • • 3.5V to 42V Input Voltage Range 200-mΩ High-Side MOSFET High Efficiency at Light Loads with a Pulse Skipping Eco-Mode™ 138μA Operating Quiescent Current 1.3μA Shutdown Current 100kHz to 2.
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TPS54240 SLVSAA6A – APRIL 2010 – REVISED DECEMBER 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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TPS54240 www.ti.com SLVSAA6A – APRIL 2010 – REVISED DECEMBER 2012 THERMAL INFORMATION TPS54240 THERMAL METRIC (1) (2) DGQ (10 PINS) θJA Junction-to-ambient thermal resistance (standard board) 62.5 40 ψJT Junction-to-top characterization parameter 1.7 0.6 ψJB Junction-to-board characterization parameter 20.1 7.5 θJCtop Junction-to-case(top) thermal resistance 83 65 θJCbot Junction-to-case(bottom) thermal resistance 21 7.
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TPS54240 SLVSAA6A – APRIL 2010 – REVISED DECEMBER 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) TJ = –40°C to 150°C, VIN = 3.5 to 42V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ERROR AMPLIFIER Input current 50 nA Error amplifier transconductance (gM) –2 μA < ICOMP < 2 μA, VCOMP = 1 V 310 μMhos Error amplifier transconductance (gM) –2 μA < ICOMP < 2 μA, VCOMP = 1 V, during slow start VVSENSE = 0.4 V 70 μMhos Error amplifier dc gain VVSENSE = 0.
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TPS54240 www.ti.com SLVSAA6A – APRIL 2010 – REVISED DECEMBER 2012 DEVICE INFORMATION PIN CONFIGURATION DRC PACKAGE (TOP VIEW) DGQ PACKAGE (TOP VIEW) BOOT VIN EN SS/TR RT/CLK 1 10 2 9 3 4 Thermal Pad (11) 5 8 7 6 PH GND COMP VSENSE PWRGD BOOT 1 10 PH VIN EN SS/TR RT/CLK 2 9 GND COMP VSENSE PWRGD 3 4 5 Thermal Pad (11) 8 7 6 PIN FUNCTIONS PIN I/O DESCRIPTION NAME NO. BOOT 1 O A bootstrap capacitor is required between BOOT and PH.
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TPS54240 SLVSAA6A – APRIL 2010 – REVISED DECEMBER 2012 www.ti.
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TPS54240 www.ti.com SLVSAA6A – APRIL 2010 – REVISED DECEMBER 2012 TYPICAL CHARACTERISTICS VOLTAGE REFERENCE vs JUNCTION TEMPERATURE 0.816 VI = 12 V VI = 12 V 375 Vref - Voltage Reference - V RDSON - Static Drain-Source On-State Resistance - mW ON RESISTANCE vs JUNCTION TEMPERATURE 500 BOOT-PH = 3 V 250 BOOT-PH = 6 V 125 0 -50 0.808 0.800 0.792 0.784 -50 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 -25 0 150 25 50 75 100 TJ - Junction Temperature - °C 125 150 Figure 1.
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TPS54240 SLVSAA6A – APRIL 2010 – REVISED DECEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) EA TRANSCONDUCTANCE DURING SLOW START vs JUNCTION TEMPERATURE EA TRANSCONDUCTANCE vs JUNCTION TEMPERATURE 500 120 VI = 12 V VI = 12 V 450 100 gm - mA/V gm - mA/V 400 80 60 350 300 40 250 20 -50 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 200 -50 150 -25 0 25 50 75 100 125 150 TJ - Junction Temperature - °C Figure 7. Figure 8.
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TPS54240 www.ti.com SLVSAA6A – APRIL 2010 – REVISED DECEMBER 2012 TYPICAL CHARACTERISTICS (continued) SS/TR DISCHARGE CURRENT vs JUNCTION TEMPERATURE SWITCHING FREQUENCY vs VSENSE 575 100 VI = 12 V, TJ = 25°C VI = 12 V 80 % of Nominal fsw II(SS/TR) - mA 500 425 350 275 60 40 20 200 -50 0 0 50 100 TJ - Junction Temperature - °C 150 0 0.8 SHUTDOWN SUPPLY CURRENT vs JUNCTION TEMPERATURE SHUTDOWN SUPPLY CURRENT vs INPUT VOLTAGE (Vin) 2 TJ = 25°C 1.5 1.5 I(VIN) - mA I(VIN) - mA 0.
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TPS54240 SLVSAA6A – APRIL 2010 – REVISED DECEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) PWRGD ON RESISTANCE vs JUNCTION TEMPERATURE PWRGD THRESHOLD vs JUNCTION TEMPERATURE 115 100 VI = 12 V PWRGD Threshold - % of Vref VI = 12 V RDSON - W 80 60 40 20 0 -50 VSENSE Rising 110 VSENSE Falling 105 100 VSENSE Rising 95 VSENSE Falling 90 -25 0 50 25 75 100 125 85 -50 150 -25 0 INPUT VOLTAGE (UVLO) vs JUNCTION TEMPERATURE 2.3 2.75 2 1.8 2.50 2.
PAGE 11
TPS54240 www.ti.com SLVSAA6A – APRIL 2010 – REVISED DECEMBER 2012 OVERVIEW The TPS54240 device is a 42-V, 2.5-A, step-down (buck) regulator with an integrated high side n-channel MOSFET. To improve performance during line and load transients the device implements a constant frequency, current mode control which reduces output capacitance and simplifies external frequency compensation design.
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TPS54240 SLVSAA6A – APRIL 2010 – REVISED DECEMBER 2012 www.ti.com DETAILED DESCRIPTION Fixed Frequency PWM Control The TPS54240 uses an adjustable fixed frequency, peak current mode control. The output voltage is compared through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives the COMP pin. An internal oscillator initiates the turn on of the high side power switch. The error amplifier output is compared to the high side power switch current.
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TPS54240 www.ti.com SLVSAA6A – APRIL 2010 – REVISED DECEMBER 2012 DETAILED DESCRIPTION (continued) Attention must be taken in maximum duty cycle applications which experience extended time periods with light loads or no load. When the voltage across the BOOT capacitor falls below the 2.1V UVLO threshold, the high side MOSFET is turned off, but there may not be enough inductor current to pull the PH pin down to recharge the BOOT capacitor.
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TPS54240 SLVSAA6A – APRIL 2010 – REVISED DECEMBER 2012 www.ti.com DETAILED DESCRIPTION (continued) æ Vout - 0.8V ö R1 = R2 ´ ç ÷ 0.8 V è ø (1) Enable and Adjusting Undervoltage Lockout The TPS54240 is disabled when the VIN pin voltage falls below 2.5 V. If an application requires a higher undervoltage lockout (UVLO), use the EN pin as shown in Figure 27 to adjust the input voltage UVLO by using the two external resistors.
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TPS54240 www.ti.com SLVSAA6A – APRIL 2010 – REVISED DECEMBER 2012 DETAILED DESCRIPTION (continued) R1 = R2 = VSTART - VSTOP V IHYS + OUT R3 (4) VENA VSTART - VENA V + I1 - ENA R1 R3 (5) Slow Start/Tracking Pin (SS/TR) The TPS54240 effectively uses the lower voltage of the internal voltage reference or the SS/TR pin voltage as the power-supply's reference voltage and regulates the output accordingly. A capacitor on the SS/TR pin to ground implements a slow start time.
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TPS54240 SLVSAA6A – APRIL 2010 – REVISED DECEMBER 2012 www.ti.com DETAILED DESCRIPTION (continued) Overload Recovery Circuit The TPS54240 has an overload recovery (OLR) circuit. The OLR circuit will slow start the output from the overload voltage to the nominal regulation voltage once the fault condition is removed.
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TPS54240 www.ti.com SLVSAA6A – APRIL 2010 – REVISED DECEMBER 2012 DETAILED DESCRIPTION (continued) TPS54160 TPS54240 3 EN 4 SS/TR 6 PWRGD EN1, EN2 VOUT1 TPS54240 TPS54160 VOUT2 3 EN 4 SS/TR 6 PWRGD Figure 32. Schematic for Ratiometric Start-Up Sequence Figure 33. Ratio-Metric Startup using Coupled SS/TR pins Figure 32 shows a method for ratio-metric start up sequence by connecting the SS/TR pins together. The regulator outputs will ramp up and reach regulation at the same time.
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TPS54240 SLVSAA6A – APRIL 2010 – REVISED DECEMBER 2012 www.ti.com DETAILED DESCRIPTION (continued) Ratio-metric and simultaneous power supply sequencing can be implemented by connecting the resistor network of R1 and R2 shown in Figure 34 to the output of the power supply that needs to be tracked or another voltage reference source. Using Equation 7 and Equation 8, the tracking resistors can be calculated to initiate the Vout2 slightly before, after or at the same time as Vout1.
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TPS54240 www.ti.com SLVSAA6A – APRIL 2010 – REVISED DECEMBER 2012 DETAILED DESCRIPTION (continued) EN VOUT1 VOUT2 Figure 37.
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TPS54240 SLVSAA6A – APRIL 2010 – REVISED DECEMBER 2012 www.ti.com DETAILED DESCRIPTION (continued) Constant Switching Frequency and Timing Resistor (RT/CLK Pin) The switching frequency of the TPS54240 is adjustable over a wide range from approximately 100kHz to 2500kHz by placing a resistor on the RT/CLK pin. The RT/CLK pin voltage is typically 0.5V and must have a resistor to ground to set the switching frequency.
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TPS54240 www.ti.com SLVSAA6A – APRIL 2010 – REVISED DECEMBER 2012 DETAILED DESCRIPTION (continued) Selecting the Switching Frequency The switching frequency that is selected should be the lower value of the two equations, Equation 12 and Equation 13. Equation 12 is the maximum switching frequency limitation set by the minimum controllable on time. Setting the switching frequency above this value will cause the regulator to skip switching pulses.
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TPS54240 SLVSAA6A – APRIL 2010 – REVISED DECEMBER 2012 www.ti.com DETAILED DESCRIPTION (continued) How to Interface to RT/CLK Pin The RT/CLK pin can be used to synchronize the regulator to an external system clock. To implement the synchronization feature connect a square wave to the RT/CLK pin through the circuit network shown in Figure 41. The square wave amplitude must transition lower than 0.5V and higher than 2.
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TPS54240 www.ti.com SLVSAA6A – APRIL 2010 – REVISED DECEMBER 2012 DETAILED DESCRIPTION (continued) PH PH EXT EXT IL IL Figure 42. Plot of Synchronizing in ccm Figure 43. Plot of Synchronizing in dcm PH EXT IL Figure 44. Plot of Synchronizing in PSM Power Good (PWRGD Pin) The PWRGD pin is an open drain output. Once the VSENSE pin is between 94% and 107% of the internal voltage reference the PWRGD pin is de-asserted and the pin floats.
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TPS54240 SLVSAA6A – APRIL 2010 – REVISED DECEMBER 2012 www.ti.com DETAILED DESCRIPTION (continued) The PWRGD pin is pulled low when the VSENSE is lower than 92% or greater than 109% of the nominal internal reference voltage. Also, the PWRGD is pulled low, if the UVLO or thermal shutdown are asserted or the EN pin pulled low.
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TPS54240 www.ti.com SLVSAA6A – APRIL 2010 – REVISED DECEMBER 2012 DETAILED DESCRIPTION (continued) PH VO Power Stage gmps 10.5 A/V a b RESR R1 RL COMP c 0.8 V R3 CO C2 RO COUT VSENSE gmea 350 mA/V R2 C1 Figure 45. Small Signal Model for Loop Response Simple Small Signal Model for Peak Current Mode Control Figure 46 describes a simple small signal model that can be used to understand how to design the frequency compensation.
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TPS54240 SLVSAA6A – APRIL 2010 – REVISED DECEMBER 2012 www.ti.com DETAILED DESCRIPTION (continued) VO Adc VC RESR fp RL gmps COUT fz Figure 46.
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TPS54240 www.ti.com SLVSAA6A – APRIL 2010 – REVISED DECEMBER 2012 DETAILED DESCRIPTION (continued) VO R1 VSENSE gmea Type 2A COMP Type 2B Type 1 Vref R2 RO R3 CO C2 C1 R3 C2 C1 Figure 47. Types of Frequency Compensation Aol A0 P1 Z1 P2 A1 BW Figure 48.
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TPS54240 SLVSAA6A – APRIL 2010 – REVISED DECEMBER 2012 www.ti.
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TPS54240 www.ti.com SLVSAA6A – APRIL 2010 – REVISED DECEMBER 2012 APPLICATION INFORMATION Design Guide — Step-By-Step Design Procedure This example details the design of a high frequency switching regulator design using ceramic output capacitors. A few parameters must be known in order to start the design process. These parameters are typically determined at the system level. For this example, we will start with the following known parameters: Output Voltage 3.3 V Transient Response 0 to 1.
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TPS54240 SLVSAA6A – APRIL 2010 – REVISED DECEMBER 2012 www.ti.com TPS54240DGQ Figure 49. 3.3V Output TPS54240 Design Example. Output Inductor Selection (LO) To calculate the minimum value of the output inductor, use Equation 28. KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. The inductor ripple current will be filtered by the output capacitor.
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TPS54240 www.ti.com IRIPPLE = IL(rms) = SLVSAA6A – APRIL 2010 – REVISED DECEMBER 2012 VOUT ´ (Vin max - VOUT ) Vin max ´ L O ´ fSW 1 - VOUT ) ö ÷ ÷ Vinmax ´ LO ´ fSW ø æ VOUT ´ (IO )2 + 12 ´ çç è (29) (Vinmax 2 (30) Iripple ILpeak = Iout + 2 (31) Output Capacitor There are three primary considerations for selecting the value of the output capacitor.
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TPS54240 SLVSAA6A – APRIL 2010 – REVISED DECEMBER 2012 www.ti.com Capacitors generally have limits to the amount of ripple current they can handle without failing or producing excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor data sheets specify the Root Mean Square (RMS) value of the maximum ripple current. Equation 36 can be used to calculate the RMS ripple current the output capacitor needs to support.
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TPS54240 www.ti.com SLVSAA6A – APRIL 2010 – REVISED DECEMBER 2012 Input Capacitor The TPS54240 requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least 3 μF of effective capacitance and in some applications a bulk capacitance. The effective capacitance includes any dc bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage.
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TPS54240 SLVSAA6A – APRIL 2010 – REVISED DECEMBER 2012 www.ti.com The slow start time must be long enough to allow the regulator to charge the output capacitor up to the output voltage without drawing excessive current. Equation 40 can be used to find the minimum slow start time, tss, necessary to charge the output capacitor, Cout, from 10% to 90% of the output voltage, Vout, with an average slow start current of Issavg. In the example, to charge the effective output capacitance of 72.4 µF up to 3.
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TPS54240 www.ti.com SLVSAA6A – APRIL 2010 – REVISED DECEMBER 2012 Ioutmax 2 × p × Vout × Cout 1 ¦ z mod = 2 ´ p ´ Resr × Cout ¦p mod = (41) (42) fco = f p mod ´ f z mod (43) fco = f f p mod ´ sw 2 (44) To determine the compensation resistor, R4, use Equation 45. Assume the power stage transconductance, gmps, is 10.5A/V. The output voltage, Vo, reference voltage, VREF, and amplifier transconductance, gmea, are 3.3V, 0.8V and 310 μA/V, respectively. R4 is calculated to be 20.
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TPS54240 SLVSAA6A – APRIL 2010 – REVISED DECEMBER 2012 www.ti.com Vout = 20 mV / div (ac coupled) Vout = 20 mV / div (ac coupled) PH = 5 V / div PH = 5 V / div Time = 2 usec / div Time = 2 usec / div Figure 52. Output Ripple CCM Figure 53. Output Ripple, DCM Vin = 200 mV / div (ac coupled) Vout = 20 mV / div (ac coupled) PH = 5 V / div PH = 5 V / div Time = 2 usec / div Time = 10 usec / div Figure 54. Output Ripple, PSM Figure 55.
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TPS54240 www.ti.com SLVSAA6A – APRIL 2010 – REVISED DECEMBER 2012 100 60 180 90 40 80 120 Phase 70 60 Gain 50 40 0 0 -20 30 VIN=12V VOUT=3.3V fsw=300kHz 20 -60 VIN=12 V VOUT=3.3V IOUT=2.5A -40 10 0 0.001 0.1 0.01 IO - Output Current - A -60 10 100 -120 1-104 1-103 f - Frequency - Hz 3.4 3.4 3.38 3.38 3.36 3.34 3.32 3.36 3.34 VIN=12V VOUT=3.3V fsw=300kHz IOUT=1.5A 3.32 VIN=12V VOUT=3.3V fsw=300kHz 3.3 0 0.5 1.5 1.0 2.0 IO - Output Current - A 2.5 Figure 60.
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TPS54240 SLVSAA6A – APRIL 2010 – REVISED DECEMBER 2012 www.ti.com Power Dissipation Estimate The following formulas show how to estimate the IC power dissipation under continuous conduction mode (CCM) operation. These equations should not be used if the device is working in discontinuous conduction mode (DCM). The power dissipation of the IC includes conduction loss (Pcon), switching loss (Psw), gate drive loss (Pgd) and supply current (Pq).
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TPS54240 www.ti.com SLVSAA6A – APRIL 2010 – REVISED DECEMBER 2012 Layout Layout is a critical portion of good power supply design. There are several signals paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help eliminate these problems, the VIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor with X5R or X7R dielectric.
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TPS54240 SLVSAA6A – APRIL 2010 – REVISED DECEMBER 2012 www.ti.com VIN + Cin Cboot Lo Cd PH BOOT VIN GND R1 + GND Co R2 TPS54240 VOUT VSENSE EN COMP SS/TR Rcomp RT/CLK Css Czero RT Cpole Figure 63. TPS54240 Inverting Power Supply from SLVA317 Application Note VOPOS + VIN Copos + Cin Cboot BOOT VIN GND PH Lo Cd R1 GND + Coneg R2 TPS54240 VONEG VSENSE EN COMP SS/TR Rcomp RT/CLK Css RT Czero Cpole Figure 64.
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TPS54240 www.ti.com SLVSAA6A – APRIL 2010 – REVISED DECEMBER 2012 TPS54240DGQ Figure 65. 12V to 3.8V GSM Power Supply TPS54240DGQ Figure 66. 24V to 4.
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TPS54240 SLVSAA6A – APRIL 2010 – REVISED DECEMBER 2012 www.ti.com REVISION HISTORY NOTE: Page numbers of current version may differ from previous versions. Changes from Original (April 2010) to Revision A Page • Added 10-Pin 3mm x 3mm SON to Features ....................................................................................................................... 1 • Added DRC package option to Ordering Information table ...........................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 31-Oct-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 12-Jun-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS54240DGQR MSOPPower PAD DGQ 10 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 TPS54240DGQR MSOPPower PAD DGQ 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TPS54240DRCR SON DRC 10 3000 330.0 12.4 3.3 3.3 1.0 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 12-Jun-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS54240DGQR MSOP-PowerPAD DGQ 10 2500 346.0 346.0 35.0 TPS54240DGQR MSOP-PowerPAD DGQ 10 2500 364.0 364.0 27.0 TPS54240DRCR SON DRC 10 3000 346.0 346.0 35.0 TPS54240DRCT SON DRC 10 250 203.0 203.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.