Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - DC/DC voltage regulator Buck, Split-rail MSOP 10

VIN

GND

BOOT

VSENSE

COMP

TPS54240

RT /CLK

SS /TR

PWRGD

VIN

OUT

100

0 0.5 1.0 1.5 2.0

I - Output Current - A

Efficiency - %

2.5 3.0

VIN=12V

VOUT=3.3V

fsw=300kHz

TPS54240-Q1

www.ti.com

SLVSAQ4B –DECEMBER 2010–REVISED SEPTEMBER 2013

3.5-V to 42-V STEP-DOWN SWIFT™ DC/DC CONVERTER WITH Eco-mode™ CONTROL

SCHEME

Check for Samples: TPS54240-Q1

FEATURES

APPLICATIONS

• Qualified for Automotive Applications

• 12-V and 24-V Industrial and Commercial Low-

Power Systems

• AEC Q100 Qualified With the Following

Results: • GSM, GPRS Modules in Fleet Management, E-

Meters, and Security Systems

– Device Temperature Grade 1: –40°C to

125°C Ambient Operating Temperature

DESCRIPTION

Range

The TPS54240-Q1 device is a 42-V, 2.5-A, step-

– Device HBM ESD Classification Level H2

down regulator with an integrated high-side MOSFET.

– Device CDM ESD Classification Level C6

Current-mode control provides simple external

• 3.5-V to 42-V Input Voltage Range

compensation and flexible component selection. A

low-ripple pulse-skip mode reduces the no-load,

• 200-mΩ High-Side MOSFET

regulated-output supply current to 138 μA. Using the

• High Efficiency at Light Loads With a Pulse-

enable pin, shutdown supply current is reduced to 1.3

Skipping Eco-mode™ Control Scheme

μA when the enable pin is low.

• 138-μA Operating Quiescent Current

Undervoltage lockout is internally set at 2.5 V, but

• 1.3-μA Shutdown Current

can be increased using the enable pin. The output

voltage start-up ramp is controlled by the slow-start

• 100-kHz to 2.5-MHz Switching Frequency

pin that can also be configured for

• Synchronizes to External Clock

sequencing/tracking. An open-drain power-good

• Adjustable Slow Start/Sequencing

signal indicates the output is within 94% to 107% of

• UV and OV Power-Good Output

its nominal voltage.

• Adjustable UVLO Voltage and Hysteresis

A wide switching-frequency range allows efficiency

and external component size to be optimized.

• 0.8-V Internal Voltage Reference

Frequency foldback and thermal shutdown protects

• MSOP10 PowerPAD™ Package

the part during an overload condition.

• Supported by SwitcherPro™ Software Tool

The TPS54240-Q1 is available in a 10-pin thermally

(http://focus.ti.com/docs/toolsw/folders/print/s

enhanced MSOP PowerPAD package.

witcherpro.html)

• For SWIFT™ Documentation, See the TI Web

site at http://www.ti.com/swift

SIMPLIFIED SCHEMATIC EFFICIENCY vs LOAD CURRENT

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2Eco-mode, PowerPAD, SwitcherPro, SWIFT are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (52 pages)

PAGE 1
TPS54240-Q1 www.ti.com SLVSAQ4B – DECEMBER 2010 – REVISED SEPTEMBER 2013 3.5-V to 42-V STEP-DOWN SWIFT™ DC/DC CONVERTER WITH Eco-mode™ CONTROL SCHEME Check for Samples: TPS54240-Q1 FEATURES APPLICATIONS • • • 1 2 • • • • • • • • • • • • • • Qualified for Automotive Applications AEC Q100 Qualified With the Following Results: – Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature Range – Device HBM ESD Classification Level H2 – Device CDM ESD Classification Level C6 3.
PAGE 2
TPS54240-Q1 SLVSAQ4B – DECEMBER 2010 – REVISED SEPTEMBER 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
PAGE 3
TPS54240-Q1 www.ti.com SLVSAQ4B – DECEMBER 2010 – REVISED SEPTEMBER 2013 THERMAL INFORMATION TPS54240-Q1 THERMAL METRIC (1) (2) DGQ UNIT 10 PINS θJA Junction-to-ambient thermal resistance (standard board) 62.5 (3) θJA Junction-to-ambient thermal resistance (custom board) θJCtop Junction-to-case (top) thermal resistance 83 θJB Junction-to-board thermal resistance 28 ψJT Junction-to-top characterization parameter 1.7 ψJB Junction-to-board characterization parameter 20.
PAGE 4
TPS54240-Q1 SLVSAQ4B – DECEMBER 2010 – REVISED SEPTEMBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) TJ = –40°C to 150°C, VIN = 3.5 V to 42 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 3.5 6.
PAGE 5
TPS54240-Q1 www.ti.com SLVSAQ4B – DECEMBER 2010 – REVISED SEPTEMBER 2013 DEVICE INFORMATION PIN CONFIGURATION DGQ PACKAGE (TOP VIEW) DRC PACKAGE (TOP VIEW) BOOT 1 10 PH VIN 2 9 GND Thermal Pad (11) BOOT 1 VIN 2 10 Thermal Pad (11) PH 9 GND 8 COMP 8 COMP EN 3 4 7 VSENSE SS/TR 4 7 VSENSE 5 6 PWRGD RT/CLK 5 6 PWRGD EN 3 SS/TR RT/CLK PIN FUNCTIONS PIN I/O DESCRIPTION 1 O Connect a bootstrap capacitor between BOOT and PH.
PAGE 6
TPS54240-Q1 SLVSAQ4B – DECEMBER 2010 – REVISED SEPTEMBER 2013 www.ti.
PAGE 7
TPS54240-Q1 www.ti.com SLVSAQ4B – DECEMBER 2010 – REVISED SEPTEMBER 2013 TYPICAL CHARACTERISTICS VOLTAGE REFERENCE vs JUNCTION TEMPERATURE 0.816 500 VI = 12 V VI = 12 V 375 Vref - Voltage Reference - V RDSON - Static Drain-Source On-State Resistance - mW ON-RESISTANCE vs JUNCTION TEMPERATURE BOOT-PH = 3 V 250 BOOT-PH = 6 V 125 0 -50 0.808 0.800 0.792 0.784 -50 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 -25 0 150 Figure 1.
PAGE 8
TPS54240-Q1 SLVSAQ4B – DECEMBER 2010 – REVISED SEPTEMBER 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) EA TRANSCONDUCTANCE DURING SLOW START vs JUNCTION TEMPERATURE EA TRANSCONDUCTANCE vs JUNCTION TEMPERATURE 500 120 VI = 12 V VI = 12 V 450 100 gm - mA/V gm - mA/V 400 80 60 350 300 40 20 -50 250 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 200 -50 150 -25 0 25 50 75 100 125 150 TJ - Junction Temperature - °C Figure 7. Figure 8.
PAGE 9
TPS54240-Q1 www.ti.com SLVSAQ4B – DECEMBER 2010 – REVISED SEPTEMBER 2013 TYPICAL CHARACTERISTICS (continued) SS/TR DISCHARGE CURRENT vs JUNCTION TEMPERATURE SWITCHING FREQUENCY vs VSENSE 575 100 VI = 12 V, TJ = 25°C VI = 12 V 80 % of Nominal fsw II(SS/TR) - mA 500 425 350 275 60 40 20 200 -50 0 0 50 100 TJ - Junction Temperature - °C 150 0 0.8 SHUTDOWN SUPPLY CURRENT vs JUNCTION TEMPERATURE SHUTDOWN SUPPLY CURRENT vs INPUT VOLTAGE (VIN) 2 TJ = 25°C 1.5 1.
PAGE 10
TPS54240-Q1 SLVSAQ4B – DECEMBER 2010 – REVISED SEPTEMBER 2013 www.ti.
PAGE 11
TPS54240-Q1 www.ti.com SLVSAQ4B – DECEMBER 2010 – REVISED SEPTEMBER 2013 OVERVIEW The TPS54240-Q1 device is a 42-V, 2.5-A, step-down (buck) regulator with an integrated high-side n-channel MOSFET. To improve performance during line and load transients, the device implements a constant-frequency, current-mode control which reduces output capacitance and simplifies external frequency compensation design.
PAGE 12
TPS54240-Q1 SLVSAQ4B – DECEMBER 2010 – REVISED SEPTEMBER 2013 www.ti.com DETAILED DESCRIPTION Fixed-Frequency PWM Control The TPS54240-Q1 uses an adjustable fixed-frequency, peak-current-mode control. The output voltage is compared through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives the COMP pin. An internal oscillator initiates the turnon of the high-side power switch.
PAGE 13
TPS54240-Q1 www.ti.com SLVSAQ4B – DECEMBER 2010 – REVISED SEPTEMBER 2013 DETAILED DESCRIPTION (continued) Attention must be taken in maximum-duty-cycle applications which experience extended time periods with light loads or no load. When the voltage across the BOOT capacitor falls below the 2.1-V UVLO threshold, the highside MOSFET is turned off, but there may not be enough inductor current to pull the PH pin down to recharge the BOOT capacitor.
PAGE 14
TPS54240-Q1 SLVSAQ4B – DECEMBER 2010 – REVISED SEPTEMBER 2013 www.ti.com DETAILED DESCRIPTION (continued) æ Vout - 0.8V ö R1 = R2 ´ ç ÷ 0.8 V è ø (1) Enable and Adjusting Undervoltage Lockout The TPS54240-Q1 is disabled when the VIN pin voltage falls below 2.5 V. If an application requires a higher undervoltage lockout (UVLO), use the EN pin as shown in Figure 27 to adjust the input voltage UVLO by using the two external resistors.
PAGE 15
TPS54240-Q1 www.ti.com SLVSAQ4B – DECEMBER 2010 – REVISED SEPTEMBER 2013 DETAILED DESCRIPTION (continued) R1 = R2 = VSTART - VSTOP V IHYS + OUT R3 (4) VENA VSTART - VENA V + I1 - ENA R1 R3 (5) Do not place a low-impedance voltage source with greater than 5 V directly on the EN pin. Do not place a capacitor directly on the EN pin if VEN > 5 V when using a voltage divider to adjust the start and stop voltage. The node voltage, (see Figure 29) must remain equal to or less than 5.8 V.
PAGE 16
TPS54240-Q1 SLVSAQ4B – DECEMBER 2010 – REVISED SEPTEMBER 2013 www.ti.com DETAILED DESCRIPTION (continued) EN SS/TR VSENSE VOUT Figure 30. Operation of SS/TR Pin When Starting Overload Recovery Circuit The TPS54240-Q1 has an overload recovery (OLR) circuit. The OLR circuit slow starts the output from the overload voltage to the nominal regulation voltage once the fault condition is removed.
PAGE 17
TPS54240-Q1 www.ti.com SLVSAQ4B – DECEMBER 2010 – REVISED SEPTEMBER 2013 DETAILED DESCRIPTION (continued) TPS54240 EN PWRGD EN EN1 SS /TR SS /TR PWRGD1 PWRGD VOUT1 VOUT2 Figure 31. Schematic for Sequential Start-Up Sequence Figure 32. Sequential Startup using EN and PWRGD TPS54160 TPS54240 3 EN 4 SS/TR 6 PWRGD EN1, EN2 VOUT1 TPS54240 TPS54160 VOUT2 3 EN 4 SS/TR 6 PWRGD Figure 33. Schematic for Ratiometric Startup Using Coupled SS/TR Pins Figure 34.
PAGE 18
TPS54240-Q1 SLVSAQ4B – DECEMBER 2010 – REVISED SEPTEMBER 2013 www.ti.com DETAILED DESCRIPTION (continued) TPS54240 EN VOUT 1 SS/TR PWRGD TPS54240 VOUT 2 EN R1 SS/ TR R2 PWRGD R3 R4 Figure 35. Schematic for Ratiometric and Simultaneous Start-Up Sequence Ratiometric and simultaneous power supply sequencing is implemented by connecting the resistor network of R1 and R2 shown in Figure 35 to the output of the power supply that needs to be tracked or another voltage reference source.
PAGE 19
TPS54240-Q1 www.ti.com SLVSAQ4B – DECEMBER 2010 – REVISED SEPTEMBER 2013 DETAILED DESCRIPTION (continued) EN EN VOUT1 VOUT1 VOUT2 Figure 36. Ratiometric Startup With VOUT2 Leading VOUT1 VOUT2 Figure 37. Ratiometric Startup With VOUT1 Leading VOUT2 EN VOUT1 VOUT2 Figure 38.
PAGE 20
TPS54240-Q1 SLVSAQ4B – DECEMBER 2010 – REVISED SEPTEMBER 2013 www.ti.com DETAILED DESCRIPTION (continued) Constant Switching Frequency and Timing Resistor (RT/CLK Pin) The switching frequency of the TPS54240-Q1 is adjustable over a wide range from approximately 100 kHz to 2500 kHz by placing a resistor on the RT/CLK pin. The RT/CLK pin voltage is typically 0.5 V and must have a resistor to ground to set the switching frequency.
PAGE 21
TPS54240-Q1 www.ti.com SLVSAQ4B – DECEMBER 2010 – REVISED SEPTEMBER 2013 DETAILED DESCRIPTION (continued) Selecting the Switching Frequency The switching frequency that is selected should be the lower value of the two equations, Equation 12 and Equation 13. Equation 12 is the maximum switching frequency limitation set by the minimum controllable on time. Setting the switching frequency above this value causes the regulator to skip switching pulses.
PAGE 22
TPS54240-Q1 SLVSAQ4B – DECEMBER 2010 – REVISED SEPTEMBER 2013 www.ti.com DETAILED DESCRIPTION (continued) How to Interface to RT/CLK Pin The RT/CLK pin is used to synchronize the regulator to an external system clock. To implement the synchronization feature connect a square wave to the RT/CLK pin through the circuit network shown in Figure 42. The square wave amplitude must transition lower than 0.5 V and higher than 2.
PAGE 23
TPS54240-Q1 www.ti.com SLVSAQ4B – DECEMBER 2010 – REVISED SEPTEMBER 2013 DETAILED DESCRIPTION (continued) PH PH EXT EXT IL IL Figure 43. Plot of Synchronizing in CCM Figure 44. Plot of Synchronizing in DCM PH EXT IL Figure 45. Plot of Synchronizing in PSM Power Good (PWRGD Pin) The PWRGD pin is an open drain output. Once the VSENSE pin is between 94% and 107% of the internal voltage reference the PWRGD pin is de-asserted and the pin floats.
PAGE 24
TPS54240-Q1 SLVSAQ4B – DECEMBER 2010 – REVISED SEPTEMBER 2013 www.ti.com DETAILED DESCRIPTION (continued) The PWRGD pin is pulled low when the VSENSE is lower than 92% or greater than 109% of the nominal internal reference voltage. Also, the PWRGD is pulled low, if the UVLO or thermal shutdown are asserted or the EN pin pulled low.
PAGE 25
TPS54240-Q1 www.ti.com SLVSAQ4B – DECEMBER 2010 – REVISED SEPTEMBER 2013 DETAILED DESCRIPTION (continued) PH VO Power Stage gmps 10.5 A/V a b RESR R1 RL COMP c 0.8 V CO R3 RO COUT VSENSE gmea C2 R2 350 mA/V C1 Figure 46. Small-Signal Model for Loop Response Simple Small Signal Model for Peak Current Mode Control Figure 47 describes a simple small signal model that can be used to understand how to design the frequency compensation.
PAGE 26
TPS54240-Q1 SLVSAQ4B – DECEMBER 2010 – REVISED SEPTEMBER 2013 www.ti.com DETAILED DESCRIPTION (continued) æ s ö ç1 + ÷ 2p ´ fZ ø VOUT = Adc ´ è VC æ s ö ç1 + ÷ 2 p ´ fP ø è Adc = gmps ´ RL (14) (15) 1 fP = COUT ´ RL ´ 2p (16) 1 fZ = COUT ´ RESR ´ 2p (17) Small-Signal Model for Frequency Compensation The TPS54240-Q1 uses a transconductance amplifier for the error amplifier and readily supports three of the commonly-used frequency compensation circuits.
PAGE 27
TPS54240-Q1 www.ti.com SLVSAQ4B – DECEMBER 2010 – REVISED SEPTEMBER 2013 DETAILED DESCRIPTION (continued) Aol A0 P1 Z1 P2 A1 BW Figure 49.
PAGE 28
TPS54240-Q1 SLVSAQ4B – DECEMBER 2010 – REVISED SEPTEMBER 2013 www.ti.com APPLICATION INFORMATION Design Guide — Step-By-Step Design Procedure This example details the design of a high frequency switching regulator design using ceramic output capacitors. A few parameters must be known in order to start the design process. These parameters are typically determined at the system level. For this example, use the following known parameters: Output Voltage 3.3 V Transient Response 0- to 1.
PAGE 29
TPS54240-Q1 www.ti.com SLVSAQ4B – DECEMBER 2010 – REVISED SEPTEMBER 2013 TPS54240DGQ Figure 50. 3.3-V Output TPS54240-Q1 Design Example. Output Inductor Selection (LO) To calculate the minimum value of the output inductor, use Equation 28. KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. The inductor ripple current is filtered by the output capacitor.
PAGE 30
TPS54240-Q1 SLVSAQ4B – DECEMBER 2010 – REVISED SEPTEMBER 2013 IRIPPLE = IL(rms) = VOUT ´ (Vin max www.ti.com - VOUT ) Vin max ´ L O ´ fSW 1 - VOUT ) ö ÷ ÷ Vinmax ´ LO ´ fSW ø æ VOUT ´ (IO )2 + 12 ´ çç è (29) (Vinmax 2 Iripple ILpeak = Iout + 2 (30) (31) Output Capacitor There are three primary considerations for selecting the value of the output capacitor.
PAGE 31
TPS54240-Q1 www.ti.com SLVSAQ4B – DECEMBER 2010 – REVISED SEPTEMBER 2013 Capacitors generally have limits to the amount of ripple current they can handle without failing or producing excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor data sheets specify the Root Mean Square (RMS) value of the maximum ripple current. Equation 36 can be used to calculate the RMS ripple current the output capacitor needs to support.
PAGE 32
TPS54240-Q1 SLVSAQ4B – DECEMBER 2010 – REVISED SEPTEMBER 2013 www.ti.com The value of a ceramic capacitor varies significantly over temperature and the amount of dc bias applied to the capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature.
PAGE 33
TPS54240-Q1 www.ti.com SLVSAQ4B – DECEMBER 2010 – REVISED SEPTEMBER 2013 Once the slow start time is known, the slow start capacitor value can be calculated using Equation 6. For the example circuit, the slow start time is not too critical because the output capacitor value is 2 × 47μF which does not require much current to charge to 3.3 V. The example circuit has the slow start time set to an arbitrary value of 3.5 ms which requires a 8.75 nF slow start capacitor.
PAGE 34
TPS54240-Q1 SLVSAQ4B – DECEMBER 2010 – REVISED SEPTEMBER 2013 fco = f p mod ´ f sw 2 www.ti.com (44) To determine the compensation resistor, R4, use Equation 45. Assume the power stage transconductance, gmPS, is 10.5 A/V. The output voltage, Vo, reference voltage, VREF, and amplifier transconductance, gmEA, are 3.3 V, 0.8 V and 310 μA/V, respectively. R4 is calculated to be 20.2 kΩ, use the nearest standard value of 20 kΩ. Use Equation 46 to set the compensation zero to the modulator pole frequency.
PAGE 35
TPS54240-Q1 www.ti.com SLVSAQ4B – DECEMBER 2010 – REVISED SEPTEMBER 2013 APPLICATION CURVES Vout = 50 mv / div (ac coupled) Vin = 10 V / div Vout = 2 V / div Output Current = 1 A / div (Load Step 1.5 A to 2.5 A) EN = 2 V / div SS/TR = 2 V / div Time = 200 usec / div Time = 5 msec / div Figure 51. Load Transient Figure 52. Startup With VIN Vout = 20 mV / div (ac coupled) Vout = 20 mV / div (ac coupled) PH = 5 V / div PH = 5 V / div Time = 2 usec / div Time = 2 usec / div Figure 53.
PAGE 36
TPS54240-Q1 SLVSAQ4B – DECEMBER 2010 – REVISED SEPTEMBER 2013 www.ti.com 100 90 Vin = 50 mV / div (ac coupled) 80 Efficiency - % 70 PH = 5 V / div 60 50 40 30 VIN=12V VOUT=3.3V fsw=300kHz 20 Time = 2 usec / div 10 0 0 Figure 57. Input Ripple, DCM 0.5 2.5 1.0 1.5 2.0 IO - Output Current - A 3.0 Figure 58. Efficiency Versus Load Current 100 60 180 90 40 80 120 Phase 70 60 Gain 50 40 0 0 -20 30 VIN=12V VOUT=3.3V fsw=300kHz 20 -60 VIN=12 V VOUT=3.3V IOUT=2.5A -40 10 0 0.
PAGE 37
TPS54240-Q1 www.ti.com SLVSAQ4B – DECEMBER 2010 – REVISED SEPTEMBER 2013 Power-Dissipation Estimate The following formulas show how to estimate the IC power dissipation under continuous conduction mode (CCM) operation. These equations should not be used if the device is working in discontinuous conduction mode (DCM). The power dissipation of the IC includes conduction loss (Pcon), switching loss (Psw), gate drive loss (Pgd) and supply current (Pq).
PAGE 38
TPS54240-Q1 SLVSAQ4B – DECEMBER 2010 – REVISED SEPTEMBER 2013 www.ti.com Layout Layout is a critical portion of good power supply design. There are several signals paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help eliminate these problems, the VIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor with X5R or X7R dielectric.
PAGE 39
TPS54240-Q1 www.ti.com SLVSAQ4B – DECEMBER 2010 – REVISED SEPTEMBER 2013 Estimated Circuit Area The estimated printed circuit board area for the components used in the design of Figure 50 is 0.55 in2. This area does not include test points or connectors. VIN + Cin Cboot Lo BOOT VIN Cd PH GND R1 + GND Co R2 TPS54240 VOUT VSENSE EN COMP SS/TR Rcomp RT/CLK Css Czero RT Cpole Figure 64.
PAGE 40
TPS54240-Q1 SLVSAQ4B – DECEMBER 2010 – REVISED SEPTEMBER 2013 www.ti.com TPS54240DGQ Figure 66. 12-V to 3.8-V GSM Power Supply TPS54240DGQ Figure 67. 24-V to 4.
PAGE 41
TPS54240-Q1 www.ti.com SLVSAQ4B – DECEMBER 2010 – REVISED SEPTEMBER 2013 REVISION HISTORY Changes from Revision A (April 2011) to Revision B Page • Added AEC qualification text and results for temperature grade and HBM/CDM classifications to FEATURES ................ 1 • Changed ABSOLUTE MAXIMUM RATINGS table and added HBM/CDM classification levels ........................................... 2 • Added DRC package to PIN CONFIGURATION .................................................................
PAGE 42
PACKAGE OPTION ADDENDUM www.ti.
PAGE 43
PACKAGE OPTION ADDENDUM www.ti.
PAGE 44
PACKAGE MATERIALS INFORMATION www.ti.com 11-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS54240QDGQRQ1 MSOPPower PAD DGQ 10 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 TPS54240QDRCRQ1 SON DRC 10 3000 330.0 12.4 3.3 3.3 1.0 8.0 12.
PAGE 45
PACKAGE MATERIALS INFORMATION www.ti.com 11-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS54240QDGQRQ1 MSOP-PowerPAD DGQ 10 2500 370.0 355.0 55.0 TPS54240QDRCRQ1 SON DRC 10 3000 370.0 355.0 55.
PAGE 46
PAGE 47
PAGE 48
PAGE 49
PAGE 50
PAGE 51
PAGE 52
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.