Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - DC/DC voltage regulator Buck, Split-rail VSON 10

DRCDGQ

100

0 0.5 1.0 1.5 2.0

I - Output Current - A

Efficiency - %

2.5 3.0

VIN=12V

VOUT=3.3V

fsw=300kHz

VIN

GND

BOOT

VSENSE

COMP

TPS54260

RT /CLK

SS /TR

PWRGD

TPS54260

www.ti.com

SLVSA86A –MARCH 2010–REVISED DECEMBER 2010

3.5V to 60V INPUT, 2.5A, STEP DOWN CONVERTER WITH ECO-MODE™

Check for Samples: TPS54260

FEATURES

• 0.8-V Internal Voltage Reference

• 3.5V to 60V Input Voltage Range

• 10-Pin MSOP and 10-Pin 3mm × 3mm SON

with PowerPAD™ Packages

• 200-mΩ High-Side MOSFET

• Supported by SwitcherPro™ Software Tool

• High Efficiency at Light Loads with a Pulse

(http://focus.ti.com/docs/toolsw/folders/print/s

Skipping Eco-Mode™

witcherpro.html)

• 138mA Operating Quiescent Current

• For SWIFT™ Documentation, See the TI

• 1.3mA Shutdown Current

Website at http://www.ti.com/swift

• 100kHz to 2.5MHz Switching Frequency

• Synchronizes to External Clock

APPLICATIONS

• Adjustable Slow Start/Sequencing

• 12-V, 24-V and 48-V Industrial and Commercial

Low Power Systems

• UV and OV Power Good Output

• GSM, GPRS Modules in Fleet Management,

• Adjustable UVLO Voltage and Hysteresis

E-Meters, and Security Systems

DESCRIPTION

The TPS54260 device is a 60V, 2.5A, step down regulator with an integrated high side MOSFET. Current mode

control provides simple external compensation and flexible component selection. A low ripple pulse skip mode

reduces the no load, regulated output supply current to 138mA. Using the enable pin, shutdown supply current is

reduced to 1.3mA, when the enable pin is low.

Under voltage lockout is internally set at 2.5V, but can be increased using the enable pin. The output voltage

startup ramp is controlled by the slow start pin that can also be configured for sequencing/tracking. An open

drain power good signal indicates the output is within 94% to 107% of its nominal voltage.

A wide switching frequency range allows efficiency and external component size to be optimized. Frequency fold

back and thermal shutdown protects the part during an overload condition.

The TPS54260 is available in 10-pin thermally enhanced MSOP and 10-pin 3mm × 3mm SON PowerPAD™

packages.

SIMPLIFIED SCHEMATIC EFFICIENCY vs LOAD CURRENT

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2Eco-Mode, PowerPAD, SwitcherPro, SWIFT are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (52 pages)

PAGE 1
TPS54260 DGQ DRC www.ti.com SLVSA86A – MARCH 2010 – REVISED DECEMBER 2010 3.5V to 60V INPUT, 2.5A, STEP DOWN CONVERTER WITH ECO-MODE™ Check for Samples: TPS54260 FEATURES 1 • • • 2 • • • • • • • 3.5V to 60V Input Voltage Range 200-mΩ High-Side MOSFET High Efficiency at Light Loads with a Pulse Skipping Eco-Mode™ 138mA Operating Quiescent Current 1.3mA Shutdown Current 100kHz to 2.
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TPS54260 SLVSA86A – MARCH 2010 – REVISED DECEMBER 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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TPS54260 www.ti.com SLVSA86A – MARCH 2010 – REVISED DECEMBER 2010 THERMAL INFORMATION TPS54260 THERMAL METRIC (1) (2) DGQ (10 PINS) qJA Junction-to-ambient thermal resistance (standard board) qJA Junction-to-ambient thermal resistance (custom board) 62.5 40 57 56.5 yJT yJB Junction-to-top characterization parameter 1.7 0.6 Junction-to-board characterization parameter 20.1 qJCtop 7.
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TPS54260 SLVSA86A – MARCH 2010 – REVISED DECEMBER 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) TJ = –40°C to 150°C, VIN = 3.5 to 60V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 2500 kHz 720 kHz 2200 kHz TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN) Switching frequency range using RT mode fSW Switching frequency 100 RT = 200 kΩ Switching frequency range using CLK mode 450 581 300 Minimum CLK input pulse width 40 RT/CLK high threshold 1.
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TPS54260 www.ti.com SLVSA86A – MARCH 2010 – REVISED DECEMBER 2010 DEVICE INFORMATION PIN CONFIGURATION DRC PACKAGE (TOP VIEW) DGQ PACKAGE (TOP VIEW) BOOT VIN EN SS/TR RT/CLK 10 1 2 3 4 Thermal Pad (11) 5 9 8 7 6 PH GND COMP VSENSE PWRGD BOOT VIN EN SS/TR RT/CLK 1 10 PH 2 9 GND COMP VSENSE PWRGD 3 4 5 Thermal Pad (11) 8 7 6 PIN FUNCTIONS PIN I/O DESCRIPTION NAME NO. BOOT 1 O A bootstrap capacitor is required between BOOT and PH.
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TPS54260 SLVSA86A – MARCH 2010 – REVISED DECEMBER 2010 www.ti.
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TPS54260 www.ti.com SLVSA86A – MARCH 2010 – REVISED DECEMBER 2010 TYPICAL CHARACTERISTICS VOLTAGE REFERENCE vs JUNCTION TEMPERATURE 0.816 500 VI = 12 V VI = 12 V 375 Vref - Voltage Reference - V RDSON - Static Drain-Source On-State Resistance - mW ON RESISTANCE vs JUNCTION TEMPERATURE BOOT-PH = 3 V 250 BOOT-PH = 6 V 125 0 -50 0.808 0.800 0.792 0.784 -50 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 -25 0 150 25 50 75 100 TJ - Junction Temperature - °C 125 150 Figure 1.
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TPS54260 SLVSA86A – MARCH 2010 – REVISED DECEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) EA TRANSCONDUCTANCE DURING SLOW START vs JUNCTION TEMPERATURE EA TRANSCONDUCTANCE vs JUNCTION TEMPERATURE 500 120 VI = 12 V VI = 12 V 450 100 gm - mA/V gm - mA/V 400 80 60 350 300 40 250 20 -50 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 200 -50 150 -25 0 25 50 75 100 125 150 TJ - Junction Temperature - °C Figure 7. Figure 8.
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TPS54260 www.ti.com SLVSA86A – MARCH 2010 – REVISED DECEMBER 2010 TYPICAL CHARACTERISTICS (continued) SS/TR DISCHARGE CURRENT vs JUNCTION TEMPERATURE SWITCHING FREQUENCY vs VSENSE 575 100 VI = 12 V, TJ = 25°C VI = 12 V 80 % of Nominal fsw II(SS/TR) - mA 500 425 350 275 60 40 20 200 -50 0 0 50 100 TJ - Junction Temperature - °C 150 0 0.8 SHUTDOWN SUPPLY CURRENT vs JUNCTION TEMPERATURE SHUTDOWN SUPPLY CURRENT vs INPUT VOLTAGE (Vin) 2 TJ = 25°C 1.5 I(VIN) - mA 1.5 1 0.5 1 0.
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TPS54260 SLVSA86A – MARCH 2010 – REVISED DECEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) PWRGD ON RESISTANCE vs JUNCTION TEMPERATURE PWRGD THRESHOLD vs JUNCTION TEMPERATURE 115 100 VI = 12 V PWRGD Threshold - % of Vref VI = 12 V RDSON - W 80 60 40 20 0 -50 VSENSE Rising 110 VSENSE Falling 105 100 VSENSE Rising 95 VSENSE Falling 90 -25 0 50 25 75 100 125 85 -50 150 -25 0 BOOT-PH UVLO vs JUNCTION TEMPERATURE INPUT VOLTAGE (UVLO) vs JUNCTION TEMPERATURE 3 2.3 2.
PAGE 11
TPS54260 www.ti.com SLVSA86A – MARCH 2010 – REVISED DECEMBER 2010 OVERVIEW The TPS54260 device is a 60-V, 2.5-A, step-down (buck) regulator with an integrated high side n-channel MOSFET. To improve performance during line and load transients the device implements a constant frequency, current mode control which reduces output capacitance and simplifies external frequency compensation design.
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TPS54260 SLVSA86A – MARCH 2010 – REVISED DECEMBER 2010 www.ti.com DETAILED DESCRIPTION Fixed Frequency PWM Control The TPS54260 uses an adjustable fixed frequency, peak current mode control. The output voltage is compared through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives the COMP pin. An internal oscillator initiates the turn on of the high side power switch. The error amplifier output is compared to the high side power switch current.
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TPS54260 www.ti.com SLVSA86A – MARCH 2010 – REVISED DECEMBER 2010 DETAILED DESCRIPTION (continued) Attention must be taken in maximum duty cycle applications which experience extended time periods with light loads or no load. When the voltage across the BOOT capacitor falls below the 2.1V UVLO threshold, the high side MOSFET is turned off, but there may not be enough inductor current to pull the PH pin down to recharge the BOOT capacitor.
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TPS54260 SLVSA86A – MARCH 2010 – REVISED DECEMBER 2010 www.ti.com DETAILED DESCRIPTION (continued) Adjusting the Output Voltage The output voltage is set with a resistor divider from the output node to the VSENSE pin. It is recommended to use 1% tolerance or better divider resistors. Start with a 10 kΩ for the R2 resistor and use the Equation 1 to calculate R1. To improve efficiency at light loads consider using larger value resistors.
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TPS54260 www.ti.com SLVSA86A – MARCH 2010 – REVISED DECEMBER 2010 DETAILED DESCRIPTION (continued) TPS54260 VIN R1 Ihys I1 0.9 mA 2.9 mA + R2 EN 1.25 V R3 - VOUT Figure 28.
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TPS54260 SLVSA86A – MARCH 2010 – REVISED DECEMBER 2010 www.ti.com DETAILED DESCRIPTION (continued) EN SS/TR VSENSE VOUT Figure 29. Operation of SS/TR Pin when Starting Overload Recovery Circuit The TPS54260 has an overload recovery (OLR) circuit. The OLR circuit will slow start the output from the overload voltage to the nominal regulation voltage once the fault condition is removed.
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TPS54260 www.ti.com SLVSA86A – MARCH 2010 – REVISED DECEMBER 2010 DETAILED DESCRIPTION (continued) TPS54260 EN PWRGD EN EN1 SS /TR SS /TR PWRGD1 PWRGD VOUT1 VOUT2 Figure 30. Schematic for Sequential Start-Up Sequence Figure 31. Sequential Startup using EN and PWRGD TPS54160 TPS54260 3 EN 4 SS/TR 6 PWRGD EN1, EN2 VOUT1 TPS54260 TPS54160 VOUT2 3 EN 4 SS/TR 6 PWRGD Figure 32. Schematic for Ratiometric Start-Up Sequence Figure 33.
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TPS54260 SLVSA86A – MARCH 2010 – REVISED DECEMBER 2010 www.ti.com DETAILED DESCRIPTION (continued) TPS54260 EN VOUT 1 SS/TR PWRGD TPS54260 VOUT 2 EN R1 SS/ TR R2 PWRGD R3 R4 Figure 34. Schematic for Ratiometric and Simultaneous Start-Up Sequence Ratio-metric and simultaneous power supply sequencing can be implemented by connecting the resistor network of R1 and R2 shown in Figure 34 to the output of the power supply that needs to be tracked or another voltage reference source.
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TPS54260 www.ti.com SLVSA86A – MARCH 2010 – REVISED DECEMBER 2010 DETAILED DESCRIPTION (continued) EN EN VOUT1 VOUT1 VOUT2 Figure 35. Ratio-metric Startup with Tracking Resistors VOUT2 Figure 36. Ratiometric Startup with Tracking Resistors EN VOUT1 VOUT2 Figure 37.
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TPS54260 SLVSA86A – MARCH 2010 – REVISED DECEMBER 2010 www.ti.com DETAILED DESCRIPTION (continued) Constant Switching Frequency and Timing Resistor (RT/CLK Pin) The switching frequency of the TPS54260 is adjustable over a wide range from approximately 100kHz to 2500kHz by placing a resistor on the RT/CLK pin. The RT/CLK pin voltage is typically 0.5V and must have a resistor to ground to set the switching frequency.
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TPS54260 www.ti.com SLVSA86A – MARCH 2010 – REVISED DECEMBER 2010 DETAILED DESCRIPTION (continued) Selecting the Switching Frequency The switching frequency that is selected should be the lower value of the two equations, Equation 12 and Equation 13. Equation 12 is the maximum switching frequency limitation set by the minimum controllable on time. Setting the switching frequency above this value will cause the regulator to skip switching pulses.
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TPS54260 SLVSA86A – MARCH 2010 – REVISED DECEMBER 2010 www.ti.com DETAILED DESCRIPTION (continued) How to Interface to RT/CLK Pin The RT/CLK pin can be used to synchronize the regulator to an external system clock. To implement the synchronization feature connect a square wave to the RT/CLK pin through the circuit network shown in Figure 41. The square wave amplitude must transition lower than 0.5V and higher than 2.
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TPS54260 www.ti.com SLVSA86A – MARCH 2010 – REVISED DECEMBER 2010 DETAILED DESCRIPTION (continued) PH PH EXT EXT IL IL Figure 42. Plot of Synchronizing in ccm Figure 43. Plot of Synchronizing in dcm PH EXT IL Figure 44. Plot of Synchronizing in PSM Power Good (PWRGD Pin) The PWRGD pin is an open drain output. Once the VSENSE pin is between 94% and 107% of the internal voltage reference the PWRGD pin is de-asserted and the pin floats.
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TPS54260 SLVSA86A – MARCH 2010 – REVISED DECEMBER 2010 www.ti.com DETAILED DESCRIPTION (continued) The PWRGD pin is pulled low when the VSENSE is lower than 92% or greater than 109% of the nominal internal reference voltage. Also, the PWRGD is pulled low, if the UVLO or thermal shutdown are asserted or the EN pin pulled low.
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TPS54260 www.ti.com SLVSA86A – MARCH 2010 – REVISED DECEMBER 2010 DETAILED DESCRIPTION (continued) PH VO Power Stage gmps 10.5 A/V a b RESR R1 RL COMP c 0.8 V CO R3 RO VSENSE COUT gmea C2 R2 310 mA/V C1 Figure 45. Small Signal Model for Loop Response Simple Small Signal Model for Peak Current Mode Control Figure 46 describes a simple small signal model that can be used to understand how to design the frequency compensation.
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TPS54260 SLVSA86A – MARCH 2010 – REVISED DECEMBER 2010 www.ti.com DETAILED DESCRIPTION (continued) æ s ö ç1 + ÷ 2p ´ fZ ø VOUT = Adc ´ è VC æ s ö ç1 + ÷ 2 p ´ fP ø è Adc = gmps ´ RL (14) (15) 1 fP = COUT ´ RL ´ 2p (16) 1 fZ = COUT ´ RESR ´ 2p (17) Small Signal Model for Frequency Compensation The TPS54260 uses a transconductance amplifier for the error amplifier and readily supports three of the commonly-used frequency compensation circuits.
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TPS54260 www.ti.com SLVSA86A – MARCH 2010 – REVISED DECEMBER 2010 DETAILED DESCRIPTION (continued) Aol A0 P1 Z1 P2 A1 BW Figure 48.
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TPS54260 SLVSA86A – MARCH 2010 – REVISED DECEMBER 2010 www.ti.com APPLICATION INFORMATION Design Guide — Step-By-Step Design Procedure This example details the design of a high frequency switching regulator design using ceramic output capacitors. A few parameters must be known in order to start the design process. These parameters are typically determined at the system level. For this example, we will start with the following known parameters: Output Voltage 3.3 V Transient Response 0 to 1.
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TPS54260 www.ti.com SLVSA86A – MARCH 2010 – REVISED DECEMBER 2010 Figure 49. 3.3V Output TPS54260 Design Example. Output Inductor Selection (LO) To calculate the minimum value of the output inductor, use Equation 28. KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. The inductor ripple current will be filtered by the output capacitor.
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TPS54260 SLVSA86A – MARCH 2010 – REVISED DECEMBER 2010 IRIPPLE = IL(rms) = VOUT ´ (Vin max www.ti.com - VOUT ) Vin max ´ L O ´ fSW 1 - VOUT ) ö ÷ ÷ Vinmax ´ LO ´ fSW ø æ VOUT ´ (IO )2 + 12 ´ çç è (29) (Vinmax 2 Iripple ILpeak = Iout + 2 (30) (31) Output Capacitor There are three primary considerations for selecting the value of the output capacitor.
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TPS54260 www.ti.com SLVSA86A – MARCH 2010 – REVISED DECEMBER 2010 Capacitors generally have limits to the amount of ripple current they can handle without failing or producing excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor data sheets specify the Root Mean Square (RMS) value of the maximum ripple current. Equation 36 can be used to calculate the RMS ripple current the output capacitor needs to support.
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TPS54260 SLVSA86A – MARCH 2010 – REVISED DECEMBER 2010 www.ti.com Input Capacitor The TPS54260 requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least 3 mF of effective capacitance and in some applications a bulk capacitance. The effective capacitance includes any dc bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage.
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TPS54260 www.ti.com SLVSA86A – MARCH 2010 – REVISED DECEMBER 2010 The slow start time must be long enough to allow the regulator to charge the output capacitor up to the output voltage without drawing excessive current. Equation 40 can be used to find the minimum slow start time, tss, necessary to charge the output capacitor, Cout, from 10% to 90% of the output voltage, Vout, with an average slow start current of Issavg. In the example, to charge the effective output capacitance of 72.4 µF up to 3.
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TPS54260 SLVSA86A – MARCH 2010 – REVISED DECEMBER 2010 www.ti.com Ioutmax 2 × p × Vout × Cout 1 ¦ z mod = 2 ´ p ´ Resr × Cout ¦p mod = (41) (42) fco = f p mod ´ f z mod (43) fco = f f p mod ´ sw 2 (44) To determine the compensation resistor, R4, use Equation 45. Assume the power stage transconductance, gmps, is 10.5A/V. The output voltage, Vo, reference voltage, VREF, and amplifier transconductance, gmea, are 3.3V, 0.8V and 310 mA/V, respectively. R4 is calculated to be 20.
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TPS54260 www.ti.com SLVSA86A – MARCH 2010 – REVISED DECEMBER 2010 Vout = 20 mV / div (ac coupled) Vout = 20 mV / div (ac coupled) PH = 5 V / div PH = 5 V / div Time = 2 usec / div Time = 2 usec / div Figure 52. Output Ripple CCM Figure 53. Output Ripple, DCM Vin = 200 mV / div (ac coupled) Vout = 20 mV / div (ac coupled) PH = 5 V / div PH = 5 V / div Time = 2 usec / div Time = 10 usec / div Figure 54. Output Ripple, PSM Figure 55.
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TPS54260 SLVSA86A – MARCH 2010 – REVISED DECEMBER 2010 www.ti.com 100 60 180 90 40 80 120 Phase 70 60 Gain 50 40 0 0 -20 30 VIN=12V VOUT=3.3V fsw=300kHz 20 -60 VIN=12 V VOUT=3.3V IOUT=2.5A -40 10 0 0.001 0.1 0.01 IO - Output Current - A -60 10 100 -120 1-104 1-103 f - Frequency - Hz 3.4 3.38 3.38 3.36 3.34 3.32 3.36 3.34 VIN=12V VOUT=3.3V fsw=300kHz IOUT=1.5A 3.32 VIN=12V VOUT=3.3V fsw=300kHz 3.3 0 0.5 1.5 1.0 2.0 IO - Output Current - A 2.5 Figure 60.
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TPS54260 www.ti.com SLVSA86A – MARCH 2010 – REVISED DECEMBER 2010 Power Dissipation Estimate The following formulas show how to estimate the IC power dissipation under continuous conduction mode (CCM) operation. These equations should not be used if the device is working in discontinuous conduction mode (DCM). The power dissipation of the IC includes conduction loss (Pcon), switching loss (Psw), gate drive loss (Pgd) and supply current (Pq).
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TPS54260 SLVSA86A – MARCH 2010 – REVISED DECEMBER 2010 www.ti.com Layout Layout is a critical portion of good power supply design. There are several signals paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help eliminate these problems, the VIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor with X5R or X7R dielectric.
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TPS54260 www.ti.com SLVSA86A – MARCH 2010 – REVISED DECEMBER 2010 VIN + Cin Cboot Lo Cd PH BOOT VIN GND R1 + GND Co R2 TPS54260 VOUT VSENSE EN COMP SS/TR Rcomp RT/CLK Css Czero RT Cpole Figure 63. TPS54260 Inverting Power Supply from SLVA317 Application Note VOPOS + VIN Copos + Cin Cboot BOOT VIN GND PH Lo Cd R1 GND + Coneg R2 TPS54260 VONEG VSENSE EN COMP SS/TR Rcomp RT/CLK Css RT Czero Cpole Figure 64.
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TPS54260 SLVSA86A – MARCH 2010 – REVISED DECEMBER 2010 www.ti.com Figure 65. 12V to 3.8V GSM Power Supply Figure 66. 24V to 4.
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TPS54260 www.ti.com SLVSA86A – MARCH 2010 – REVISED DECEMBER 2010 Changes from Original (March 2010) to Revision A Page • Added 10-Pin 3mm x 3mm SON to Features ....................................................................................................................... 1 • Added 10-pin 3mm x 3mm SON package to DESCRIPTION .............................................................................................. 1 • Added second row to the ORDERING INFORMATION table ..................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 31-Oct-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS54260DGQR MSOPPower PAD DGQ 10 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 TPS54260DRCR SON DRC 10 3000 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2 TPS54260DRCT SON DRC 10 250 180.0 12.4 3.3 3.3 1.0 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS54260DGQR MSOP-PowerPAD DGQ 10 2500 346.0 346.0 35.0 TPS54260DRCR SON DRC 10 3000 346.0 346.0 35.0 TPS54260DRCT SON DRC 10 250 203.0 203.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.