Datasheet
TPS54311, TPS54312
TPS54313, TPS54314
TPS54315, TPS54316
SLVS416B − FEBRUARY 2002 − REVISED APRIL 2005
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3
ELECTRICAL CHARACTERISTICS
T
J
= −40°C to 125°C, VIN = 3 V to 6 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE, VIN
VIN input voltage range 3 6 V
f
s
= 350 kHz, FSEL = 0.8 V, RT open 6.2 9.6
Quiescent current
f
s
= 550 kHz,
Phase pin open
FSEL ≥ 2.5 V, RT open,
8.4 12.8
mA
Shutdown, SS/ENA = 0 V 1 1.4
UNDER VOLTAGE LOCK OUT
Start threshold voltage, UVLO 2.95 3
V
Stop threshold voltage, UVLO 2.70 2.80
V
Hysteresis voltage, UVLO 0.14 0.16 V
Rising and falling edge deglitch,
UVLO
(1)
2.5 µs
BIAS VOLTAGE
Output voltage, VBIAS I
(VBIAS)
= 0 2.70 2.80 2.90 V
Output current, VBIAS
(2)
100 µA
OUTPUT VOLTAGE
TPS54311
T
J
= 25°C, VIN = 5 V 0.9 V
TPS54311
3 ≤ VIN ≤ 6 V, 0 ≤ IL ≤ 3 A, −40 ≤ T
J
≤ 125 −2.5% 2.5%
TPS54312
T
J
= 25°C, VIN = 5 V 1.2 V
TPS54312
3 ≤ VIN ≤ 6 V, 0 ≤ IL ≤ 3 A, −40 ≤ T
J
≤ 125 −2.5% 2.5%
TPS54313
T
J
= 25°C, VIN = 5 V 1.5 V
V
Output voltage
TPS54313
3 ≤ VIN ≤ 6 V, 0 ≤ IL ≤ 3 A, −40 ≤ T
J
≤ 125 −2.5% 2.5%
V
O
Output voltage
TPS54314
T
J
= 25°C, VIN = 5 V 1.8 V
TPS54314
3 ≤ VIN ≤ 6 V, 0 ≤ IL ≤ 3 A, −40 ≤ T
J
≤ 125 −2.5% 2.5%
TPS54315
T
J
= 25°C, VIN = 5 V 2.5 V
TPS54315
3 ≤ VIN ≤ 6 V, 0 ≤ IL ≤ 3 A, −40 ≤ T
J
≤ 125 −2.5% 2.5%
TPS54316
T
J
= 25°C, VIN = 5 V 3.3 V
TPS54316
3 ≤ VIN ≤ 6 V, 0 ≤ IL ≤ 3 A, −40 ≤ T
J
≤ 125 −2.5% 2.5%
REGULATION
Line regulation
(1)
(3)
I
L
= 1.5 A, 350 ≤ f
s
≤ 550 kHz, T
J
= 85°C 0.21 %/V
Load regulation
(1)
(3)
I
L
= 0 A to 3 A, 350 ≤ f
s
≤ 550 kHz, T
J
= 85°C 0.21 %/A
OSCILLATOR
Internall
y
set free-runnin
g
frequenc
y
FSEL ≤ 0.8 V, RT open 280 350 420
kHz
Internally set free running frequency
range
FSEL ≥ 2.5 V, RT open 440 550 660
kHz
Externally set free running frequency
RT = 180 kΩ (1% resistor to AGND)
(1)
252 280 308
Externally set free-running frequency
range
RT = 100 kΩ (1% resistor to AGND) 460 500 540
kHz
range
RT = 68 kΩ (1% resistor to AGND)
(1)
663 700 762
kHz
High-level threshold voltage at FSEL 2.5 V
Low-level threshold voltage at FSEL 0.8 V
Ramp valley
(1)
0.75 V
Ramp amplitude (peak-to-peak)
(1)
1 V
Minimum controllable on time
(1)
200 ns
Maximum duty cycle 90%
(1)
Specified by design
(2)
Static resistive loads only
(3)
Specified by the circuit used in Figure 10.