Datasheet

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VIN

POWERPAD

BOOT

VSENSE

COMP

TPS54318

RT /CLK

PWRGD

BOOT

VOUT

VIN

AGND

GND

100

0 0.5 1 1.5 2 2.5 3

I -OutputCurrent- A

Efficiency-%

V =5V,

V =1.8V,

F =1000kHz

TPS54318

www.ti.com

SLVS975A –SEPTEMBER 2009–REVISED SEPTEMBER 2013

2.95-V To 6-V Input, 3-A Output, 2-MHz, Synchronous Step-Down

Switcher With Integrated FETs ( SWIFT™)

Check for Samples: TPS54318

FEATURES

DESCRIPTION

The TPS54318 device is a full featured 6-V, 3-A,

• Two 30-mΩ (typical) MOSFETs for High

synchronous step-down current-mode converter with

Efficiency at 3-A loads

two integrated MOSFETs.

• 200-kHz to 2-MHz Switching Frequency

The TPS54318 enables small designs by integrating

• 0.8-V ± 1% Voltage Reference Over

the MOSFETs, implementing current mode control to

temperature

reduce external component count, reducing inductor

• Synchronizes to External Clock

size by enabling up to 2- MHz switching frequency,

and minimizing the IC footprint with a small 3-mm x

• Adjustable Slow Start and Sequencing

3-mm thermally enhanced WQFN package.

• UV and OV Power-Good Output

The TPS54318 provides accurate regulation for a

• Low Operating and Shutdown Quiescent

variety of loads with an accurate ±1% Voltage

Current

Reference (V

ref

) over temperature.

• Safe Start-up into Pre-Biased Output

Efficiency is maximized through the integrated 30-mΩ

• Cycle by Cycle Current Limit, Thermal and

MOSFETs and 350-μA typical supply current. Using

Frequency Foldback Protection

the enable pin, shutdown supply current is reduced to

• –40°C to 150°C Operating Junction

2 μA by entering a shutdown mode.

Temperature Range

Undervoltage lockout is internally set at 2.6 V, but

• Thermally Enhanced 3-mm × 3-mm 16-pin

can be increased by programming the threshold with

WQFN

a resistor network on the enable pin. The output

voltage startup ramp is controlled by the slow-start

APPLICATIONS

pin. An open drain power-good signal indicates the

output is within 93% to 107% of its nominal voltage.

• Low-Voltage, High-Density Power Systems

Frequency foldback and thermal shutdown protects

• Point of Load Regulation for High Performance

the device during an overcurrent condition.

DSPs, FPGAs, ASICs and Microprocessors

• Broadband, Networking and Optical

The TPS54318 is supported in the SwitcherPro™

Software Tool at www.ti.com/tool/switcherpro.

Communications Infrastructure

For more SWIFT

documentation, see the TI

SIMPLIFIED SCHEMATIC

website at www.ti.com/swift.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2SWIFT, SwitcherPro, PowerPAD are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (38 pages)

PAGE 1
TPS54318 www.ti.com SLVS975A – SEPTEMBER 2009 – REVISED SEPTEMBER 2013 2.95-V To 6-V Input, 3-A Output, 2-MHz, Synchronous Step-Down Switcher With Integrated FETs ( SWIFT™) Check for Samples: TPS54318 FEATURES DESCRIPTION • The TPS54318 device is a full featured 6-V, 3-A, synchronous step-down current-mode converter with two integrated MOSFETs. 1 2 • • • • • • • • • • Two 30-mΩ (typical) MOSFETs for High Efficiency at 3-A loads 200-kHz to 2-MHz Switching Frequency 0.
PAGE 2
TPS54318 SLVS975A – SEPTEMBER 2009 – REVISED SEPTEMBER 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
PAGE 3
TPS54318 www.ti.com SLVS975A – SEPTEMBER 2009 – REVISED SEPTEMBER 2013 ELECTRICAL CHARACTERISTICS TJ = –40°C to 150°C, VIN = 2.95 to 6 V (unless otherwise noted) DESCRIPTION CONDITIONS MIN TYP MAX UNIT 2.6 2.8 V 2 5 μA 350 500 μA 1.25 1.37 V SUPPLY VOLTAGE (VIN PIN) Operating input voltage 2.95 Internal under voltage lockout threshold No voltage hysteresis, rising and falling Shutdown supply current EN = 0 V, 25°C, 2.95 V ≤ VIN ≤ 6 V Quiescent Current - Iq VSENSE = 0.
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TPS54318 SLVS975A – SEPTEMBER 2009 – REVISED SEPTEMBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) TJ = –40°C to 150°C, VIN = 2.95 to 6 V (unless otherwise noted) DESCRIPTION CONDITIONS MIN TYP MAX UNIT BOOT (BOOT PIN) BOOT Charge Resistance VIN = 5 V 16 Ω BOOT-PH UVLO VIN = 2.95 V 2.1 V Charge Current V(SS) = 0.4 V 1.8 μA SS to reference crossover 98% nominal 0.
PAGE 5
TPS54318 www.ti.com SLVS975A – SEPTEMBER 2009 – REVISED SEPTEMBER 2013 PIN CONFIGURATION 2 GND 3 GND 4 EN PWRGD BOOT 14 13 Thermal Pad (17) AGND 5 6 7 8 RT/CLK VIN 15 COMP 1 16 VSENSE VIN VIN WQFN-16 RTE PACKAGE (TOP VIEW) 12 PH 11 PH 10 PH 9 SS PIN FUNCTIONS PIN DESCRIPTION NAME NO. AGND 5 Analog Ground should be electrically connected to GND close to the device. BOOT 13 A bootstrap capacitor is required between BOOT and PH.
PAGE 6
TPS54318 SLVS975A – SEPTEMBER 2009 – REVISED SEPTEMBER 2013 www.ti.
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TPS54318 www.ti.com SLVS975A – SEPTEMBER 2009 – REVISED SEPTEMBER 2013 TYPICAL CHARACTERISTICS CURVES FREQUENCY vs TEMPERATURE 550 High Side Rdson VI = 3.3 V Low Side Rdson VI = 3.3 V 0.05 0.045 540 fs - Switching Frequency - kHz RDSON - Static Drain-Source On-State Resistance - W HIGH-SIDE AND LOW-SIDE RDS(on) vs TEMPERATURE 0.055 High Side Rdson VI = 5 V 0.04 0.035 Low Side Rdson VI = 5 V 0.03 RT = 400 kW, VI = 3.3 V 530 520 510 500 490 480 470 0.025 460 0.
PAGE 8
TPS54318 SLVS975A – SEPTEMBER 2009 – REVISED SEPTEMBER 2013 www.ti.com TYPICAL CHARACTERISTICS CURVES (continued) SWITCHING FREQUENCY vs VSENSE TRANSCONDUCTANCE vs TEMPERATURE 100 280 VIN = 3 .3 V 260 EA - Transconductance - mA/V Normal Switching Frequency - % Vsense Falling 75 Vsense Rising 50 25 240 220 200 180 160 0 0 0.1 0.2 0.3 0.4 0.5 Vsense - V 0.6 0.7 140 -50 0.8 -25 0 25 50 75 100 TJ - Junction Temperature - °C Figure 7. 150 Figure 8.
PAGE 9
TPS54318 www.ti.com SLVS975A – SEPTEMBER 2009 – REVISED SEPTEMBER 2013 TYPICAL CHARACTERISTICS CURVES (continued) CHARGE CURRENT vs TEMPERATURE DISCHARGE CURRENT vs TEMPERATURE -1 105 -1.2 103 SS/TR - Discharge Current - mA SS/TR - Charge Current - mA -1.4 VIN = 5 V -1.6 -1.8 -2 -2.2 -2.4 -2.6 -2.8 101 VIN = 5 V 99 97 95 93 91 89 87 -3 -50 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 85 -50 150 -25 0 25 50 75 100 TJ - Junction Temperature - °C Figure 13. 150 Figure 14.
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TPS54318 SLVS975A – SEPTEMBER 2009 – REVISED SEPTEMBER 2013 www.ti.com TYPICAL CHARACTERISTICS CURVES (continued) SUPPLY CURRENT vs INPUT VOLTAGE PWRGD THRESHOLD vs TEMPERATURE 110 400 390 108 380 106 PWRGD - Threshold - % Vref ICC - Supply Current - mA TJ = 25°C 370 360 350 340 330 Vsense Rising, VIN = 3.3 V Vsense Falling 104 102 100 98 96 94 320 Vsense Rising 92 310 90 300 88 -50 3 3.5 4 4.5 5 VIN - Input Voltage - V 5.5 6 Vsense Falling -25 0 Figure 19.
PAGE 11
TPS54318 www.ti.com SLVS975A – SEPTEMBER 2009 – REVISED SEPTEMBER 2013 The TPS54318 reduces the external component count by integrating the boot recharge diode. The bias voltage for the integrated high-side MOSFET is supplied by a capacitor on the BOOT to PH pin. The boot capacitor voltage is monitored by an UVLO circuit and turns off the high-side MOSFET when the voltage falls below a preset threshold. This BOOT circuit allows the TPS54318 to operate approaching 100%.
PAGE 12
TPS54318 SLVS975A – SEPTEMBER 2009 – REVISED SEPTEMBER 2013 www.ti.com VOLTAGE REFERENCE The voltage reference system produces a precise ±1% voltage reference overtemperature by scaling the output of a temperature stable bandgap circuit. The bandgap and scaling circuits produce 0.8 V at the non-inverting input of the error amplifier. ADJUSTING THE OUTPUT VOLTAGE The output voltage is set with a resistor divider from the output node to the VSENSE pin.
PAGE 13
TPS54318 www.ti.com R2 = SLVS975A – SEPTEMBER 2009 – REVISED SEPTEMBER 2013 1.18 × R1 VSTOP - 1.18 + R1 × 3.2 ´ 10 - 6 (3) SLOW-START PIN The TPS54318 regulates to the lower of the SS pin and the internal reference voltage. A capacitor on the SS pin to ground implements a slow-start time. The TPS54318 has an internal pullup current source of 1.8 μA which charges the external slow-start capacitor.
PAGE 14
TPS54318 SLVS975A – SEPTEMBER 2009 – REVISED SEPTEMBER 2013 www.ti.com TPS54318 EN1 = 2 V / div EN SS Vout1 = 1 V / div PWRGD Vout2 = 1 V / div TPS54318 EN Time = 5 msec / div SS PWRGD Figure 27. Schematic for Ratiometric Startup Sequence Figure 28.
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TPS54318 www.ti.com SLVS975A – SEPTEMBER 2009 – REVISED SEPTEMBER 2013 REVERSE OVERCURRENT PROTECTION The TPS54318 implements low-side current protection by detecting the voltage across the low-side MOSFET. When the converter sinks current through its low-side FET, the control circuit turns off the low-side MOSFET if the reverse current is more than 1.3 A.
PAGE 16
TPS54318 SLVS975A – SEPTEMBER 2009 – REVISED SEPTEMBER 2013 www.ti.com SMALL-SIGNAL MODEL FOR LOOP RESPONSE Figure 31 shows an equivalent model for the TPS54318 control loop which can be modeled in a circuit simulation program to check frequency response and dynamic load response. The error amplifier is a transconductance amplifier with a gm of 225 μA/V. The error amplifier is modeled using an ideal voltage controlled current source.
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TPS54318 www.ti.com SLVS975A – SEPTEMBER 2009 – REVISED SEPTEMBER 2013 æ ç 1+ vo è 2p = Adc ´ vc æ ç 1+ è 2p ö s ÷ × ¦z ø ö s ÷ × ¦p ø (7) Adc = gmps ´ RL ¦p = ¦z = (8) C OUT 1 ´ RL ´ 2p COUT 1 ´ RESR ´ 2p (9) (10) SMALL SIGNAL MODEL FOR FREQUENCY COMPENSATION The TPS54318 uses a transconductance amplifier for the error amplifier and readily supports two of the commonly used frequency compensation circuits. The compensation circuits are shown in Figure 33.
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TPS54318 SLVS975A – SEPTEMBER 2009 – REVISED SEPTEMBER 2013 www.ti.com The design guidelines for TPS54318 loop compensation are as follows: 1. The modulator pole, fpmod, and the ESR zero, fz1 must be calculated using Equation 11 and Equation 12. Derating the output capacitor (COUT) is required if the output voltage is a high percentage of the capacitor rating. Use the capacitor manufacturer information to derate the capacitor value.
PAGE 19
TPS54318 www.ti.com SLVS975A – SEPTEMBER 2009 – REVISED SEPTEMBER 2013 APPLICATION INFORMATION DESIGN GUIDE – STEP-BY-STEP DESIGN PROCEDURE This example details the design of a high frequency switching regulator design using ceramic output capacitors. This design is available as the HPA512 evaluation module (EVM). A few parameters must be known in order to start the design process. These parameters are typically determined on the system level.
PAGE 20
TPS54318 SLVS975A – SEPTEMBER 2009 – REVISED SEPTEMBER 2013 www.ti.com For this design example, use KIND = 0.3 and the inductor value is calculated to be 1.4 μH. For this design, a nearest standard value was chosen: 1.5 μH. For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded. The RMS and peak inductor current is found from Equation 20 and Equation 21. For this design, the RMS inductor current is 3.01 A and the peak inductor current is 3.42 A.
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TPS54318 www.ti.com SLVS975A – SEPTEMBER 2009 – REVISED SEPTEMBER 2013 2 ´ DIOUT ¦ sw ´ DVOUT COUT > (22) 1 1 ´ > VOripple 8 ´ ¦ sw Iripple COUT where • • • ΔIOUT is the change in output current, ƒsw is the regulators switching frequency ΔVOUT is the allowable change in the output voltage (23) Equation 24 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple specification. Equation 24 indicates the ESR should be less than 39 mΩ.
PAGE 22
TPS54318 SLVS975A – SEPTEMBER 2009 – REVISED SEPTEMBER 2013 www.ti.com COMP VOLTAGE LEVEL The TPS54318 implements a minimum COMP voltage clamp for improved load transient response. The COMP voltage tracks the peak inductor current, increasing as the peak inductor current increases, and decreasing as the peak inductor current decreases.
PAGE 23
TPS54318 www.ti.com SLVS975A – SEPTEMBER 2009 – REVISED SEPTEMBER 2013 OUTPUT VOLTAGE AND FEEDBACK RESISTORS SELECTION For the example design, 100 kΩ was selected for R6. Using Equation 31, R7 is calculated as 80 kΩ. The nearest standard 1% resistor is 80.5 kΩ. Vref R7 = R6 VOUT - Vref (31) Due to the internal design of the TPS54318, there is a minimum output voltage limit for any given input voltage. The output voltage can never be lower than the internal voltage reference of 0.8 V. Above 0.
PAGE 24
TPS54318 SLVS975A – SEPTEMBER 2009 – REVISED SEPTEMBER 2013 ¦ z mod = www.ti.com 1 2p ´ RESR ´ COUT ¦C = ¦p mod ´ ¦ z mod ¦C = ¦p mod ´ (35) (36) ¦ sw 2 (37) The compensation design takes the following steps: 1. Set up the anticipated cross-over frequency. Use Equation 38 to calculate the compensation network’s resistor value. In this example, the anticipated cross-over frequency (fc) is 45 kHz. The power stage gain (gmps) is 13 A/V and the error amplifier gain (gmea) is 225 μA/V.
PAGE 25
TPS54318 www.ti.com SLVS975A – SEPTEMBER 2009 – REVISED SEPTEMBER 2013 TRANSIENT RESPONSE, 1.5-A STEP TRANSIENT RESPONSE, 3-A STEP VOUT = 50 mV/div (ac coupled) IOUT = 1 A/div 0.75 to 2.25 A step VOUT = 50 mV/div (ac coupled) IOUT = 1 A/div 0 to 3 A step Time = 2 ms/div Time = 2 ms/div Figure 37. Figure 38.
PAGE 26
TPS54318 SLVS975A – SEPTEMBER 2009 – REVISED SEPTEMBER 2013 www.ti.com OUTPUT RIPPLE, 0 A OUTPUT RIPPLE, 3 A VIN = 50 mV/div (ac coupled) VOUT = 10 mV/div (ac coupled) PH = 2 V/div PH = 2 V/div Time = 500 ns/div Time = 500 ns/div Figure 43. Figure 44. INPUT RIPPLE, 0 A INPUT RIPPLE, 3 A VIN = 50 mV/div VOUT = 10 mV/div (ac coupled) PH = 2 V/div PH = 2 V/div Time = 500 ns/div Time = 500 ns/div Figure 45. Figure 46. LOAD REGULATION vs LOAD CURRENT CLOSED-LOOP RESPONSE, VIN (3.
PAGE 27
TPS54318 www.ti.com SLVS975A – SEPTEMBER 2009 – REVISED SEPTEMBER 2013 LOAD REGULATION vs LOAD CURRENT REGULATION vs INPUT VOLTAGE 1.8 0.25 0.2 1.798 IO = 1.5 A 0.1 VO - Output Voltage - V Output Voltage Change - % 0.15 VI = 5 V 0.05 0 -0.05 -0.1 -0.15 1.796 1.794 1.792 -0.2 1.79 -0.25 0 0.5 1 1.5 2 IO - Output Current - A 2.5 3 3 Figure 49. 3.5 4 4.5 5 VI - Input Voltage - V 5.5 6 Figure 50.
PAGE 28
TPS54318 SLVS975A – SEPTEMBER 2009 – REVISED SEPTEMBER 2013 www.ti.com There are additional power losses in the regulator circuit due to the inductor AC and DC losses and trace resistance that impact the overall efficiency of the regulator. As an example, the maximum ambient temperature versus power dissipation for the EVM is shown in Figure 52. 150 TA = room temperature, no air flow 140 TJ - Junction Temperature - °C 130 120 110 100 90 80 70 60 50 40 30 20 0 0.5 1 1.5 2 2.
PAGE 29
TPS54318 www.ti.com SLVS975A – SEPTEMBER 2009 – REVISED SEPTEMBER 2013 to a separate analog ground trace as shown. The RT/CLK pin is particularly sensitive to noise so the RT resistor should be located as close as possible to the IC and routed with minimal lengths of trace. The additional external components can be placed approximately as shown.
PAGE 30
TPS54318 SLVS975A – SEPTEMBER 2009 – REVISED SEPTEMBER 2013 www.ti.com REVISION HISTORY Changes from Original (September 2009) to Revision A Page • Added MINIMUM COMP VOLTAGE CLAMP vs TEMPERATURE graph to TYPICAL CHARACTERISTICS CURVES .. 10 • Changed FIXED FREQUENCY PWM CONTROL section by adding additional text about COMP voltage ...................... 11 • Added recommended soft-start time range to SLOW START PIN capacitor .....................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PAGE 33
PACKAGE MATERIALS INFORMATION www.ti.com 5-Nov-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS54318RTER WQFN RTE 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS54318RTET WQFN RTE 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.
PAGE 34
PACKAGE MATERIALS INFORMATION www.ti.com 5-Nov-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS54318RTER WQFN RTE 16 3000 367.0 367.0 35.0 TPS54318RTET WQFN RTE 16 250 210.0 185.0 35.
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