Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - DC/DC voltage regulator Holder SO 8

VIN

ENA

GND

VSENSE

BOOT

TPS5430/31

VIN VOUT

100

0 0.5 1 1.5 2.5 3 3.5

Efficiency − %

I OutputCurrent A

EfficiencyvsOutputCurrent

SimplifiedSchematic

=12V

V =5V

f =500kHz

T =25 C

TPS5430

TPS5431

www.ti.com

SLVS632E –JANUARY 2006–REVISED SEPTEMBER 2013

3-A, WIDE INPUT RANGE, STEP-DOWN CONVERTER

Check for Samples: TPS5430 , TPS5431

FEATURES

DESCRIPTION

• Wide Input Voltage Range:

The TPS5430/TPS5431 is a high-output-current

– TPS5430: 5.5 V to 36 V

PWM converter that integrates a low resistance high

– TPS5431: 5.5 V to 23 V

side N-channel MOSFET. Included on the substrate

with the listed features are a high performance

• Up to 3-A Continuous (4-A Peak) Output

voltage error amplifier that provides tight voltage

Current

regulation accuracy under transient conditions; an

• High Efficiency up to 95% Enabled by 110-mΩ

undervoltage-lockout circuit to prevent start-up until

Integrated MOSFET Switch

the input voltage reaches 5.5 V; an internally set

• Wide Output Voltage Range: Adjustable Down

slow-start circuit to limit inrush currents; and a voltage

to 1.22 V with 1.5% Initial Accuracy

feed-forward circuit to improve the transient

response. Using the ENA pin, shutdown supply

• Internal Compensation Minimizes External

current is reduced to 18 μA typically. Other features

Parts Count

include an active-high enable, overcurrent limiting,

• Fixed 500 kHz Switching Frequency for Small

overvoltage protection and thermal shutdown. To

Filter Size

reduce design complexity and external component

count, the TPS5430/TPS5431 feedback loop is

• Improved Line Regulation and Transient

internally compensated. The TPS5431 is intended to

Response by Input Voltage Feed Forward

operate from power rails up to 23 V. The TPS5430

• System Protected by Overcurrent Limiting,

regulates a wide variety of power sources including

Overvoltage Protection and Thermal Shutdown

24-V bus.

• –40°C to 125°C Operating Junction

The TPS5430/TPS5431 device is available in a

Temperature Range

thermally enhanced, easy to use 8-pin SOIC

• Available in Small Thermally Enhanced 8-Pin

PowerPAD™ package. TI provides evaluation

SOIC PowerPAD™ Package

modules and the Designer software tool to aid in

quickly achieving high-performance power supply

designs to meet aggressive equipment development

APPLICATIONS

cycles.

• Consumer: Set-top Box, DVD, LCD Displays

• Industrial and Car Audio Power Supplies

• Battery Chargers, High Power LED Supply

• 12-V/24-V Distributed Power Systems

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (32 pages)

PAGE 1
TPS5430 TPS5431 www.ti.com SLVS632E – JANUARY 2006 – REVISED SEPTEMBER 2013 3-A, WIDE INPUT RANGE, STEP-DOWN CONVERTER Check for Samples: TPS5430 , TPS5431 FEATURES 1 • 2 • • • • • • • • • DESCRIPTION Wide Input Voltage Range: – TPS5430: 5.5 V to 36 V – TPS5431: 5.5 V to 23 V Up to 3-A Continuous (4-A Peak) Output Current High Efficiency up to 95% Enabled by 110-mΩ Integrated MOSFET Switch Wide Output Voltage Range: Adjustable Down to 1.22 V with 1.
PAGE 2
TPS5430 TPS5431 SLVS632E – JANUARY 2006 – REVISED SEPTEMBER 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION TJ INPUT VOLTAGE OUTPUT VOLTAGE PACKAGE (1) PART NUMBER –40°C to 125°C 5.5 V to 36 V Adjustable to 1.22 V Thermally Enhanced SOIC (DDA) (2) TPS5430DDA –40°C to 125°C 5.
PAGE 3
TPS5430 TPS5431 www.ti.com SLVS632E – JANUARY 2006 – REVISED SEPTEMBER 2013 THERMAL INFORMATION TPS5430 TPS5431 THERMAL METRIC (1) (2) (3) UNITS DDA (8 PINS) θJA Junction-to-ambient thermal resistance (2-layer custom board) (4) 33 θJA Junction-to-ambient thermal resistance (4-layer custom board) (5) 26 θJA Junction-to-ambient thermal resistance (standard board) ψJT Junction-to-top characterization parameter 4.9 ψJB Junction-to-board characterization parameter 20.
PAGE 4
TPS5430 TPS5431 SLVS632E – JANUARY 2006 – REVISED SEPTEMBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS TJ = –40°C to 125°C, VIN = 12 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 3 4.4 mA 18 50 μA Start threshold voltage, UVLO 5.3 5.5 Hysteresis voltage, UVLO 330 SUPPLY VOLTAGE (VIN PIN) IQ Quiescent current VSENSE = 2 V, Not switching, PH pin open Shutdown, ENA = 0 V UNDERVOLTAGE LOCK OUT (UVLO) V mV VOLTAGE REFERENCE Voltage reference accuracy TJ = 25°C 1.
PAGE 5
TPS5430 TPS5431 www.ti.com SLVS632E – JANUARY 2006 – REVISED SEPTEMBER 2013 PIN ASSIGNMENTS DDA PACKAGE (TOP VIEW) 8 PH 7 VIN 3 6 GND 4 5 ENA BOOT 1 NC 2 NC VSENSE PowerPAD (Pin 9) TERMINAL FUNCTIONS TERMINAL NAME BOOT NC DESCRIPTION NO. 1 2, 3 Boost capacitor for the high-side FET gate driver. Connect 0.01 μF low ESR capacitor from BOOT pin to PH pin. Not connected internally. VSENSE 4 Feedback voltage for the regulator. Connect to output voltage divider. ENA 5 On/off control.
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TPS5430 TPS5431 SLVS632E – JANUARY 2006 – REVISED SEPTEMBER 2013 www.ti.com TYPICAL CHARACTERISTICS OSCILLATOR FREQUENCY vs JUNCTION TEMPERATURE NON-SWITCHING QUIESCENT CURRENT vs JUNCTION TEMPERATURE 530 3.5 VI = 12 V I Q−Quiescent Current −mA f − Oscillator Frequency − kHz 520 510 500 490 480 3.25 3 2.75 470 460 −50 −25 0 25 50 75 100 2.5 −50 125 −25 50 75 100 Figure 2.
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TPS5430 TPS5431 www.ti.com SLVS632E – JANUARY 2006 – REVISED SEPTEMBER 2013 TYPICAL CHARACTERISTICS (continued) MINIMUM CONTROLLABLE ON TIME vs JUNCTION TEMPERATURE MINIMUM CONTROLLABLE DUTY RATIO vs JUNCTION TEMPERATURE 8 170 7.75 Minimum Duty Ratio - % Minimum Controllable On Time − ns 180 160 150 140 7.50 7.25 130 120 −50 −25 0 25 50 75 100 TJ − Junction Temperature − °C 125 7 -50 Figure 7. -25 50 0 25 75 100 TJ - Junction Temperature - °C 125 Figure 8.
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TPS5430 TPS5431 SLVS632E – JANUARY 2006 – REVISED SEPTEMBER 2013 www.ti.com APPLICATION INFORMATION FUNCTIONAL BLOCK DIAGRAM VIN VIN 1.221 V Bandgap Reference UVLO VREF SHDN Slow Start Boot Regulator BOOT HICCUP 5 µA ENABLE ENA SHDN SHDN VSENSE Z1 Thermal Protection SHDN NC VIN Ramp Generator NC SHDN VSENSE PWM Comparator HICCUP Overcurrent Protection Oscillator OVP Z2 Feed Forward Gain = 25 SHDN GND POWERPAD Error Amplifier SHDN SHDN Gate Drive Control 112.
PAGE 9
TPS5430 TPS5431 www.ti.com SLVS632E – JANUARY 2006 – REVISED SEPTEMBER 2013 Undervoltage Lockout (UVLO) The TPS5430/TPS5431 incorporates an undervoltage lockout circuit to keep the device disabled when VIN (the input voltage) is below the UVLO start voltage threshold. During power up, internal circuits are held inactive and the internal slow start is grouded until VIN exceeds the UVLO start threshold voltage.
PAGE 10
TPS5430 TPS5431 SLVS632E – JANUARY 2006 – REVISED SEPTEMBER 2013 www.ti.com Overvoltage Protection The TPS5430/TPS5431 has an overvoltage protection (OVP) circuit to minimize voltage overshoot when recovering from output fault conditions. The OVP circuit includes an overvoltage comparator to compare the VSENSE pin voltage and a threshold of 112.5% x VREF. Once the VSENSE pin voltage is higher than the threshold, the high-side MOSFET will be forced off.
PAGE 11
TPS5430 TPS5431 www.ti.com SLVS632E – JANUARY 2006 – REVISED SEPTEMBER 2013 PH BOOT CAPACITOR OUTPUT INDUCTOR RESISTOR DIVIDER VOUT CATCH DIODE BOOT PH NC VIN NC GND VSENSE ENA OUTPUT FILTER CAPACITOR INPUT INPUT BYPASS BULK CAPACITOR FILTER Vin TOPSIDE GROUND AREA VIA to Ground Plane Route feedback trace under output filter capacitor or on other layer Signal VIA Figure 9.
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TPS5430 TPS5431 SLVS632E – JANUARY 2006 – REVISED SEPTEMBER 2013 www.ti.com 0.110 0.220 0.026 0.118 0.050 0.050 0.080 0.013 DIA 4 PL 0.040 0.098 All dimensions in inches Figure 10. TPS5430 Land Pattern Application Circuits Figure 11 shows the schematic for a typical TPS5430 application. The TPS5430 can provide up to 3-A output current at a nominal output voltage of 5 V. For proper thermal performance, the exposed PowerPAD™ underneath the device must be soldered down to the printed-circuit board.
PAGE 13
TPS5430 TPS5431 www.ti.com • • • • • SLVS632E – JANUARY 2006 – REVISED SEPTEMBER 2013 Output voltage Input ripple voltage Output ripple voltage Output current rating Operating frequency Design Parameters For this design example, use the following as the input parameters: (1) DESIGN PARAMETER (1) EXAMPLE VALUE Input voltage range 10.8 V to 19.
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TPS5430 TPS5431 SLVS632E – JANUARY 2006 – REVISED SEPTEMBER 2013 www.ti.com Inductor Selection To calculate the minimum value of the output inductor, use Equation 4: V L MIN + ǒ V * V OUT(MAX) IN(MAX) OUT V K I F IN(max) IND OUT SW Ǔ (4) KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current.
PAGE 15
TPS5430 TPS5431 www.ti.com ESR MAX + SLVS632E – JANUARY 2006 – REVISED SEPTEMBER 2013 1 C OUT 2p f CO (9) The maximum ESR of the output capacitor also determines the amount of output ripple as specified in the initial design parameters. The output ripple voltage is the inductor ripple current times the ESR of the output filter.
PAGE 16
TPS5430 TPS5431 SLVS632E – JANUARY 2006 – REVISED SEPTEMBER 2013 www.ti.com Catch Diode The TPS5430 is designed to operate using an external catch diode between PH and GND. The selected diode must meet the absolute maximum ratings for the application: Reverse voltage must be higher than the maximum voltage at the PH pin, which is VINMAX + 0.5 V. Peak current must be greater than IOUTMAX plus on half the peak to peak inductor current. Forward voltage drop should be small for higher efficiencies.
PAGE 17
TPS5430 TPS5431 www.ti.com SLVS632E – JANUARY 2006 – REVISED SEPTEMBER 2013 U1 TPS5430DDA VIN 10-24 V VIN C1 4.7 mF EN 7 VIN 1 BOOT 5 ENA 2 8 PH NC 3 4 NC VSNS 6 GND PwPd 9 C2 0.01 mF L1 15 mH 3.3 V VOUT D1 MRBS340 R1 10 kW C7 0.1 mF C4 150 pF R3 549 W C3 100 mF R2 5.9 kW C6 1500 pF Figure 14. Ceramic Output Filter Capacitors Circuit Output Filter Component Selection Using Equation 11, the minimum inductor value is 12 μH. A value of 15 μH is chosen for this design.
PAGE 18
TPS5430 TPS5431 SLVS632E – JANUARY 2006 – REVISED SEPTEMBER 2013 www.ti.com Fz2 = 2.5 x FLC (17) The final pole is located at a frequency too high to be of concern. The second zero, Fz2 as defined by Equation 17 uses 2.5 for the frequency multiplier. In some cases this may need to be slightly higher or lower. Values in the range of 2.3 to 2.7 work well. The values for R1 and R2 are fixed by the 3.3-V output voltage as calculated usingEquation 12. For this design R1 = 10 kΩ and R2 = 5.90 kΩ.
PAGE 19
TPS5430 TPS5431 www.ti.com SLVS632E – JANUARY 2006 – REVISED SEPTEMBER 2013 Internal Compensation Network The design equations given in the example circuit can be used to generate circuits using the TPS5430/TPS5431. These designs are based on certain assumptions and will tend to always select output capacitors within a limited range of ESR values. If a different capacitor type is desired, it may be possible to fit one to the internal compensation of the TPS5430/TPS5431.
PAGE 20
TPS5430 TPS5431 SLVS632E – JANUARY 2006 – REVISED SEPTEMBER 2013 www.ti.com PERFORMANCE GRAPHS The performance graphs (Figure 15 through Figure 21) are applicable to the circuit in Figure 11. Ta = 25 °C. unless otherwise specified. 0.3 100 VI = 10.8 V 95 0.2 VI = 12 V Output Regulation - % Efficiency - % VI = 15 V 90 VI = 18 V 85 VI = 19.8 V 80 0.1 0 -0.1 -0.2 -0.3 75 0 0.5 1 1.5 2 2.5 IO - Output Current - A 3 3.5 Figure 15. Efficiency vs. Output Current 0 0.5 1 2 1.5 2.
PAGE 21
TPS5430 TPS5431 www.ti.com SLVS632E – JANUARY 2006 – REVISED SEPTEMBER 2013 VOUT = 20 mV/Div (AC Coupled) VOUT = 50 mV/Div (AC Coupled) PH = 5 V/Div IOUT = 1 A /Div t - Time = 200 μs/Div t - Time = 500 ns/Div Figure 19. Output Voltage Ripple and PH Node, IO = 3 A Figure 20. Transient Response, IO Step 0.75 to 2.25 A. VIN = 5 V/Div VOUT = 2 V/Div t - Time = 2 ms/Div Figure 21. Startup Waveform, VIN and VOUT.
PAGE 22
TPS5430 TPS5431 SLVS632E – JANUARY 2006 – REVISED SEPTEMBER 2013 www.ti.com REVISION HISTORY Changes from Original (January 2006) to Revision A Page • Added device number TPS5431 ........................................................................................................................................... 1 • Changed Figure 12 .............................................................................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com (4) 22-Jan-2014 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
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PACKAGE MATERIALS INFORMATION www.ti.com 5-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS5430DDAR SO Power PAD DDA 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TPS5431DDAR SO Power PAD DDA 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 5-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS5430DDAR SO PowerPAD DDA 8 2500 367.0 367.0 35.0 TPS5431DDAR SO PowerPAD DDA 8 2500 367.0 367.0 35.
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