Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - DC/DC voltage regulator Holder QFN 14

100

0 0.5 1 1.5 2 2.5 3

Load Current - A

Efficiency - %

VOUT = 5 V

VOUT = 3.3 V

VOUT = 1.8 V

VIN = 12 V,

Fsw = 500 kHz

PVIN

GND

BOOT

VSENSE

COMP

TPS54320

RT/CLK

SS/TR

Exposed

Thermal

Pad

Css

Rrt

Cboot

Cin

VIN

VOUT

PWRGD

TPS54320

www.ti.com

SLVS982A –AUGUST 2010–REVISED SEPTEMBER 2010

4.5V to 17V Input, 3A Synchronous Step Down SWIFT™ Converter

Check for Samples: TPS54320

FEATURES

• Power Good Output for Undervoltage and

Overvoltage Monitoring

• Integrated 57mΩ / 50mΩ MOSFETs

• Adjustable Input Undervoltage Lockout

• Split Power Rail: 1.6V to 17V on PVIN

• Supported by SwitcherPro ™Software Tool

• 200kHz to 1.2MHz Switching Frequency

• For SWIFT™ Documentation and

• Synchronizes to External Clock

SwitcherPro™, visit http://www.ti.com/swift

• 0.8V Voltage Reference With ±1% Accuracy

• Low 2µA Shutdown Quiescent Current

APPLICATIONS

• Hiccup Overcurrent Protection

• Broadband, Networking & Communication

• Monotonic Start-Up into Prebiased Outputs

Infrastructure

• Automated Test and Medical Equipment

• –40°C to 150°C Operating Junction

Temperature Range

• DSP and FPGA Point-of-Load Applications

from 12-V Bus

• Pin-to-Pin Compatible with the TPS54620

• Adjustable Slow Start/Power Sequencing

DESCRIPTION

The TPS54320 is a full featured 17V, 3A synchronous step down converter which is optimized for small designs

through high efficiency and integrated high-side and low-side MOSFETs. Further space savings are achieved

through current mode control, which reduces component count, and by selecting a high switching frequency,

reducing the inductor's footprint.

The output voltage startup ramp is controlled by the SS/TR pin which allows operation as either a stand alone

power supply or in tracking situations. Power sequencing is also possible by correctly configuring the enable and

the open drain power good pins.

Cycle by cycle current limiting on the high-side FET protects the device in overload situations and is enhanced

by a low-side sourcing current limit which prevents current runaway. Hiccup protection will be triggered if the

overcurrent condition has persisted for longer than the preset time. Thermal shutdown disables the part when die

temperature exceeds thermal shutdown temperature. The TPS54320 is available in a 14 pin, 3.5mm x 3.5mm

QFN, thermally enhanced package.

WHITE SPACE

SIMPLIFIED SCHEMATIC

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2SwitcherPro, SWIFT are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (39 pages)

PAGE 1
TPS54320 www.ti.com SLVS982A – AUGUST 2010 – REVISED SEPTEMBER 2010 4.5V to 17V Input, 3A Synchronous Step Down SWIFT™ Converter Check for Samples: TPS54320 FEATURES • 1 • • • • • • • • • 2 • • Integrated 57mΩ / 50mΩ MOSFETs Split Power Rail: 1.6V to 17V on PVIN 200kHz to 1.2MHz Switching Frequency Synchronizes to External Clock 0.
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TPS54320 SLVS982A – AUGUST 2010 – REVISED SEPTEMBER 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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TPS54320 www.ti.com SLVS982A – AUGUST 2010 – REVISED SEPTEMBER 2010 THERMAL INFORMATION TPS54320 THERMAL METRIC (1) (2) QFN UNITS 14 PINS Junction-to-ambient thermal resistance qJA 47.2 (3) qJA Junction-to-ambient thermal resistance qJCtop Junction-to-case (top) thermal resistance 64.8 qJB Junction-to-board thermal resistance 14.4 yJT Junction-to-top characterization parameter 0.5 yJB Junction-to-board characterization parameter 14.
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TPS54320 SLVS982A – AUGUST 2010 – REVISED SEPTEMBER 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) TJ= –40°C to 150°C, VIN = 4.5V to 17V, PVIN = 1.6V to 17V (unless otherwise noted) DESCRIPTION CONDITIONS MIN TYP MAX UNIT ERROR AMPLIFIER Error amplifier Transconductance (gm) –2 mA < I(COMP) < 2 mA, V(COMP) = 1 V Error amplifier dc gain VSENSE = 0.
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TPS54320 www.ti.com SLVS982A – AUGUST 2010 – REVISED SEPTEMBER 2010 DEVICE INFORMATION PIN ASSIGNMENTS RT/CLK 1 PWRGD 14 GND 2 13 BOOT GND 3 PVIN 4 PVIN 5 12 PH Exposed Thermal Pad (15) VIN 6 11 PH 10 EN 9 SS/TR 7 VSENSE 8 COMP PIN FUNCTIONS PIN NAME RT/CLK DESCRIPTION No. 1 Automatically selects between RT mode and CLK mode. An external timing resistor adjusts the switching frequency of the device; In CLK mode, the device synchronizes to an external clock.
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TPS54320 SLVS982A – AUGUST 2010 – REVISED SEPTEMBER 2010 www.ti.
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TPS54320 www.ti.com SLVS982A – AUGUST 2010 – REVISED SEPTEMBER 2010 TYPICAL CHARACTERISTICS HIGH-SIDE Rdson vs TEMPERATURE LOW-SIDE Rdson vs TEMPERATURE 75 90 VI = 12 V VI = 12 V RDS(on) - On Resistance - mW RDS(on) - On Resistance - mW 80 70 60 50 40 -50 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 65 55 45 35 -50 150 -25 0 Figure 1. 25 50 75 100 TJ - Junction Temperature - °C 125 150 Figure 2.
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TPS54320 SLVS982A – AUGUST 2010 – REVISED SEPTEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) EN PIN PULL-UP CURRENT vs TEMPERATURE EN PIN UVLO THRESHOLD vs TEMPERATURE 1.2 1.24 VI = 12 V VI = 12 V, EN = 1.1 V EN - UVLO Threshold - V 1.1 1.05 Non - Switching Operating Quiescent Current - mA 1 -50 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 1.23 1.22 1.21 1.2 -50 150 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 Figure 7. Figure 8.
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TPS54320 www.ti.com SLVS982A – AUGUST 2010 – REVISED SEPTEMBER 2010 TYPICAL CHARACTERISTICS (continued) HIGH-SIDE CURRENT LIMIT THRESHOLD vs INPUT VOLTAGE MINIMUM CONTROLLABLE ON TIME vs TEMPERATURE 120 7 TJ = 150°C TJ = 25°C Minimum Controllable On Time - ns Icl - Current Limited Threshold - A 8 TJ = -40°C VI = 12 V, IO = 2 A 110 100 6 5 4 3 8 13 VI - Input Voltage - V 90 80 70 -50 18 -25 0 Figure 13. 150 BOOT-PH UVLO THRESHOLD vs TEMPERATURE 2.
PAGE 10
TPS54320 SLVS982A – AUGUST 2010 – REVISED SEPTEMBER 2010 www.ti.com The device reduces the external component count by integrating the boot recharge circuit. The bias voltage for the integrated high-side MOSFET is supplied by a capacitor between the BOOT and PH pins. The boot capacitor voltage is monitored by a BOOT to PH UVLO (BOOT-PH UVLO) circuit allowing PH pin to be pulled low to recharge the boot capacitor.
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TPS54320 www.ti.com SLVS982A – AUGUST 2010 – REVISED SEPTEMBER 2010 Adjusting the Output Voltage The output voltage is set with a resistor divider from the output (VOUT) to the VSENSE pin. It is recommended to use 1% tolerance or better divider resistors. Referring to the application schematic of Figure 34, start with a 10 kΩ resistor for R9 and use Equation 1 to calculate R8. To improve efficiency at light loads, consider using larger value resistors.
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TPS54320 SLVS982A – AUGUST 2010 – REVISED SEPTEMBER 2010 www.ti.com TPS54320 VIN ip ih R1 R2 EN Figure 17. Adjustable VIN Under Voltage Lock Out TPS54320 PVIN ip ih R1 R2 EN Figure 18. Adjustable PVIN Under Voltage Lock Out, VIN ≥ 4.5V TPS54320 PVIN VIN ip ih R1 R2 EN Figure 19.
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TPS54320 www.ti.com SLVS982A – AUGUST 2010 – REVISED SEPTEMBER 2010 Adjustable Switching Frequency and Synchronization (RT/CLK) The RT/CLK pin can be used to set the switching frequency of the device in two modes. In RT mode, a resistor (RT resistor) is connected between the RT/CLK pin and GND. The switching frequency of the device is adjustable from 200 kHz to 1200 kHz by using a maximum of 240 kΩ and minimum of 40.2 kΩ respectively. In CLK mode, an external clock is connected directly to the RT/CLK pin.
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TPS54320 SLVS982A – AUGUST 2010 – REVISED SEPTEMBER 2010 www.ti.com RT/CLK mode select TPS54320 RT/CLK Rrt Figure 21. Works with Both RT mode and CLK mode Slow Start (SS/TR) The device uses the lower voltage of the internal voltage reference or the SS/TR pin voltage as the reference voltage and regulates the output accordingly. A capacitor on the SS/TR pin to ground implements a slow start time. The device has an internal pull-up current source of 2.3mA that charges the external slow start capacitor.
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TPS54320 www.ti.com SLVS982A – AUGUST 2010 – REVISED SEPTEMBER 2010 Sequencing (SS/TR) Many of the common power supply sequencing methods can be implemented using the SS/TR, EN, and PWRGD pins. The sequential method is illustrated in Figure 22 using two TPS54320 devices. The power good of the first device is coupled to the EN pin of the second device which enables the second power supply once the primary supply reaches regulation. Figure 23 shows the results of Figure 22.
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TPS54320 SLVS982A – AUGUST 2010 – REVISED SEPTEMBER 2010 www.ti.com Ratio-metric and simultaneous power supply sequencing can be implemented by connecting the resistor network of R1 and R2 shown in Figure 26 to the output of the power supply that needs to be tracked or another voltage reference source. Using Equation 6 and Equation 7, the tracking resistors can be calculated to initiate the Vout2 slightly before, after or at the same time as Vout1.
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TPS54320 www.ti.com SLVS982A – AUGUST 2010 – REVISED SEPTEMBER 2010 EN = 2 V / div EN = 2 V / div Vout1 = 1 V / div Vout1 = 1 V / div Vout2 = 1 V / div Vout2 = 1 V / div Time = 2 msec / div Time = 2 msec / div Figure 28. Ratio-metric Startup with Vout2 Leading Vout1 Figure 29. Simultaneous Startup Output Overvoltage Protection (OVP) The device incorporates an output overvoltage protection (OVP) circuit to minimize output voltage overshoot.
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TPS54320 SLVS982A – AUGUST 2010 – REVISED SEPTEMBER 2010 www.ti.com Furthermore, if an output overload condition (as measured by the COMP pin voltage) has lasted for more than the hiccup wait time which is programmed for 512 switching cycles, the device will shut down itself and restart after the hiccup time which is set for 16384 cycles. The hiccup mode helps to reduce the device power dissipation under severe overcurrent conditions.
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TPS54320 www.ti.com SLVS982A – AUGUST 2010 – REVISED SEPTEMBER 2010 VOUT VC RESR RL gm ps CO Figure 31. Simplified Small Signal Model for Peak Current Mode Control VOUT Adc VC RESR fp RL gm ps CO fz Figure 32.
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TPS54320 SLVS982A – AUGUST 2010 – REVISED SEPTEMBER 2010 www.ti.com Small Signal Model for Frequency Compensation The device uses a transconductance amplifier for the error amplifier and readily supports two of the commonly used Type II compensation circuits and a Type III frequency compensation circuit, as shown in Figure 33. In Type 2A, one additional high frequency pole, C6, is added to attenuate high frequency noise.
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TPS54320 www.ti.com SLVS982A – AUGUST 2010 – REVISED SEPTEMBER 2010 APPLICATION INFORMATION Design Guide – Step-By-Step Design Procedure This example details the design of a high frequency switching regulator using ceramic output capacitors. A few parameters must be known in order to start the design process. These parameters are typically determined at the system level. For this example, we start with the following known parameters: PARAMETER VALUE Output Voltage 3.
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TPS54320 SLVS982A – AUGUST 2010 – REVISED SEPTEMBER 2010 www.ti.com Output Inductor Selection To calculate the value of the output inductor, Equation 18 is used. KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. The inductor ripple current is filtered by the output capacitor.
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TPS54320 www.ti.com SLVS982A – AUGUST 2010 – REVISED SEPTEMBER 2010 Equation 23 calculates the minimum output capacitance needed to meet the output voltage ripple specification. Where fsw is the switching frequency, Voripple is the maximum allowable output voltage ripple, and Iripple is the inductor ripple current. In this case, the maximum output voltage ripple is 33mV. Under this requirement, Equation 23 yields 6.4µF.
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TPS54320 SLVS982A – AUGUST 2010 – REVISED SEPTEMBER 2010 www.ti.com Slow Start Capacitor Selection The slow start capacitor determines the minimum amount of time it takes for the output voltage to reach its nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This is also used if the output capacitance is large and requires a large amount of current to charge the capacitor to the output voltage level.
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TPS54320 www.ti.com SLVS982A – AUGUST 2010 – REVISED SEPTEMBER 2010 Compensation Component Selection There are several industry techniques used to compensate DC/DC regulators. The method presented here is easy to calculate and yields high phase margins. For most conditions, the regulator has a phase margin between 60 and 90 degrees. The method presented here ignores the effects of the slope compensation that is internal to the TPS54320.
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TPS54320 SLVS982A – AUGUST 2010 – REVISED SEPTEMBER 2010 www.ti.com Application Curves STARTUP with VIN (1.1 Ω Load) LOAD TRANSIENT VIN = 10 V/div VOUT = 50 mV/div (AC coupled) EN = 2 V/div IOUT = 500 mA/div (0.75 to 1.5 A load step) SS/TR = 1 V/div VIN = 12 V VOUT = 2 V/div t - Time - 20 ms/div t - Time - 2 ms/div Figure 35. Figure 36. STARTUP with EN (1.
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TPS54320 www.ti.com SLVS982A – AUGUST 2010 – REVISED SEPTEMBER 2010 STARTUP and SHUTDOWN with PRE-BIAS on EN (1.1 Ω Load) SHUTDOWN with VIN (1.1 Ω Load) VIN = 10 V/div EN = 1 V/div EN = 2 V/div VOUT starting and stopping from a 0.5 V pre-bias voltage SS/TR = 1 V/div VOUT = 2 V/div VOUT = 1 V/div t - Time - 2 ms/div t - Time - 2 ms/div Figure 41. Figure 42. SHUTDOWN with EN (1.1 Ω Load) OUTPUT VOLTAGE RIPPLE (1.
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TPS54320 SLVS982A – AUGUST 2010 – REVISED SEPTEMBER 2010 www.ti.com CLOSED LOOP RESPONSE LINE REGULATION 180 60 VIN = 12 V, 50 Load = 1.1 W 40 Phase 150 0.04 120 0.03 90 Gain 10 30 0 0 Phase - deg 60 20 0.02 Percent Deviation - % 30 Gain - dB 0.05 0 -10 -30 -20 -60 -30 -90 -40 -120 -0.03 -50 -150 -0.04 -60 100 1k 10k f - Frequency - Hz IO = 3 A -0.01 -0.02 -180 1M 100k IO = 1.5 A IO = 1 A 0.01 -0.05 8 10 12 14 VI - Input Voltage - V Figure 47.
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TPS54320 www.ti.com SLVS982A – AUGUST 2010 – REVISED SEPTEMBER 2010 JUNCTION TEMPERATURE vs IC POWER DISSIPATION EFFICIENCY vs LOAD CURRENT 100 150 VI = 8 V VI = 10 V 95 125 90 Efficiency - % TJ - Junction Temperature - °C TA = Room Temperature no airflow 100 75 VI = 15 V 85 VI = 12 V VI = 17 V 80 75 70 50 65 25 60 0 0.5 1 1.5 2 2.5 IC Power Dissipation - W 3 3.5 0 Figure 53. 0.5 1 1.5 Load Current - A 2 2.5 3 Figure 54. Thermal Performance Figure 55.
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TPS54320 SLVS982A – AUGUST 2010 – REVISED SEPTEMBER 2010 www.ti.com Bill of Materials Table 1. Bill of Materials Count RefDes Value Description Size Part Number MFR 2 C2, C3 4.7 µF Capacitor, Ceramic, 25V, X5R, 10% 0805 Std Std 1 C4 0.015 µF Capacitor, Ceramic, 50V, X7R, 10% 0603 Std Std 1 C5 0.1 µF Capacitor, Ceramic, 16V, X7R, 10% 0603 Std Std 1 C6 330 pF Capacitor, Ceramic, 25V, X7R, 10% 0603 Std Std 1 C7 0.
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TPS54320 www.ti.com SLVS982A – AUGUST 2010 – REVISED SEPTEMBER 2010 TOPSIDE GROUND AREA FREQUENCY SET RESISTOR PVIN INPUT BYPASS CAPACITOR RT/CLK OUTPUT FILTER CAPACITOR PWRGD GND BOOT CAPACITOR BOOT EXPOSED THERMAL PAD AREA GND PH PVIN PH PVIN EN VIN SS/TR VSENSE PVIN OUTPUT INDUCTOR VOUT PH COMP VIN SLOW START CAPACITOR VIN INPUT BYPASS CAPACITOR FEEDBACK RESISTORS UVLO SET RESISTORS COMPENSATION NETWORK ANALOG GROUND TRACE 0.010 in.
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TPS54320 SLVS982A – AUGUST 2010 – REVISED SEPTEMBER 2010 www.ti.com Note: Page numbers of current version may differ from previous versions. Changes from Original (August 2010) to Revision A Page • Changed "Applications" itemized list .................................................................................................................................... 1 • Changed Figure 34 - Typical App Circuit .............................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS54320RHLR VQFN RHL 14 3000 330.0 12.4 3.75 3.75 1.15 8.0 12.0 Q1 TPS54320RHLR VQFN RHL 14 3000 330.0 12.4 3.75 3.75 1.15 8.0 12.0 Q1 TPS54320RHLT VQFN RHL 14 250 180.0 12.4 3.75 3.75 1.15 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS54320RHLR VQFN RHL 14 3000 367.0 367.0 35.0 TPS54320RHLR VQFN RHL 14 3000 367.0 367.0 35.0 TPS54320RHLT VQFN RHL 14 250 210.0 185.0 35.0 TPS54320RHLT VQFN RHL 14 250 210.0 185.0 35.
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