Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - DC/DC voltage regulator Holder HTSSOP 14

V (50mV/div)

OUT

I (1 A/div)

OUT

100 s/divm

TPS54326

www.ti.com

SLVSA13E –OCTOBER 2009–REVISED JUNE 2012

4.5V to 18V Input, 3-A Synchronous Step-Down Converter with Eco-mode™

Check for Samples: TPS54326

FEATURES

DESCRIPTION

The TPS54326 is an adaptive on-time D-CAP2™

• D-CAP2™ Mode Enables Fast Transient

mode synchronous buck converter. The TPS54326

Response

enables system designers to complete the suite of

• Low Output Ripple and Allows Ceramic Output

various end equipment’s power bus regulators with a

Capacitor

cost effective, low component count, low standby

current solution. The main control loop for the

• Wide V

Input Voltage Range: 4.5 V to 18 V

TPS54326 uses the D-CAP2™ mode control which

• Wide V

Input Voltage Range: 2 V to 18 V

provides a fast transient response with no external

• Output Voltage Range: 0.76 V to 5.5 V

components. The adoptive on-time control supports

• Highly Efficient Integrated FET’s Optimized

seamless operation between PWM mode at heavy

load condition and reduced frequency Eco-mode™

for Lower Duty Cycle Applications

operation at light load for high efficiency.

- 120 mΩ (High Side) and 70 mΩ (Low Side)

• High Efficiency, less than 10 μA at Shutdown

The TPS54326 also has a proprietary circuit that

enables the device to adapt to both low equivalent

• Auto-Skip Eco-mode™ for High Efficiency at

series resistance (ESR) output capacitors, such as

Light Load

POSCAP or SP-CAP, and ultra-low ESR ceramic

• High Initial Bandgap Reference Accuracy

capacitors. The device operates from 4.5-V to 18-V

• Adjustable Soft Start

input , and from 2-V to 18-V VIN input power

supply voltage. The output voltage can be

• Pre-Biased Soft Start

programmed between 0.76 V and 5.5 V. The device

• 700-kHz Switching Frequency (f

)

also features an adjustable slow start time and a

• Cycle-By-Cycle Overcurrent Limit

power good function. The TPS54326 is available in

the 14 pin HTSSOP or 16 pin QFN package, and

• Power Good Output

designed to operate from –40°C to 85°C.

APPLICATIONS

• Wide Range of Applications for Low Voltage

System

– Digital TV Power Supply

– High Definition Blu-ray Disc™ Players

– Networking Home Terminal

– Digital Set Top Box (STB)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2D-CAP2, Eco-mode, PowerPAD are trademarks of Texas Instruments.

3Blu-ray Disc is a trademark of Blu-ray Disc Association.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (29 pages)

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TPS54326 www.ti.com SLVSA13E – OCTOBER 2009 – REVISED JUNE 2012 4.5V to 18V Input, 3-A Synchronous Step-Down Converter with Eco-mode™ Check for Samples: TPS54326 FEATURES DESCRIPTION • The TPS54326 is an adaptive on-time D-CAP2™ mode synchronous buck converter. The TPS54326 enables system designers to complete the suite of various end equipment’s power bus regulators with a cost effective, low component count, low standby current solution.
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TPS54326 SLVSA13E – OCTOBER 2009 – REVISED JUNE 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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TPS54326 www.ti.com SLVSA13E – OCTOBER 2009 – REVISED JUNE 2012 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply input voltage range 4.5 18 V VIN Power input voltage range 2 18 V VBST –0.1 24 VBST (vs SW1, SW2) –0.1 5.7 SS, PG –0.1 5.7 EN –0.1 18 VO, VFB –0.1 5.5 SW1, SW2 –1.8 18 VI Input voltage range SW1, SW2 (10 ns transient) –3 18 PGND1, PGND2 –0.1 0.
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TPS54326 SLVSA13E – OCTOBER 2009 – REVISED JUNE 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range, VCC, VIN = 12V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ON-TIME TIMER CONTROL tON On time VIN = 12 V, VO = 1.05 V 145 tOFF(MIN) Minimum off time TA = 25°C, VFB = 0.7 V 260 310 ns 2.6 ns SOFT START ISSC SS charge current VSS = 0 V 1.4 2 ISSD SS discharge current VSS = 0.5 V 0.1 0.
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TPS54326 www.ti.com SLVSA13E – OCTOBER 2009 – REVISED JUNE 2012 VFB VREG5 VO VCC VIN2 VIN1 RGT PACKAGE (TOP VIEW) 16 15 14 13 1 2 12 VBST 11 SW3 EXPOSED THERMAL PAD SW2 GND 4 9 SW1 PG 5 6 7 8 PGND2 10 PGND1 3 EN SS PIN FUNCTIONS PIN NAME DESCRIPTION PWP 14 RGT 16 VO 1 16 Connect to output of converter. This pin is used for On-Time Adjustment. VFB 2 1 Converter feedback input. Connect with feedback resistor divider. VREG5 3 2 5.5 V power supply output.
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TPS54326 SLVSA13E – OCTOBER 2009 – REVISED JUNE 2012 www.ti.com Functional Block Diagram -30% UV 14 VO VIN VIN OV 1 VCC 13 +20% VREG5 12 Control logic VBST Ref SS 1 shot SW VFB SGND 10 XCON VREG5 VREG5 Ceramic Capacitor 3 1 mF VO 11 2 SS 9 4 8 SW Softstart ZC SS PGND 5 PGND PGND GND SW OCP SGND PG Ref 6 PGND VCC -10% UV VREG5 EN 7 A. EN Logic OV UVLO UVLO Protection Logic TSD REF Ref Block diagram shown is for PWP 14 pin package.
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TPS54326 www.ti.com SLVSA13E – OCTOBER 2009 – REVISED JUNE 2012 At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one shot timer expires. This one shot timer is set by the converter input voltage ,VIN, and the output voltage ,VO, to maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control.
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TPS54326 SLVSA13E – OCTOBER 2009 – REVISED JUNE 2012 www.ti.com Current Protection The output over-current protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit. The switch current is monitored by measuring the low-side FET switch voltage between the SW pin and GND. This voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature compensated.
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TPS54326 www.ti.com SLVSA13E – OCTOBER 2009 – REVISED JUNE 2012 TYPICAL CHARACTERISTICS VIN = 12 V, TA = 25°C (unless otherwise noted) spacer 1200 8 1000 Shutdown Current - mA Supply Current - mA 6 800 600 400 4 2 200 0 -50 0 50 100 TJ - Junction Temperature - °C 0 -50 150 Figure 1. VCC SUPPLY CURRENT vs. JUNCTION TEMPERATURE 50 100 TJ - Junction Temperature - °C 150 Figure 2. VCC SHUTDOWN CURRENT vs. JUNCTION TEMPERATURE 1.1 1.1 1.075 1.05 VI = 12 V IO = 10 mA 1.
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TPS54326 SLVSA13E – OCTOBER 2009 – REVISED JUNE 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) VIN = 12 V, TA = 25°C (unless otherwise noted) spacer VOUT (50 mV/div) EN (10 V/div) VOUT (0.5 V/div) IOUT (1 A/div) PG (5 V/div) 100 ms/div 400 ms/div Figure 5. 1.05-V, 0-A TO 3-A LOAD TRANSIERESPONSE Figure 6. START-UP WAVE FORM 100 100 VO = 3.3 V VO = 3.3 V 20 80 VO = 1.8 V VO = 2.5 V Efficiency - % Efficiency - % 80 60 VO = 1.8 V 60 VO = 2.5 40 40 20 20 0 0 0.5 1 1.
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TPS54326 www.ti.com SLVSA13E – OCTOBER 2009 – REVISED JUNE 2012 TYPICAL CHARACTERISTICS (continued) VIN = 12 V, TA = 25°C (unless otherwise noted) spacer 900 900 800 VO = 1.8 V fsw - Switching Frequency - kHz fsw - Switching Frequency - kHz 700 800 600 VO = 1.8 V VO = 2.5 V 500 700 400 300 VO = 3.3 V 600 200 100 500 0 5 10 VI - Input Voltage - V 15 20 Figure 9. SWITCHING FREQUENCY vs INPUT VOLTAGE 0 0.001 0.01 IO - Output Current - A 0.1 Figure 10.
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TPS54326 SLVSA13E – OCTOBER 2009 – REVISED JUNE 2012 www.ti.com DESIGN GUIDE Step By Step Design Procedure To • • • • • begin the design process, the following application parameters must be known: Input voltage range Output voltage Output current Output voltage ripple Input voltage ripple Figure 13 shows the schematic diagram for this design example. Figure 13. Schematic Diagram Output Voltage Resistors Selection The output voltage is set with a resistor divider from the output node to the VFB pin.
PAGE 13
TPS54326 www.ti.com SLVSA13E – OCTOBER 2009 – REVISED JUNE 2012 Output Filter Selection The output filter used with the TPS54326 is an LC circuit. This LC filter has double pole at: FP = 1 2p LOUT ´ COUT (5) At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal gain of the TPS54326. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls off at a –40 dB per decade rate and the phase drops rapidly.
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TPS54326 SLVSA13E – OCTOBER 2009 – REVISED JUNE 2012 www.ti.com Input Capacitor Selection The TPS54326 requires an input decoupling capacitor and a bulk capacitor is needed depending on the application. A ceramic capacitor over 10 μF is recommended for the decoupling capacitor. An additional 0.1 µF capacitor from pin 14 to ground is recommended. The capacitor voltage rating needs to be greater than the maximum input voltage. Bootstrap Capacitor Selection A 0.
PAGE 15
TPS54326 www.ti.com SLVSA13E – OCTOBER 2009 – REVISED JUNE 2012 LAYOUT CONSIDERATIONS The following layout guidelines are provided using the PWP 14 pin package as an example. The general guidelines and routing are also applicable to the QFN 16 pin package. Allowance should be made for the differences in the package pin configurations. 1. Keep the input switching current loop as small as possible. 2.
PAGE 16
TPS54326 SLVSA13E – OCTOBER 2009 – REVISED JUNE 2012 www.ti.com REVISION HISTORY Changes from Original (October 2009) to Revision A • Page Changed the data sheet From: Product Preview To: Production Data ................................................................................ 1 Changes from Revision A (October 2009) to Revision B Page • Changed the title to include Eco-Mode .......................................................................................................................
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TPS54326 www.ti.com SLVSA13E – OCTOBER 2009 – REVISED JUNE 2012 Changes from Revision D (February 2011) to Revision E Page • Removed SWIFT from the data sheet tilte ........................................................................................................................... 1 • Changed VENH min value in ELECTRICAL CHARACTERISTICS from 2 V to 1.5 V ............................................................ 3 • Changed Table 1 last column heading from C8 + C9 to C4 + C5 ..............
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) TPS54326PWPR HTSSOP PWP 14 2000 330.0 12.4 TPS54326RGTR QFN RGT 16 3000 330.0 TPS54326RGTT QFN RGT 16 250 180.0 6.9 5.6 1.6 8.0 12.0 Q1 12.4 3.3 3.3 1.1 8.0 12.0 Q2 12.4 3.3 3.3 1.1 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS54326PWPR HTSSOP PWP 14 2000 367.0 367.0 35.0 TPS54326RGTR QFN RGT 16 3000 367.0 367.0 35.0 TPS54326RGTT QFN RGT 16 250 210.0 185.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.