Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - DC/DC voltage regulator Holder SO 8

VIN

BOOT

VSENSE

COMP

TPS5432

INPUT

3-6 V

GND

Cin

10 F

10 V

4.99 kW

3.3 nF

Css

0.01 Fm

BOOT

0.1 F

10 V

3.3 H

22 Fx2

1.2 V@3 A

10 kW

20 kW

Cff

390 pF

100

Efficiency - %

0 500 1000 1500 2000 2500 3000

Load Current - mA

Vin = 5 V, Vout = 1.2 V

Vin = 3.3 V, Vout = 1.2 V

Vin = 5 V, Vout = 1.8 V

Vin = 3.3 V, Vout = 1.8 V

Vin = 5 V, Vout = 3.3 V

TPS5432

www.ti.com

SLVSB89A –MARCH 2012–REVISED OCTOBER 2012

2.95V to 6V Input, 3A Output, 700kHz Synchronous Step Down Converter

Check for Samples: TPS5432

FEATURES

DESCRIPTION

The TPS5432 is a 6V, 3A, low Iq, current mode,

• Two 70mΩ (typical) MOSFETs for 3A

synchronous monolithic buck converter with

Continuous Output Current

integrated MOSFETs. The TPS5432 enables small

• Current Mode Control With External

designs by integrating the MOSFETs, implementing

Compensation

current mode control to reduce external component

count, reducing inductor size by 700kHz switching

• 700kHz Switching Frequency

frequency. SOIC-8 package with exposed thermal

• 360µA no Load Quiescent Operating Current

pad provides both thermally enhanced solution and

(no switching)

easy to use.

• 0.808V Internal Voltage Reference

The TPS5432 provides accurate regulation for a

• ±2.0% Reference Accuracy at 25°C

variety of loads with an accurate 3.0% voltage

• ±3.0% Reference Accuracy Over Temperature

reference over temperature.

Range –40°C~125°C

Efficiency is maximized through the integrated 70mΩ

• Stable Operation With Ceramic Output

MOSFETs and 360μA typical supply current. Using

Capacitor

the enable pin, shutdown supply current is reduced to

2 µA by entering a shutdown mode.

• Adjustable Slow Start

• Cycle by Cycle Current Limit, and Frequency

The output voltage startup ramp is controlled by the

Fold Back Protection

slow start pin. A ceramic capacitor at this pin can

easily adjust the slow start time.

• Thermally Enhanced 8-Pin SOIC (DDA)

Package

Frequency fold back and thermal shutdown protects

the device during an over-current condition.

APPLICATIONS

• Consumer Applications such as DTV, Set Top

Boxes, LCD displays, CPE

• Low-Voltage Point-of-Load Regulations for

SoC, CPU, DSP

SIMPLIFIED SCHEMATIC

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (31 pages)

PAGE 1
TPS5432 www.ti.com SLVSB89A – MARCH 2012 – REVISED OCTOBER 2012 2.95V to 6V Input, 3A Output, 700kHz Synchronous Step Down Converter Check for Samples: TPS5432 FEATURES DESCRIPTION • The TPS5432 is a 6V, 3A, low Iq, current mode, synchronous monolithic buck converter with integrated MOSFETs. The TPS5432 enables small designs by integrating the MOSFETs, implementing current mode control to reduce external component count, reducing inductor size by 700kHz switching frequency.
PAGE 2
TPS5432 SLVSB89A – MARCH 2012 – REVISED OCTOBER 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. PIN CONFIGURATION SO-8 WITH THERMAL PAD (TOP VIEW) BOOT 1 VIN 2 8 SS 7 EN Thermal Pad PH 3 6 COMP GND 4 5 VSENSE PIN FUNCTIONS PIN DESCRIPTION NAME NUMBER BOOT 1 A bootstrap cap is required between BOOT and PH.
PAGE 3
TPS5432 www.ti.com SLVSB89A – MARCH 2012 – REVISED OCTOBER 2012 ABSOLUTE MAXIMUM RATING (1) VALUE MIN Input voltage MAX VIN –0.3 7 EN –0.3 3.6 BOOT PH + 7 VSENSE –0.3 3 COMP –0.3 3 SS –0.3 3 BOOT-PH Output voltage Sink current –0.6 –2 (2) V 10 100 COMP 100 SS 100 Electrostatic discharge (CDM) QSS 009-147 (JESD22-C101B.
PAGE 4
TPS5432 SLVSB89A – MARCH 2012 – REVISED OCTOBER 2012 www.ti.com ELECTRICAL CHARACTERISTICS The Electrical Ratings specified in this section apply to all specifications in this document, unless otherwise noted. These specifications are interpreted as conditions that do not degrade the parametric or functional specifications of the device for the life of the product containing it. Test Conditions: TJ = –40°C to 125°C, VIN = 2.
PAGE 5
TPS5432 www.ti.com SLVSB89A – MARCH 2012 – REVISED OCTOBER 2012 TYPICAL CHARACTERISTICS CURVES HIGH SIDE & LOW SIDE Rdson vs JUNCTION TEMPERATURE FREQUENCY vs JUNCTION TEMPERATURE 750 120 110 HSF, VI = 3.3 V LSF, VI = 5 V 100 90 VI =5 V LSF, VI = 3.
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TPS5432 SLVSB89A – MARCH 2012 – REVISED OCTOBER 2012 www.ti.com TYPICAL CHARACTERISTICS CURVES (continued) SWITCHING FREQUENCY vs VSENSE EA TRANSCONDUCTANCE vs JUNCTION TEMPERATURE 100 290 EA - Transconductance - mA/V Nominal Switching Frequency - % TJ = 25°C 75 Vsense Falling Vsense Rising 50 25 VI = 3.3 V 270 250 230 210 190 0 0 0.1 0.2 0.3 0.4 0.5 VSENSE - V 0.6 0.7 170 -50 0.8 -25 0 25 50 75 100 TJ - Junction Temperature - °C 125 Figure 5. Figure 6.
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TPS5432 www.ti.com SLVSB89A – MARCH 2012 – REVISED OCTOBER 2012 TYPICAL CHARACTERISTICS CURVES (continued) INPUT VOLTAGE UVLO THRESHOLD vs JUNCTION TEMPERATURE SHUTDOWN SUPPLY CURRENT vs JUNCTION TEMPERATURE 4 2.9 VI = 3.3 V; EN = 0 V Isd - Shutdown Quiescent Current - mA 2.8 VI - UVLO Threshold - V UVLO Start switching 2.7 2.6 UVLO Stop switching 2.5 2.4 2.3 2.
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TPS5432 SLVSB89A – MARCH 2012 – REVISED OCTOBER 2012 www.ti.com TYPICAL CHARACTERISTICS CURVES (continued) VIN SUPPLY CURRENT vs INPUT VOLTAGE EN PIN UVLO THRESHOLD vs JUNCTION TEMPERATURE 420 1.26 EN Rising 390 380 370 360 350 1.23 1.22 1.21 1.19 1.18 1.17 330 1.16 3 3.5 4 4.5 5 VI - Input Voltage - V 5.5 1.15 -50 6 -25 0 25 50 75 100 TJ - Junction Temperature - °C Figure 13. Figure 14. EN PIN PULLUP CURRENT vs JUNCTION TEMPERATURE EN PIN PULLUP CURRENT vs JUNCTION TEMPERATURE 5 4.
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TPS5432 www.ti.
PAGE 10
TPS5432 SLVSB89A – MARCH 2012 – REVISED OCTOBER 2012 www.ti.com The TPS5432 minimizes excessive output over-voltage transients by taking advantage of the over-voltage comparator. When the regulated output voltage is greater than 107% of the nominal voltage, the over-voltage comparator is activated, and the high side MOSFET is turned off and masked from turning on until the output voltage is lower than 105%. The SS (slow start) pin is used to minimize inrush currents during power up.
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TPS5432 www.ti.com SLVSB89A – MARCH 2012 – REVISED OCTOBER 2012 ADJUSTING THE OUTPUT VOLTAGE The output voltage is set with a resistor divider from the output node to the VSENSE pin. It is recommended to use divider resistors with 1% tolerance or better. Start with a 10 kΩ for the R1 resistor, Figure 17, and use the Equation 1 to calculate R2. To improve efficiency at light loads consider using larger value resistors.
PAGE 12
TPS5432 SLVSB89A – MARCH 2012 – REVISED OCTOBER 2012 www.ti.com spacer R2 = R1 ´ VENFALLING ( VST OP - VENF ALL ING + R1 Ip + Ih ) (3) Where Ih = 3.4 µA, IP = 1.2 µA, VENRISING = 1.23V, VENFALLING = 1.19 V VSTART is the target VIN UVLO rising threshold set by EN resistors. VSTOP is the target VIN UVLO falling threshold set by EN resistors. SLOW START PIN The TPS5432 regulates to the lower of the SS pin and the internal reference voltage.
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TPS5432 www.ti.com SLVSB89A – MARCH 2012 – REVISED OCTOBER 2012 THERMAL SHUTDOWN The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 170°C. The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal trip threshold. Once the die temperature decreases below 155°C, the device reinitiates the power-up sequence by discharging the SS pin to 0 volts. The thermal shutdown hysteresis is 15°C.
PAGE 14
TPS5432 SLVSB89A – MARCH 2012 – REVISED OCTOBER 2012 www.ti.com APPLICATION INFORMATION DESIGN GUIDE – STEP-BY-STEP DESIGN PROCEDURE This example details the design of a high frequency switching regulator design using ceramic output capacitors. This design is available as the TPS5432EVM-116 (PWR116) evaluation module (EVM). A few parameters must be known in order to start the design process. These parameters are typically determined on the system level.
PAGE 15
TPS5432 www.ti.com SLVSB89A – MARCH 2012 – REVISED OCTOBER 2012 The current flowing through the inductor is the inductor ripple current plus the output current. During power up, faults or transient load conditions, the inductor current can increase above the calculated peak inductor current level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of the device.
PAGE 16
TPS5432 SLVSB89A – MARCH 2012 – REVISED OCTOBER 2012 www.ti.com Equation 10 calculates the minimum output capacitance needed to meet the output voltage ripple specification. Where fsw is the switching frequency, Vripple is the maximum allowable output voltage ripple, and Iripple is the inductor ripple current. In this case, the maximum output voltage ripple is 18 mV. Under this requirement, Equation 10 yields 8.1 uF.
PAGE 17
TPS5432 www.ti.com Icirms = Iout ´ SLVSB89A – MARCH 2012 – REVISED OCTOBER 2012 Vout ´ Vinmin (Vinmin - Vout ) Vinmin (13) vertical spacer Ioutmax ´ 0.25 DVin = Cin ´ ¦ sw (14) SLOW START CAPACITOR The slow start capacitor determines the minimum amount of time it takes for the output voltage to reach its nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate.
PAGE 18
TPS5432 SLVSB89A – MARCH 2012 – REVISED OCTOBER 2012 www.ti.com For the TPS5432 most circuits will have relatively high amounts of slope compensation. As more slope compensation is applied, the power stage characteristics will deviate from the ideal approximations. The phase loss of the power stage will now approach -180 degrees, making compensation more difficult. The power stage transfer function can be solved but it is a tedious hand calculation that does not lend itself to simple approximations.
PAGE 19
TPS5432 www.ti.com SLVSB89A – MARCH 2012 – REVISED OCTOBER 2012 This zero and pole pair is not independent. Once the zero location is chosen, the pole is fixed as well. For optimum performance, the zero and pole should be located symmetrically about the intended crossover frequency. The required value for C10 can calculated from Equation 23. 1 C7 = VREF 2 × p × R6 × FCO × VOUT (23) For this design the calculated values for the compensation components are R3 = 4.
PAGE 20
TPS5432 SLVSB89A – MARCH 2012 – REVISED OCTOBER 2012 www.ti.com VIN = 5 V/div VIN = 5 V/div EN = 2 V/div EN = 2 V/div SS = 2 V/div SS = 2 V/div VOUT = 1 V/div VOUT = 1 V/div Time = 2 ms/div Time = 2 ms/div Figure 25. START UP RELATIVE TO VIN Figure 26. START UP RELATIVE TO EN VIN = 5 V/div VIN = 5 V/div EN = 2 V/div EN = 2 V/div SS = 2 V/div SS = 2 V/div VOUT = 1 V/div VOUT = 1 V/div Time = 2 ms/div Time = 2 ms/div Figure 27. SHUT DOWN RELATIVE TO VIN Figure 28.
PAGE 21
TPS5432 www.ti.com SLVSB89A – MARCH 2012 – REVISED OCTOBER 2012 LAYOUT Layout is a critical portion of good power supply design. There are several signal paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance. Care should be taken to minimize the loop area formed by the bypass capacitor connections and the VIN pins. See Figure 31 for a PCB layout example.
PAGE 22
TPS5432 SLVSB89A – MARCH 2012 – REVISED OCTOBER 2012 www.ti.
PAGE 23
TPS5432 www.ti.com SLVSB89A – MARCH 2012 – REVISED OCTOBER 2012 REVISION HISTORY Note: Page numbers of current version may differ from previous versions. Changes from Original (March 2012) to Revision A Page • Changed lower temperature range from –20°C to –40°C in the Reference Accuracy Over Temperature bullet ................. 1 • Changed ESD HBM spec from 1 kV to 2 kV ........................................................................................................................
PAGE 24
PACKAGE OPTION ADDENDUM www.ti.
PAGE 25
PACKAGE OPTION ADDENDUM www.ti.com 31-May-2014 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PAGE 26
PACKAGE MATERIALS INFORMATION www.ti.com 5-May-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS5432DDAR Package Package Pins Type Drawing SO Power PAD DDA 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.8 Pack Materials-Page 1 6.4 B0 (mm) K0 (mm) P1 (mm) 5.2 2.1 8.0 W Pin1 (mm) Quadrant 12.
PAGE 27
PACKAGE MATERIALS INFORMATION www.ti.com 5-May-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS5432DDAR SO PowerPAD DDA 8 2500 366.0 364.0 50.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.