Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - DC/DC voltage regulator Holder SOIC 8

VIN

GND

BOOT

VSENSE

COMP

VIN

BOOT

Ren1

Ren2

TPS54331D

OUT

100

0.01 0.1 1 10

Efficiency-%

I -LoadCurrent- A

V =3.3V

V =12V

V =18V

V =24V

V =28V

V =5V

TPS54331

www.ti.com

SLVS839D –JULY 2008– REVISED JANUARY 2012

3A, 28V INPUT, STEP DOWN SWIFT™ DC/DC CONVERTER WITH ECO-MODE™

Check for Samples: TPS54331

FEATURES

APPLICATIONS

• 3.5V to 28V Input Voltage Range

• Consumer Applications such as Set-Top

Boxes, CPE Equipment, LCD Displays,

• Adjustable Output Voltage Down to 0.8V

Peripherals, and Battery Chargers

• Integrated 80 mΩ High Side MOSFET Supports

• Industrial and Car Audio Power Supplies

up to 3A Continuous Output Current

• 5V, 12V and 24V Distributed Power Systems

• High Efficiency at Light Loads with a Pulse

Skipping Eco-mode™

DESCRIPTION

• Fixed 570kHz Switching Frequency

The TPS54331 is a 28-V, 3-A non-synchronous buck

• Typical 1μA Shutdown Quiescent Current

converter that integrates a low R

DS(on)

high side

• Adjustable Slow Start Limits Inrush Currents

MOSFET. To increase efficiency at light loads, a

pulse skipping Eco-mode™ feature is automatically

• Programmable UVLO Threshold

activated. Furthermore, the 1 μA shutdown supply

• Overvoltage Transient Protection

current allows the device to be used in battery

• Cycle-by-Cycle Current Limit, Frequency Fold

powered applications. Current mode control with

Back and Thermal Shutdown Protection

internal slope compensation simplifies the external

compensation calculations and reduces component

• Available in Easy-to-Use SOIC8 Package or

count while allowing the use of ceramic output

Thermally Enhanced SOIC8 PowerPAD

capacitors. A resistor divider programs the hysteresis

Package

of the input under-voltage lockout. An overvoltage

• Supported by SwitcherPro™ Software Tool

transient protection circuit limits voltage overshoots

(http://focus.ti.com/docs/toolsw/folders/print/s

during startup and transient conditions. A cycle by

witcherpro.html)

cycle current limit scheme, frequency fold back and

thermal shutdown protect the device and the load in

• For SWIFT™ Documentation, See the TI

the event of an overload condition. The TPS54331 is

Website at www.ti.com/swift

available in 8-pin SOIC package and 8-pin SOIC

PowerPAD

package that have been internally

optimized to improve thermal performance.

SIMPLIFIED SCHEMATIC Figure 1. EFFICIENCY

TPS54331D

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2SWIFT, Eco-mode, SwitcherPro, PowerPAD are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (31 pages)

PAGE 1
TPS54331 SLVS839D – JULY 2008 – REVISED JANUARY 2012 www.ti.com 3A, 28V INPUT, STEP DOWN SWIFT™ DC/DC CONVERTER WITH ECO-MODE™ Check for Samples: TPS54331 FEATURES APPLICATIONS • • • • 1 2 • • • • • • • • • • 3.5V to 28V Input Voltage Range Adjustable Output Voltage Down to 0.
PAGE 2
TPS54331 SLVS839D – JULY 2008 – REVISED JANUARY 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION CONTINUED For additional design needs, see: TPS54231 TPS54232 TPS54233 TPS54331 IO(Max) 2A 2A 2A 3A 3.5A Input Voltage Range 3.5V - 28V 3.5V - 28V 3.5V - 28V 3.5V - 28V 3.5V - 28V Switching Freq.
PAGE 3
TPS54331 SLVS839D – JULY 2008 – REVISED JANUARY 2012 www.ti.com PACKAGE DISSIPATION RATINGS (1) (1) (2) (3) (2) (3) PACKAGE THERMAL IMPEDANCE JUNCTION TO AMBIENT PSEUDO THERMAL IMPEDANCE JUNCTION TO TOP SOIC8 100°C/W 5°C/W SOIC8 PowerPAD™ 50°C/W 5°C/W Maximum power dissipation may be limited by overcurrent protection Power rating at a specific ambient temperature TA should be determined with a junction temperature of 150°C. This is the point where distortion starts to substantially increase.
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TPS54331 SLVS839D – JULY 2008 – REVISED JANUARY 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) TJ = –40°C to 150°C, VIN = 3.5V to 28V (unless otherwise noted) DESCRIPTION TEST CONDITIONS MIN TYP MAX UNIT THERMAL SHUTDOWN Thermal Shutdown 165 °C SLOW START (SS PIN) Charge current V(SS) = 0.4 V 2 μA SS to VSENSE matching V(SS) = 0.
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TPS54331 SLVS839D – JULY 2008 – REVISED JANUARY 2012 www.ti.com FUNCTIONAL BLOCK DIAGRAM EN VIN 165 C Thermal Shutdown 1 mA 3 mA Shutdown Shutdown Logic 1.25 V Enable Threshold Enable Comparator Boot Charge ™ ECO-MODE Minimum Clamp Boot UVLO BOOT 2.1V Error Amplifier VSENSE 2 mA PWM Comparator Gate Drive Logic gm = 92 mA/V DC gain = 800 V/V BW = 2.7 MHz Voltage Reference SS 2 kW 0.
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TPS54331 SLVS839D – JULY 2008 – REVISED JANUARY 2012 www.ti.
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TPS54331 SLVS839D – JULY 2008 – REVISED JANUARY 2012 www.ti.com SUPPLEMENTAL APPLICATION CURVES TYPICAL MINIMUM OUTPUT VOLTAGE vs INPUT VOLTAGE 1.75 30 150 VO - Output Voltage - V IO = 2 A 1.25 1 TJ - Junction Temperature - °C 25 1.5 VO - Output Voltage - V MAXIMUM POWER DISSIPATION vs JUNCTION TEMPERATURE TPS54331D TYPICAL MAXIMUM OUTPUT VOLTAGE vs INPUT VOLTAGE IO = 2 A 20 15 10 IO = 3 A 0.75 0.
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TPS54331 SLVS839D – JULY 2008 – REVISED JANUARY 2012 www.ti.com OVERVIEW The TPS54331 is a 28-V, 3-A, step-down (buck) converter with an integrated high-side n-channel MOSFET. To improve performance during line and load transients, the device implements a constant frequency, current mode control which reduces output capacitance and simplifies external frequency compensation design. The TPS54331 has a pre-set switching frequency of 570kHz. The TPS54331 needs a minimum input voltage of 3.
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TPS54331 SLVS839D – JULY 2008 – REVISED JANUARY 2012 www.ti.com ENABLE AND ADJUSTABLE INPUT UNDER-VOLTAGE LOCKOUT (VIN UVLO) The EN pin has an internal pull-up current source that provides the default condition of the TPS54331 operating when the EN pin floats. The TPS54331 is disabled when the VIN pin voltage falls below internal VIN UVLO threshold. It is recommended to use an external VIN UVLO to add Hysteresis unless VIN is greater than (VOUT + 2 V).
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TPS54331 SLVS839D – JULY 2008 – REVISED JANUARY 2012 www.ti.com CURRENT MODE COMPENSATION DESIGN To simplify design efforts using the TPS54331, the typical designs for common applications are listed in Table 1. For designs using ceramic output capacitors, proper derating of ceramic output capacitance is recommended when doing the stability analysis. This is because the actual ceramic capacitance drops considerably from the nominal value when the applied voltage increases.
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TPS54331 SLVS839D – JULY 2008 – REVISED JANUARY 2012 www.ti.com APPLICATION INFORMATION Vout 3.3 V Iout Max 3 A 6.8 µH 0.1 μF 47 µF Vin 7 V – 28 V 4.7µF 4.7µF 0.01 μF 0Ω 10.2 kΩ 1000 pF 332 kΩ 47 µF 47 pF 0.01 µF 3.24 kΩ 29.4 kΩ 68.1 kΩ Figure 15. Typical Application Schematic STEP BY STEP DESIGN PROCEDURE The following design procedure can be used to select component values for the TPS54331. Alternately, the SwitcherPro™Software may be used to generate a complete design.
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TPS54331 SLVS839D – JULY 2008 – REVISED JANUARY 2012 www.ti.com OUTPUT VOLTAGE SET POINT The output voltage of the TPS54331 is externally adjustable using a resistor divider network. In the application circuit of Figure 15, this divider network is comprised of R5 and R6. The relationship of the output voltage to the resistor divider is given by Equation 4 and Equation 5: R5 ´ VREF R6 = VOUT - VREF (4) é R5 ù VOUT = VREF ´ ê +1ú ë R6 û (5) Choose R5 to be approximately 10.0 kΩ.
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TPS54331 SLVS839D – JULY 2008 – REVISED JANUARY 2012 www.ti.com LMIN = (VIN(MAX) - VOUT ) VOUT(MAX) ´ VIN(MAX) ´ KIND ´ IOUT ´ FSW (8) KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. In general, this value is at the discretion of the designer; however, the following guidelines may be used. For designs using low ESR output capacitors such as ceramics, a value as high as KIND = 0.3 may be used.
PAGE 14
TPS54331 SLVS839D – JULY 2008 – REVISED JANUARY 2012 www.ti.com The maximum ESR of the output capacitor can be determined from the amount of allowable output ripple as specified in the initial design parameters. The contribution to the output ripple voltage due to ESR is the inductor ripple current times the ESR of the output filter, so the maximum specified ESR as listed in the capacitor data sheet is given by Equation 13 ESRmax = VOPPMAX ILPP - (D - 0.
PAGE 15
TPS54331 www.ti.com SLVS839D – JULY 2008 – REVISED JANUARY 2012 Gain = - 20 log (2 ´ p ´ RSENSE ´ FCO ´ CO ) (19) Where: RSENSE = 1Ω/12 FCO = Closed-loop crossover frequency CO = Output capacitance The phase loss is given by Equation 20: PL = a tan (2 ´ p ´ FCO ´ RESR ´ CO ) - a tan (2 ´ p ´ FCO ´ RO ´ CO ) (20) Where: RESR = Equivalent series resistance of the output capacitor RO = VO/IO The measured overall loop response for the circuit is given in Figure 20.
PAGE 16
TPS54331 SLVS839D – JULY 2008 – REVISED JANUARY 2012 CZ = CP = www.ti.com 1 2 ´ p ´ FZ 1 ´ Rz (26) 1 2 ´ p ´ FP1 ´ Rz (27) For this design, the two 47-μF output capacitors are used. For ceramic capacitors, the actual output capacitance is less than the rated value when the capacitors have a dc bias voltage applied. This is the case in a dc/dc converter. The actual output capacitance may be as low as 54 μF. The combined ESR is approximately .001 Ω.
PAGE 17
TPS54331 SLVS839D – JULY 2008 – REVISED JANUARY 2012 www.ti.com OUTPUT VOLTAGE LIMITATIONS Due to the internal design of the TPS54331, there are both upper and lower output voltage limits for any given input voltage. The upper limit of the output voltage set point is constrained by the maximum duty cycle of 91% and is given by Equation 31: VOmax = 0.
PAGE 18
TPS54331 SLVS839D – JULY 2008 – REVISED JANUARY 2012 www.ti.com Ptot is the total device power dissipation (W). TA is the ambient temperature (°C). TJ is the junction temperature (°C) . Rth is the thermal resistance of the package (°C/W). TJMAX is maximum junction temperature (°C). TAMAX is maximum ambient temperature (°C). PCB LAYOUT The VIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor.
PAGE 19
TPS54331 SLVS839D – JULY 2008 – REVISED JANUARY 2012 www.ti.com ELECTROMAGNETIC INTERFERENCE (EMI) CONSIDERATIONS As EMI becomes a rising concern in more and more applications, the internal design of the TPS54331 takes measures to reduce the EMI. The high-side MOSFET gate drive is designed to reduce the PH pin voltage ringing. The internal IC rails are isolated to decrease the noise sensitivity. A package bond wire scheme is used to lower the parasitics effects.
PAGE 20
TPS54331 SLVS839D – JULY 2008 – REVISED JANUARY 2012 www.ti.com Gain - dB VOUT Output Current t - Time - 200 ms/div Figure 21. TPS54331 Transient Response 70 210 60 180 50 150 40 120 30 90 20 60 10 30 0 0 -10 -30 -20 -60 -30 10 100 1k 10k f - Frequency - Hz 100k Phase - deg spacer -90 1M Figure 22. TPS54331 Loop Response spacer spacer VOUT VIN PH PH t - Time - 1 ms/div t - Time - 1 ms/div Figure 23. TPS54331 Output Ripple Figure 24.
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TPS54331 SLVS839D – JULY 2008 – REVISED JANUARY 2012 www.ti.com ENA VIN VOUT VOUT t - Time - 5 ms/div t - Time - 5 ms/div Figure 25. TPS54331 Start Up Figure 26. TPS54331 Start-up Relative to Enable SPACER REVISION HISTORY Changes from Original (July 2008) to Revision A • Page Changed the Elect Char - Shutdown supply current test condition From: -40°C to 25°C To: From: -40°C to 85°C and the MAX value from 10µA to 4µA ...............................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 20-Feb-2014 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line.
PAGE 24
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS54331DDAR Package Package Pins Type Drawing SO Power PAD DDA 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 6.4 B0 (mm) K0 (mm) P1 (mm) 5.2 2.1 8.0 W Pin1 (mm) Quadrant 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS54331DDAR SO PowerPAD DDA 8 2500 367.0 367.0 35.
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