Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - voltage regulator - special purpose HTSSOP 20

6,4 mm X 6,6 mm

Typical Size

www.ti.com

FEATURES DESCRIPTION

APPLICATIONS

VIN PH

BOOT

PGND

VSENSE

VTTQ

AGND

VBIAS

Input

TPS54372

COMP

Compensation

Network

REFIN

VDDQ

t − Time − 25 ms/div

− Output Voltage − 50 mV/div

TRANSIENT RESPONSE

− Output Current − 1 A/div

= 5 V,

= 1.25 V

0 A to

2.25 A

SIMPLIFIED SCHEMATIC

TPS54372

SLVS430D – JUNE 2002 – REVISED FEBRUARY 2005

3-A OUTPUT TRACKING/TERMINATION SYNCHRONOUS PWM SWITCHER WITH

INTEGRATED FETs ( SWIFT™)

• Tracks Externally Applied Reference Voltage

As a member of the SWIFT™ family of dc/dc regu-

lators, the TPS54372 low-input voltage, high-output

• 60-m Ω MOSFET Switches for High Efficiency

current, synchronous-buck PWM converter integrates

at 3-A Continuous Output Source or Sink

all required active components. Included on the

Current

substrate with the listed features are a true, high

• 6% to 90% V

Output Tracking Range

performance, voltage error amplifier that enables

• Wide PWM Frequency: Fixed 350 kHz or

maximum performance under transient conditions

Adjustable 280 kHz to 700 kHz

and flexibility in choosing the output filter L and C

components; an undervoltage-lockout circuit to pre-

• Load Protected by Peak Current Limit and

vent start-up until the input voltage reaches 3 V; an

Thermal Shutdown

internally and externally set slow-start circuit to limit

• Integrated Solution Reduces Board Area and

in-rush currents; and a status output to indicate valid

Total Cost

operating conditions.

The TPS54372 is available in a thermally enhanced

20-pin TSSOP (PWP) PowerPAD™ package, which

• DDR Memory Termination Voltage

eliminates bulky heatsinks. TI provides evaluation

• Active Termination of GTL and SSTL

modules and the SWIFT™ designer software tool to

High-Speed Logic Families

aid in quickly achieving high-performance power

supply designs to meet aggressive equipment devel-

• DAC Controlled, High-Current Output Stage

opment cycles.

• Precision Point-of-Load Power Supply

SIMPLIFIED SCHEMATIC

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SWIFT, PowerPAD are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (20 pages)

PAGE 1
Typical Size 6,4 mm X 6,6 mm www.ti.
PAGE 2
TPS54372 www.ti.com SLVS430D – JUNE 2002 – REVISED FEBRUARY 2005 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) (1) (2) TA REFIN VOLTAGE PACKAGE PART NUMBER (2) -40°C to 85°C 0.2 V to 1.
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TPS54372 www.ti.com SLVS430D – JUNE 2002 – REVISED FEBRUARY 2005 DISSIPATION RATINGS PACKAGE (1) (2) THERMAL IMPEDANCE JUNCTION-TO-AMBIENT 20-Pin PWP with solder 26.0°C/W 20-Pin PWP without solder 57.5°C/W (1) (2) (3) TA = 25°C POWER RATING 3.85 W TA = 70°C POWER RATING (3) 1.73 W TA = 85°C POWER RATING 2.11 W 1.54 W 0.96 W 0.69 W For more information on the PWP package, see TI technical brief, literature number SLMA002. Test board conditions: a. 3-inch x 3-inch, 4 layers, thickness: 0.
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TPS54372 www.ti.com SLVS430D – JUNE 2002 – REVISED FEBRUARY 2005 ELECTRICAL CHARACTERISTICS (continued) TJ = –40°C to 125°C, VI = 3 V to 6 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PWM COMPARATOR PWM comparator propagation delay time, PWM comparator input to PH pin (excluding dead time) 10-mV overdrive (1) 70 85 ns 1.20 1.40 V SLOW-START/ENABLE Enable threshold voltage, ENA Enable hysteresis voltage, 0.
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TPS54372 www.ti.com SLVS430D – JUNE 2002 – REVISED FEBRUARY 2005 HTTSOP PowerPAD (TOP VIEW) AGND VSENSE COMP STATUS BOOT PH PH PH PH PH 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 RT ENA REFIN VBIAS VIN VIN VIN PGND PGND PGND Terminal Functions TERMINAL DESCRIPTION NAME NO. AGND 1 Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, and RT resistor. Connect PowerPAD connection to AGND. BOOT 5 Bootstrap output. 0.022-µF to 0.
PAGE 6
TPS54372 www.ti.com SLVS430D – JUNE 2002 – REVISED FEBRUARY 2005 INTERNAL BLOCK DIAGRAM VBIAS AGND Enable Comparator Falling Edge Deglitch ENA 1.2 V Hysteresis: 0.03 V 2.5 µs VIN UVLO Comparator 2.95 V Hysteresis: 0.16 V VDDQ VIN ILIM Comparator Thermal Shutdown 150°C VIN Leading Edge Blanking Falling and Rising Edge Deglitch VIN REG VBIAS SHUTDOWN 100 ns BOOT 30 mΩ 2.5 µs SS_DIS SHUTDOWN PH REFIN Slow-start (0.
PAGE 7
TPS54372 www.ti.com SLVS430D – JUNE 2002 – REVISED FEBRUARY 2005 TYPICAL CHARACTERISTICS VIN = 3.3 V IO = 3 A 80 60 40 20 0 25 85 TJ − Junction Temperature − °C VIN = 5 V IO = 3 A 80 70 60 50 40 30 20 10 0 −40 125 0 25 85 125 750 650 550 450 RT = Open 350 250 −40 0 25 85 125 TJ − Junction Temperature − °C TJ − Junction Temperature − °C Figure 1. Figure 2. Figure 3.
PAGE 8
TPS54372 www.ti.com SLVS430D – JUNE 2002 – REVISED FEBRUARY 2005 APPLICATION INFORMATION TP2 VI J1 2 1 GND TP9 TP3 C4 10 µF TP1 1 2 3 R2 36.5 kΩ 4 C2 470 pF 5 6 C6 0.047 pF C1 12 pF 7 8 9 10 R1 10 kΩ AGND RT J2 VDDQ 2 20 R6 10 kΩ VSENSE ENA 19 18 REFIN COMP 17 STATUS VBIAS 16 VIN BOOT 15 VIN PH 14 VIN PH 13 PH PGND 12 PGND PH 11 PGND PH PwrPAD R7 10 kΩ C9 1 µF R5 71.5 kΩ GND C13 0.1 µF C12 0.1 µF TP8 C8 10 µF 21 R3 1.
PAGE 9
TPS54372 www.ti.com OPERATING FREQUENCY In the application circuit, RT is grounded through a 71.5-kΩ resistor to select the operating frequency of 700 kHz. To set a different frequency, place a 68-kΩ to 180-kΩ resistor between RT (pin 20) and analog ground or leave RT floating to select the default of 350 kHz. The resistance can be approximated using the following equation: 500 kHz R 100 [k ] Switching Frequency OUTPUT FILTER The output filter is composed of a 1.0-µH inductor and two 150-µF capacitors.
PAGE 10
TPS54372 www.ti.com SLVS430D – JUNE 2002 – REVISED FEBRUARY 2005 ANALOG GROUND TRACE AGND RT COMPENSATION NETWORK TRACKING VOLTAGE ENA VSENSE COMP RESISTOR DIVIDER NETWORK REFIN BIAS CAPACITOR PWRGD BOOT CAPACITOR VBIAS EXPOSED VIN BOOT PH VOUT OUTPUT INDUCTOR PH POWERPAD AREA Vin VIN PH VIN PH PGND PH PGND PH PGND INPUT BYPASS CAPACITOR OUTPUT FILTER CAPACITOR INPUT BULK FILTER TOPSIDE GROUND AREA VIA to Ground Plane Figure 9.
PAGE 11
TPS54372 www.ti.com SLVS430D – JUNE 2002 – REVISED FEBRUARY 2005 PERFORMANCE GRAPHS (continued) LINE REGULATION vs INPUT VOLTAGE OUTPUT RIPPLE VOLTAGE 1.253 Line Regulation IO = 1.5 A 1.251 1.25 IO = 3 A 1.249 fs = 700 kHz, TA = 25°C, VO = 1.25 V 1.248 fs = 700 kHz, IO = 3 A, VI = 5 V, VO = 1.25 V Output Ripple Voltage − 10 mV/div IO = 0 A 1.252 1.247 4 5 VI − Input Voltage − V t − Time − 1 µs/div 6 Figure 13. TRANSIENT RESPONSE SLOW-START TIMING VI = 5 V, VO = 1.25 V 0 A to 2.
PAGE 12
TPS54372 www.ti.com SLVS430D – JUNE 2002 – REVISED FEBRUARY 2005 DETAILED DESCRIPTION UNDERVOLTAGE LOCKOUT (UVLO) VOLTAGE REFERENCE The TPS54372 incorporates an undervoltage lockout circuit to keep the device disabled when the input voltage (VIN) is insufficient. During power up, internal circuits are held inactive until VIN exceeds the nominal UVLO threshold voltage of 2.95 V. Once the UVLO start threshold is reached, device start-up begins.
PAGE 13
TPS54372 www.ti.com error amplifier output voltage, the PWM comparator resets the latch, thus turning off the high-side FET and turning on the low-side FET. The low-side FET remains on until the next oscillator pulse discharges the PWM ramp. During transient conditions, the error amplifier output could be below the PWM ramp valley voltage or above the PWM peak voltage.
PAGE 14
PACKAGE OPTION ADDENDUM www.ti.
PAGE 15
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS54372PWPR Package Package Pins Type Drawing SPQ HTSSOP 2000 PWP 20 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 16.4 Pack Materials-Page 1 6.95 B0 (mm) K0 (mm) P1 (mm) 7.1 1.6 8.0 W Pin1 (mm) Quadrant 16.
PAGE 16
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS54372PWPR HTSSOP PWP 20 2000 367.0 367.0 38.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.