! " #$ # % & # " User’s Guide June 2003 PMP Systems Power SLVU088
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
EVM IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not considered by TI to be fit for commercial use.
EVM WARNINGS AND RESTRICTIONS It is important to operate this EVM with an input voltage of 3.3 V and the output voltage range of 0.9 V to 2.5 V, or an input voltage of 5 V and the output voltage range of 0.9 V to 3.3 V. Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions concerning the input range, please contact a TI field representative prior to connecting the input power.
Preface About This Manual This user’s guide describes the characteristics, operation and use of the TPS54373EVM–237 evaluation module (EVM). The user’s guide includes a schematic diagram, printout-circuit board (PCB) layouts, and bill of materials. How to Use This Manual - Chapter 1—Introduction - Chapter 2—Test Setup and Results - Chapter 3—Board Layout - Chapter 4—Schematic and Bill of MAterials Information About Cautions and Warnings This book may contain cautions and warnings.
Information About Cautions and Warnings Trademarks SWIFT is a trademark of Texas Instruments. PowerPAD is a trademark of Texas Instruments.
Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Performance Specification Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Modifications . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents Figures 1–1 2–1 2–2 2–3 2–4 2–5 2–6 2–7 2–8 2–9 2–10 2–11 2–12 2–13 2–14 2–15 3–1 3–2 3–3 4–1 Frequency Trimming Resistor Selection Graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Measured Efficiency, TPS54373 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 1 Introduction This chapter contains background information for the TPS54373 as well as support documentation for the TPS54373EVM-237 evaluation module (SLVP237). The TPS54373EVM-237 performance specifications are given, with the schematic and bill of material for the TPS54373EVM-237. Topic Page 1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Performance Specification Summary . . . . . . . . . . . . . . . . . . . . . .
Background 1.1 Background The TPS54373EVM-237 evaluation module uses the TPS54373 synchronous buck regulator with disabled sink during start-up (DSDS) to provide an output voltage of from 0.9 V to 2.5 V from a nominal 3.3-V input or 0.9 V to 3.3 V for a nominal 5-V input. Rated input voltage and output current range is given in Table 1–1. This evaluation module is designed to demonstrate the small PCB areas that are achieved when designing with the TPS54373 regulator.
Performance Specification Summary 1.2 Performance Specification Summary A summary of the TPS54373EVM-225 performance specifications is provided in Table 1–2. Specifications are given for an input voltage of 3.3 V and an output voltage of 1.8 V unless otherwise specified. The ambient temperature is 25°C for all measurements, unless otherwise noted. The data presented in Table 1–2 compiled with no precharge. The output, J3, is open and no voltage source is present on J4.
Modifications 1.3 Modifications The TPS54373EVM-237 is designed to demonstrate the small size that can be attained when designing with the TPS54373, so many of the features, which allow for extensive modifications have been omitted from this EVM. Changing the value of R2 can change the output voltage in the range of 0.9 V to 3.3 V. The value of R2 for a specific output voltage can be calculated by using Equation 1–1. Table 1–3 list the values for R2 for some common output voltages. Equation 1–1.
Modifications Figure 1–1. Frequency Trimming Resistor Selection Graph 750 700 Switching Frequency – kHz 650 600 550 500 450 400 350 300 250 60 70 80 90 100 110 120 130 140 150 160 170 180 Resistance – kΩ The TPS54373EVM–237 EVM supports alternate output filter configurations by means of pads located on the back side of the PCB. The positions for C15 and C16 provide space for one or two electrolytic type surface-mount capacitors as an alternative to the ceramic types provided.
Modifications Warning Under no circumstances can the output voltage be allowed to precharge to a level higher than the preset output voltage. If this condition occurs during start-up, the TPS54373 device does not begin switching. If a voltage transient on the precharge voltage source causes the series diodes to conduct, current may be sunk through the low side FET in the device, possibly damaging the device.
Chapter 2 Test Setup and Results This chapter describes how to properly connect, setup, and use the TPS54373EVM-237 evaluation module. The chapter also includes test results typical for the TPS54373EVM-237 and covers efficiency, output voltage regulation, load transients, loop response, output ripple, input ripple, and start-up. Topic Page 2.1 Input/Output Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 Efficiency . . . . . . . . . . . . . . . . . . . . .
Input/Output Connections 2.1 Input/Output Connections The TPS54373EVM-237 has the following three input/output connectors: VI J1, VO J2 and PRECHG_IN J4. A diagram showing the connection points is shown in Figure 2–1. A power supply capable of supplying 5 A is connected to J1 through a pair of 20 AWG wires. The load is connected to J2 through a pair of 20 AWG wires. The maximum load current capability is 3 A. Wire lengths should be minimized to reduce losses in the wires.
Efficiency 2.2 Efficiency The TPS54373EVM-237 efficiency peaks at load current of about 1 A to 2 A, and then decreases as the load current increases towards full load. Figure 2–2 shows the efficiency for the TPS54373 at an ambient temperature of 25°C. The efficiency is lower at higher ambient temperatures, due to temperature variation in the drain-to-source resistance of the MOSFETs.
Power Dissipation 2.3 Power Dissipation The low junction-to-case thermal resistance of the PWP package, along with a good board layout, allows the TPS54373EVM–237 EVMs to output full rated load current while maintaining safe junction temperatures. With a 3.3-V input source and a 3-A load, the junction temperature is approximately 60°C, while the case temperature is approximately 55°C. The total circuit losses at 25°C are shown in Figure 2–3. Power dissipation is shown for input voltages of 3.3 V and 5.0 V.
Output Voltage Regulation 2.4 Output Voltage Regulation The output voltage load regulation of the TPS54373EVM-237 is shown in Figure 2–4, while the output voltage line regulation is shown in Figure 2–5. Measurements are given for an ambient temperature of 25°C. Figure 2–4. Load Regulation OUTPUT VOLTAGE vs OUTPUT CURRENT 0.5 VO – Output Voltage Change – % 0.4 0.3 0.2 0.1 VI = 3.3 V 0 –0.1 VI = 5 V –0.2 –0.3 –0.4 –0.5 0 0.5 1 1.5 2 2.5 IO – Output Current – A 3 3.5 Figure 2–5.
Load Transients 2.5 Load Transients The TPS54373EVM-237 response to load transients is shown in Figure 2–6. The current step is from 25% to 75% of maximum rated load. Total peak-to-peak voltage variation is as shown, including ripple and noise on the output. Figure 2–6.
Loop Characteristics 2.6 Loop Characteristics The TPS54373EVM-237 loop response characteristics are shown in Figure 2–7 and Figure 2–8. Gain and phase plots are shown for each device at minimum and maximum operating voltage. Figure 2–7. Measured Loop Response, TPS54373, VI = 3 V MEASURED LOOP RESPONSE 60 180 50 150 120 40 Phase 30 90 Gain – dB 10 Gain 30 0 0 –10 –30 –20 –60 –30 –90 –40 –120 –50 –150 –60 100 1k 10 k 100 k Phase – deg 60 20 –180 1M f – Frequency – Hz Figure 2–8.
Output Voltage Ripple 2.7 Output Voltage Ripple The TPS54373EVM–237 output voltage ripple is shown in Figure 2–9. The input voltage is 3.3 V for the TPS54373. Output current is the rated full load of 3 A. Voltage is measured directly across output capacitors. Figure 2–9.
Input Voltage Ripple 2.8 Input Voltage Ripple The TPS54373EVM–237 output voltage ripple is shown in Figure 2–10. The input voltage is 3.3 V for the TPS54373. Output current for each device is rated full load of 3 A. Figure 2–10.
Start-Up 2.9 Start-Up Start-up voltage waveforms of the TPS54373EVM–237 are shown in Figure 2–11 through Figure 2–15. Figure 2–11 shows the start-up waveform with no precharge on the output. When the VI reaches the nominal 2.95-V UVLO threshold, the slow start capacitor C5 begins to charge. When the voltage on the SS/ENA pin reaches the enable threshold of 1.2 V, the internal reference begins to ramp up at the slow start rate.
Start-Up Figure 2–12. Measured Start-Up Waveform, Two Diode Precharge VI 500 mV/div VO 500 mV/div Time Scale 5 ms/div Figure 2–13.
Start-Up Figure 2–14. Measured Start-Up Waveform, Four Diode Precharge VI 500 mV/div VO 500 mV/div Time Scale 5 ms/div Figure 2–15 shows the start-up waveform with the output precharged through 4 diodes and no load. Compare the precharge level to that in Figure 2–14 to see how start-up load current affects the voltage drop across the diodes and the final precharge voltage.
Start-Up Figure 2–15.
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Chapter 3 Board Layout This chapter provides a description of the TPS54373EVM–237 board layout and layer illustrations. Topic 3.1 Page Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Layout 3.1 Layout The board layout for the TPS54373EVM-237 is shown in Figure 3–1 through Figure 3–3. The top-side layer of the TPS54373EVM-237 is laid out in a manner typical of a user application. The bottom layer of the TPS54373EVM-237 is designed to accommodate optional alternate output filter capacitors. The top and bottom layers are 1.5 oz. copper. The top layer contains the main power traces for VI, VO, and V(phase).
Layout Figure 3–2. Bottom-Side Layout (looking from top side) Figure 3–3.
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Chapter 4 Schematic and Bill of Materials The TPS54373EVM–237 schematic and bill of materials are presented in this chapter. Topic Page 4.1 Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Schematic 4.1 Schematic The schematic for the TPS54373EVM–237 is shown in Figure 4–1. Figure 4–1. TPS54373EVM–237 Schematic TP2 J1 J3 2 Vin 1 2 1 GND + C1 TP3 C10 10 µF TP1 U1 TPS54373PWP 1 2 R3 6.34 kΩ 3 4 5 C6 1500 pF C7 82 pF C3 0.047 µF TP10 9 10 R2 9.
Bill of Materials 4.2 Bill of Materials Table 4–1 contains the bill of materials for the TPS54380EVM–001. Table 4–1. TPS54373EVM-237 Bill of Materials Count RefDes Description MFR Part Number C1 Capacitor, POSCAP, 220 µF, 10 V, 40 mΩ, 20% D4 Sanyo 10TPB220M 1 C13 Capacitor, ceramic, 0.1 µF, 25 V, X7R, 10% 603 Std Std 1 C14 Capacitor, ceramic, 3300 pF, 50–V, X7R, 10% 603 Std Std 2 C15, C16 Open 62100 3 C2, C11, C12 Capacitor, ceramic, 22 µF, 6.
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