Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - DC/DC voltage regulator Holder HTSSOP 20

TPS54380

SLVS454B − JANUARY 2003 − REVISED FEBRUARY 2005

3-V TO 6-V INPUT, 3-A OUTPUT TRACKING SYNCHRONOUS BUCK

PWM SWITCHER WITH INTEGRATED FETs (SWIFT™) FOR SEQUENCING

6,4 mm X 6,6 mm

Typical Size

FEATURES

D Power-Up/Down Tracking for Sequencing

D 60-mΩ MOSFET Switches for High Efficiency

at 3-A Continuous Output Source or Sink

Current

D Wide PWM Frequency:

Fixed 350 kHz or Adjustable 280 kHz to

700 kHz

D Power Good and Enable

D Load Protected by Peak Current Limit and

Thermal Shutdown

D Integrated Solution Reduces Board Area and

Component Count

APPLICATIONS

D Low-Voltage, High-Density Distributed Power

Systems

D Point of Load Regulation for

High-Performance DSPs, FPGAs, ASICs, and

Microprocessors Requiring Sequencing

D Broadband, Networking, and Optical

Communications Infrastructure

DESCRIPTION

As a member of the SWIFT™ family of dc/dc regulators,

the TPS54380 low-input voltage, high-output current,

synchronous buck PWM converter integrates all

required active components. Using the TRACKIN pin

with other regulators, simultaneous power up and down

are easily implemented. Included on the substrate with

the listed features are a true, high-performance, voltage

error amplifier that enables maximum performance and

flexibility in choosing the output filter L and C

components; an undervoltage-lockout circuit to prevent

start-up until the input voltage reaches 3 V; an internally

or externally set slow-start circuit to limit inrush

currents; and a power-good output useful for

processor/logic reset.

The TPS54380 is available in a thermally enhanced

20-pin TSSOP (PWP) PowerPAD™ package, which

eliminates bulky heatsinks. TI provides evaluation

modules and the SWIFT™ designer software tool to aid

in quickly achieving high-performance power supply

designs to meet aggressive equipment development

cycles.

SIMPLIFIED SCHEMATIC

VIN PH

BOOT

PGND

VSENSE

Core Supply

COMPAGND

VBIAS

Input

TPS54380

TRACKIN

I/O Supply

VI/O = 3.3 V

Vcore = 1.8 V

= 1 Ω

START-UP WAVEFORM

1 ms/div

500 mV/div

PRODUCTION DATA information is current as of publication date. Products

conform to specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all parameters.

PowerPAD and SWIFT are trademarks of Texas Instruments.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

www.ti.com

Summary of content (21 pages)

PAGE 1
Typical Size 6,4 mm X 6,6 mm TPS54380 www.ti.
PAGE 2
TPS54380 www.ti.com SLVS454B − JANUARY 2003 − REVISED FEBRUARY 2005 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION TA OUTPUT VOLTAGE PACKAGE PART NUMBER −40°C to 85°C 0.9 V to 3.3 V Plastic HTSSOP (PWP)(1) TPS54380PWP (1) The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e.
PAGE 3
TPS54380 www.ti.com SLVS454B − JANUARY 2003 − REVISED FEBRUARY 2005 ELECTRICAL CHARACTERISTICS over operating free-air temperature range unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE, VIN Input voltage range, VIN I(Q) Quiescent current 3.0 6.0 fs = 350 kHz, RT open, PH pin open 6.2 9.6 fs = 500 kHz, RT = 100 kΩ, PH pin open 8.4 12.8 1 1.4 2.95 3.
PAGE 4
TPS54380 www.ti.
PAGE 5
TPS54380 www.ti.com SLVS454B − JANUARY 2003 − REVISED FEBRUARY 2005 PWP PACKAGE (TOP VIEW) AGND VSENSE COMP PWRGD BOOT PH PH PH PH PH 1 2 3 4 5 6 7 8 9 10 20 19 18 17 THERMAL 16 PAD 15 14 13 12 11 RT ENA TRACKIN VBIAS VIN VIN VIN PGND PGND PGND TERMINAL FUNCTIONS TERMINAL NAME NO. DESCRIPTION AGND 1 Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor. Connect PowerPAD to AGND. BOOT 5 Bootstrap output. 0.022-µF to 0.
PAGE 6
TPS54380 www.ti.com SLVS454B − JANUARY 2003 − REVISED FEBRUARY 2005 INTERNAL BLOCK DIAGRAM VBIAS AGND Enable Comparator ENA 1.2 V Hysteresis: 0.03 V Falling Edge Deglitch 2.5 µs VIN UVLO Comparator VIN 2.95 V Hysteresis: 0.16 V I/O VIN ILIM Comparator Thermal Shutdown 150°C Falling and Rising Edge Deglitch 100 ns BOOT Sense FET 60 mΩ 2.5 µs SHUTDOWN PH Multiplexer + − R Q Error Amplifier Reference S PWM Comparator 25-ns Adaptive Dead-Time VIN 60 mΩ PGND Power-Good Comparator VSENSE 0.
PAGE 7
TPS54380 www.ti.com SLVS454B − JANUARY 2003 − REVISED FEBRUARY 2005 TYPICAL CHARACTERISTICS DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE VI = 3.3 V 100 IO = 3 A 80 60 40 20 0 −40 0 25 85 VI = 5 V IO = 3 A 80 60 40 20 0 −40 125 TJ − Junction Temperature − °C 0 25 85 125 250 −40 600 RT = 100 k 500 400 RT = 180 k 300 25 85 0.893 0.891 0.889 0.887 TJ − Junction Temperature − °C 0 Figure 4 85 25 0.8910 0.
PAGE 8
TPS54380 www.ti.com SLVS454B − JANUARY 2003 − REVISED FEBRUARY 2005 APPLICATION INFORMATION Figure 9 shows the schematic diagram for a typical TPS54380 application. The TPS54380 (U1) can provide greater than 3 A of output current at a nominal output voltage of 1.8 V. For proper thermal performance, the exposed thermal PowerPAD underneath the integrated circuit package must be soldered to the printed-circuit board. To provide power-up tracking, the enable of the I/O supply should be used.
PAGE 9
www.ti.com TPS54380 SLVS454B − JANUARY 2003 − REVISED FEBRUARY 2005 An additional high-frequency bypass capacitor, C12, is also used. The feedback loop is compensated so that the unity gain frequency is approximately 50 kHz. PCB LAYOUT Figure 10 shows a generalized PCB layout guide for the TPS54380. The VIN pins should be connected together on the printed-circuit board (PCB) and bypassed with a low-ESR ceramic bypass capacitor.
PAGE 10
TPS54380 www.ti.com SLVS454B − JANUARY 2003 − REVISED FEBRUARY 2005 ANALOG GROUND TRACE AGND RT COMPENSATION NETWORK TRACKING VOLTAGE ENA VSENSE COMP RESISTOR DIVIDER NETWORK TRACKIN BIAS CAPACITOR PWRGD BOOT CAPACITOR EXPOSED BOOT OUTPUT INDUCTOR PH VIN Vin VIN POWERPAD AREA PH VOUT VBIAS PH VIN PH PGND PH PGND PH PGND INPUT BYPASS CAPACITOR OUTPUT FILTER CAPACITOR INPUT BULK FILTER TOPSIDE GROUND AREA VIA to Ground Plane Figure 10.
PAGE 11
TPS54380 www.ti.com SLVS454B − JANUARY 2003 − REVISED FEBRUARY 2005 30 90 20 60 10 30 Gain 0 −10 0 −30 115 95 85 −90 −40 −120 −50 −150 35 −180 1M 25 100 k f − Frequency − Hz Safe Operating Area(1) 65 −30 10 k VI = 3.
PAGE 12
TPS54380 www.ti.com SLVS454B − JANUARY 2003 − REVISED FEBRUARY 2005 VBIAS REGULATOR (VBIAS) The VBIAS regulator provides internal analog and digital blocks with a stable supply voltage over variations in junction temperature and input voltage. A high quality, low-ESR, ceramic bypass capacitor is required on the VBIAS pin. X7R- or X5R-grade dielectrics are recommended because their values are more stable over temperature. The bypass capacitor must be placed close to the VBIAS pin and returned to AGND.
PAGE 13
TPS54380 www.ti.com SLVS454B − JANUARY 2003 − REVISED FEBRUARY 2005 OVERCURRENT PROTECTION The cycle-by-cycle current limiting is achieved by sensing the current flowing through the high-side MOSFET and comparing this signal to a preset overcurrent threshold. The high-side MOSFET is turned off within 200 ns of reaching the current limit threshold. A 100-ns leading edge blanking circuit prevents the current limit from false tripping.
PAGE 14
PAGE 15
PACKAGE OPTION ADDENDUM www.ti.
PAGE 16
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS54380PWPR Package Package Pins Type Drawing SPQ HTSSOP 2000 PWP 20 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 16.4 Pack Materials-Page 1 6.95 B0 (mm) K0 (mm) P1 (mm) 7.1 1.6 8.0 W Pin1 (mm) Quadrant 16.
PAGE 17
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS54380PWPR HTSSOP PWP 20 2000 367.0 367.0 38.
PAGE 18
PAGE 19
PAGE 20
PAGE 21
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.