Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - DC/DC voltage regulator Holder HTSSOP 14

Vout (50 mV/div)

Iout (2A/div)

100 s/divm

TPS54425

www.ti.com

SLVSA84C –AUGUST 2010– REVISED JULY 2011

4-A OUTPUT SINGLE SYNCHRONOUS STEP DOWN SWITCHER

WITH INTEGRATED FET ( SWIFT™)

Check for Samples: TPS54425

FEATURES

DESCRIPTION

The TPS54425 is an adaptive on-time D-CAP2™

• D-CAP2™ Mode Enables Fast Transient

mode synchronous buck converter. The TPS54425

Response

enables system designers to complete the suite of

• Low Output Ripple and Allows Ceramic Output

various end equipment’s power bus regulators with a

Capacitor

cost effective, low component count, low standby

current solution. The main control loop for the

• Wide V

Input Voltage Range: 4.5 V to 18 V

TPS54425 uses the D-CAP2™ mode control which

• Output Voltage Range: 0.76 V to 5.5 V

provides a very fast transient response with no

• Highly Efficient Integrated FET’s Optimized

external compensation components. The TPS54425

for Lower Duty Cycle Applications

also has a proprietary circuit that enables the device

– 65 mΩ (High Side) and 55 mΩ (Low Side)

to adopt to both low equivalent series resistance

(ESR) output capacitors, such as POSCAP or

• High Efficiency, less than 10 μA at shutdown

SP-CAP, and ultra-low ESR ceramic capacitors. The

• High Initial Bandgap Reference Accuracy

device operates from 4.5-V to 18-V VIN input. The

• Adjustable Soft Start

output voltage can be programmed between 0.76 V

and 5.5 V. The device also features an adjustable

• Pre-Biased Soft Start

soft start time and a power good function. The

• 700-kHz Switching Frequency (f

)

TPS54425 is available in the 14-pin HTSSOP

• Cycle By Cycle Over Current Limit

package, and designed to operate from –40°C to

85°C.

• Power Good Output

APPLICATIONS

• Wide Range of Applications for Low Voltage

System

– Digital TV Power Supply

– High Definition Blu-ray Disc™ Players

– Networking Home Terminal

– Digital Set Top Box (STB)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2SWIFT, D-CAP2, PowerPAD are trademarks of Texas Instruments.

3Blu-ray Disc is a trademark of Blu-ray Disc Association.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (24 pages)

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TPS54425 SLVSA84C – AUGUST 2010 – REVISED JULY 2011 www.ti.com 4-A OUTPUT SINGLE SYNCHRONOUS STEP DOWN SWITCHER WITH INTEGRATED FET ( SWIFT™) Check for Samples: TPS54425 FEATURES DESCRIPTION • The TPS54425 is an adaptive on-time D-CAP2™ mode synchronous buck converter. The TPS54425 enables system designers to complete the suite of various end equipment’s power bus regulators with a cost effective, low component count, low standby current solution.
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TPS54425 SLVSA84C – AUGUST 2010 – REVISED JULY 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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TPS54425 SLVSA84C – AUGUST 2010 – REVISED JULY 2011 www.ti.com RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) VIN Supply input voltage range VI Input voltage range MIN MAX 4.5 18 VBST –0.3 24 VBST(10 ns transient) –0.3 27 SS, PG –0.1 5.7 EN –0.1 18 VO, VFB –0.1 5.5 SW1, SW2 –1.8 18 UNIT V V –3 21 PGND1, PGND2 –0.1 0.1 –0.1 5.
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TPS54425 SLVSA84C – AUGUST 2010 – REVISED JULY 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range, VIN = 12V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 4.7 5.4 7.5 UNIT CURRENT LIMIT Iocl Current limit LOUT = 1.5 μH (2), TA = -20ºC to 85ºC A THERMAL SHUTDOWN TSDN Thermal shutdown threshold Shutdown temperature Hysteresis (2) 165 (2) °C 30 ON-TIME TIMER CONTROL TON On time VIN = 12 V, VO = 1.
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TPS54425 SLVSA84C – AUGUST 2010 – REVISED JULY 2011 www.ti.com DEVICE INFORMATION PWP PACKAGE (TOP VIEW) 1 2 3 VO VFB VREG5 POWER PAD VIN2 14 VIN1 13 VBST 12 SW2 11 SW1 10 TPS54425 4 SS PWP HTSSOP14 5 GND 6 PG PGND2 9 7 EN PGND1 8 PIN FUNCTIONS PIN NAME NO. DESCRIPTION VO 1 Connect to output of converter. This terminal is used for On-Time Adjustment. VFB 2 Converter feedback input. Connect to output voltage with feedback resistor divider. VREG5 3 5.
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TPS54425 SLVSA84C – AUGUST 2010 – REVISED JULY 2011 www.ti.
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TPS54425 www.ti.com SLVSA84C – AUGUST 2010 – REVISED JULY 2011 OVERVIEW The TPS54425 is a 4-A synchronous step-down (buck) converter with two integrated N-channel MOSFETs. It operates using D-CAP2™ mode control. The fast transient response of D-CAP2™ control reduces the output capacitance required to meet a specific level of performance. Proprietary internal circuitry allows the use of low ESR output capacitors including ceramic and special polymer types.
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TPS54425 SLVSA84C – AUGUST 2010 – REVISED JULY 2011 www.ti.com VREG5 VREG5 is an internally generated voltage source used by the TPS54425. It is derived directly from the input voltage and is nominally regulated to 5.5 V when the input voltage is above 5.6 V. The output of the VREG5 regulator is the input to the internal UVLO function. VREG5 must be above the UVLO wake up threshold voltage (3.8 V typical) for the TPS54425 to function. Connect a 1.
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TPS54425 SLVSA84C – AUGUST 2010 – REVISED JULY 2011 www.ti.com TYPICAL CHARACTERISTICS VCC CURRENT vs JUNCTION TEMPERATURE VCC SHUTDOWN CURRENT vs JUNCTION TEMPERATURE 1200 8 Ivccsdn - Shutdown Current - mA ICC - Supply Current - mA 1000 800 600 400 200 0 -50 0 50 100 TJ - Junction Temperature - °C 6 4 2 0 -50 150 0 50 100 TJ - Junction Temperature - °C Figure 1. Figure 2. EN CURRENT vs EN VOLTAGE 1.05-V OUTPUT VOLTAGE vs OUTPUT CURRENT 100 150 1.1 1.
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TPS54425 SLVSA84C – AUGUST 2010 – REVISED JULY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) 1.05-V OUTPUT VOLTAGE vs INPUT VOLTAGE 1.05-V, 50-mA to 2-A LOAD TRANSIENT RESPONSE 1.1 Vout (50 mV/div) VO - Output Voltage - V 1.075 IO = 0 A 1.05 IO = 1 A 1.025 1 0 Iout (2 A/div) 5 10 15 VI - Input Voltage - V 20 100 ms/div Figure 5. Figure 6. START-UP WAVE FORM EFFICIENCY vs OUTPUT CURRENT 100 VO = 3.3 V 90 EN (10 V/div) VO = 2.5 V Vout (0.5 V/div) Efficiency - % 80 VO = 1.
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TPS54425 SLVSA84C – AUGUST 2010 – REVISED JULY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) SWITCHING FREQUENCY vs INPUT VOLTAGE (IO = 1 A) SWITCHING FREQUENCY vs OUTPUT CURRENT 800 fsw - Switching Frequency - kHz fsw - Switching Frequency - kHz 800 700 VO = 1.8 V 600 VO = 3.3 V 500 400 0 5 10 15 VI - Input Voltage - V 20 700 VO = 1.8 V 600 VO = 3.3 V 500 400 0 1 2 3 IO - Output Current - A Figure 9. Figure 10.
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TPS54425 SLVSA84C – AUGUST 2010 – REVISED JULY 2011 www.ti.com DESIGN GUIDE Step By Step Design Procedure To • • • • • begin the design process, you must know a few application parameters: Input voltage range Output voltage Output current Output voltage ripple Input voltage ripple Figure 13. Shows the schematic diagram for this design example. Output Voltage Resistors Selection The output voltage is set with a resistor divider from the output node to the VFB pin.
PAGE 13
TPS54425 SLVSA84C – AUGUST 2010 – REVISED JULY 2011 www.ti.com At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal gain of the TPS54425. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls off at a -40 dB per decade rate and the phase drops rapidly.
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TPS54425 SLVSA84C – AUGUST 2010 – REVISED JULY 2011 www.ti.com Input Capacitor Selection The TPS54425 requires an input decoupling capacitor and a bulk capacitor is needed depending on the application. A ceramic capacitor over 10 μF is recommended for the decoupling capacitor. An additional 0.1 µF capacitor from pin 14 to ground is recommended to improve the stability of the over-current limit function. The capacitor voltage rating needs to be greater than the maximum input voltage.
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TPS54425 SLVSA84C – AUGUST 2010 – REVISED JULY 2011 www.ti.com LAYOUT CONSIDERATIONS 1. Keep the input switching current loop as small as possible. 2. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the feedback pin of the device. 3. Keep analog and non-switching components away from switching components. 4.
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TPS54425 SLVSA84C – AUGUST 2010 – REVISED JULY 2011 www.ti.com REVISION HISTORY Changes from Original (August 2010) to Revision A • Page Added VIN = 12V to the conditions statement in the Electrical Characteristics table ........................................................... 3 Changes from Revision A (October 2010) to Revision B Page • Changed the FUNCTIONAL BLOCK DIAGRAM ..................................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS54425PWPR Package Package Pins Type Drawing SPQ HTSSOP 2000 PWP 14 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 12.4 Pack Materials-Page 1 6.9 B0 (mm) K0 (mm) P1 (mm) 5.6 1.6 8.0 W Pin1 (mm) Quadrant 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS54425PWPR HTSSOP PWP 14 2000 367.0 367.0 35.
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