Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - DC/DC voltage regulator Holder HTSSOP 16

V = 1.5 V (50 mV/div)

Iout (1 A/div)

t - Time - 100 s/divm

Input Voltage

PGND

SW1

VIN1

VBST1

EN1

VFB2

VFB1

GND

VREG5

PGND1

VIN2

VBST2

EN2

SW2

PG1

PG2

PGND2

TPS54494

HTSSOP16

PGND

SGND

C11

VO1

C21

R11

R21

L11

C31

C32

L12

C12

VO2

C22

R12

R22

(PowerPAD)

TPS54494

www.ti.com

SLVSBH1B –JUNE 2012–REVISED AUGUST 2013

4A/2A Dual Channel Synchronous Step-Down Switcher with Integrated FET

Check for Samples: TPS54494

FEATURES

APPLICATIONS

• D-CAP2™ Control Mode

• Point-of-Load Regulation in Low Power

Systems for Wide Range of Applications

– Fast Transient Response

– Digital TV Power Supply

– No External Parts Required For Loop

Compensation – Networking Home Terminal

– Compatible with Ceramic Output – Digital Set Top Box (STB)

Capacitors

– DVD Player/Recorder

• Wide Input Voltage Range : 4.5 V to 18 V

– Gaming Consoles and Other

• Output Voltage Range : 0.76V to 7V

DESCRIPTION

• Highly Efficient Integrated FETs Optimized for

The TPS54494 is a dual, adaptive on-time D-CAP2™

Low Duty Cycle Applications

mode synchronous buck converter. The TPS54494

– 90 mΩ (High Side) and 60 mΩ (Low Side)

enables system designers to complete the suite of

• High Initial Reference Accuracy

various end equipment’s power bus regulators with a

cost effective, low component count, and low standby

• 4A CH1 / 2A CH2 Continuous Load Current

current solution. The main control loops of the

• Low-Side r

DS(on)

Loss-Less Current Sensing

TPS54494 use the D-CAP2™ mode control which

• Fixed Soft Start : 1 ms

provides a very fast transient response with no

• Non-Sinking Pre-Biased Soft Start

external compensation components. The adaptive on-

time control supports seamless transition between

• Powergood

PWM mode at higher load conditions and Eco-

• 700 kHz Switching Frequency

mode™ operation at light loads. Eco-mode™ allows

• Cycle-by-Cycle Over-Current Limit Control

the TPS54494 to maintain high efficiency during

lighter load conditions. The TPS54494 is able to

• OCL/UVLO/TSD Protections

adapt to both low equivalent series resistance (ESR)

• Hiccup Timer for Overload Protection

output capacitors such as POSCAP or SP-CAP, and

• Adaptive Gate Drivers with Integrated Boost

ultra-low ESR, ceramic capacitors. The device

PMOS Switch

provides convenient and efficient operation with input

voltages from 4.5V to 18V.

• OCP Constant Due To Thermally Compensated

DS(on)

with 4000ppm/℃℃

The TPS54494 is available in a 4.4 mm × 5 mm 16-

pin TSSOP (PWP) and 4 mm x 4 mm 16-pin VQFN

• 16-Pin HTSSOP, 16-Pin VQFN

(RSA) package, and is specified for an ambient

• Auto-Skip Eco-mode™　　for High Efficiency at

temperature range from –40°C to 85°C.

Light Load

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2D-CAP2, Eco-mode, Eco-Mode are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (29 pages)

PAGE 1
TPS54494 www.ti.com SLVSBH1B – JUNE 2012 – REVISED AUGUST 2013 4A/2A Dual Channel Synchronous Step-Down Switcher with Integrated FET Check for Samples: TPS54494 FEATURES APPLICATIONS • • 1 2 • • • • • • • • • • • • • • • • • D-CAP2™ Control Mode – Fast Transient Response – No External Parts Required For Loop Compensation – Compatible with Ceramic Output Capacitors Wide Input Voltage Range : 4.5 V to 18 V Output Voltage Range : 0.
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TPS54494 SLVSBH1B – JUNE 2012 – REVISED AUGUST 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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TPS54494 www.ti.com SLVSBH1B – JUNE 2012 – REVISED AUGUST 2013 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) VALUES Supply input voltage range Input voltage range VIN1, VIN2 MAX 4.5 18 VBST1, VBST2 –0.1 24 VBST1, VBST2 (10ns transient) –0.1 27 VBST1–SW1, VBST2–SW2 –0.1 5.7 VFB1, VFB2 –0.1 5.7 EN1, EN2 –0.1 18 SW1, SW2 –1.0 18 SW1, SW2 (10ns transient) Output voltage range MIN –3 21 VREG5, PG1 , PG2 –0.1 5.
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TPS54494 SLVSBH1B – JUNE 2012 – REVISED AUGUST 2013 www.ti.com ELECTRICAL CHARACTERISTICS(1) (continued) over recommended free-air temperature range, VIN = 12 V (unless otherwise noted) PARAMETER CONDITIONS MIN TYP MAX UNIT 110 Ω POWER GOOD VPGTH PGx threshold RPG PGx pull-down resistance TPGDLY PGx delay time TPGCOMPSS PGx comparator start-up delay PG from lower VOx (going high) 84% PG from higher VOx (going low) 116% VPGx = 0.5 V 50 Delay for PGx going high 75 1.
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TPS54494 www.ti.
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TPS54494 SLVSBH1B – JUNE 2012 – REVISED AUGUST 2013 www.ti.com FUNCTIONAL BLOCK DIAGRAM - 16% VIN1 PG Comp VIN1 +16% PG1 VBST1 - 32 UV1 Control logic 0.1 µF VO1 SW1 Ref1 VFB1 PGND1 Err SS1 Ref_OCL PGND1 SW1 OCP1 EN1 EN2 EN Logic PGND1 Comp SW1 ZC1 EN Logic VIN1 VREG5 GND CH1 Min-off timer 5VREG 1.0 µF CH2 Min-off timer Fixed SoftStart SS1 UV1 UV2 SS2 UVLO TSD - 32 Ref1 Ref2 REF UVLO Protection Logic VIN2 VIN2 VBST2 UV2 Control logic 0.
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TPS54494 www.ti.com SLVSBH1B – JUNE 2012 – REVISED AUGUST 2013 OVERVIEW The TPS54494 is a 4A/2A dual synchronous step-down (buck) converter with two integrated N-channel MOSFETs for each channel. It operates using D-CAP2™ control mode. The fast transient response of D-CAP2™ control reduces the required output capacitance to meet a specific level of performance. Proprietary internal circuitry allows the use of low ESR output capacitors including ceramic and special polymer types.
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TPS54494 SLVSBH1B – JUNE 2012 – REVISED AUGUST 2013 www.ti.com POWERGOOD The TPS54494 has power-good outputs that are measured on VFBx. The power-good function is activated after the soft-start has finished. If the output voltage is within 16% of the target voltage, the internal comparator detects the power good state and the power good signal becomes high after 1.5ms delay. During start-up, this internal delay starts after 1.5ms of the UVP Enable delay time to avoid a glitch of the power-good signal.
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TPS54494 www.ti.com SLVSBH1B – JUNE 2012 – REVISED AUGUST 2013 TYPICAL CHARACTERISTICS One output is enabled unless otherwise noted. VIN = VIN1 or VIN2. VIN = 12 V, TA = 25°C (unless otherwise noted). EN1, EN2 = ON 1800 Icc − Supply Current (dB) Supply Current−Shutdown Current (µA) 2000 1600 1400 1200 1000 800 600 400 200 VIN1, VIN2 = 12 V 0 −50 0 50 100 Junction Temperature (°C) 150 14 12 10 8 6 4 2 3.40 45 3.38 40 3.
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TPS54494 SLVSBH1B – JUNE 2012 – REVISED AUGUST 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) One output is enabled unless otherwise noted. VIN = VIN1 or VIN2. VIN = 12 V, TA = 25°C (unless otherwise noted). 1.55 1.54 Vout(50mV/div) Output Voltage (V) 1.53 1.52 1.51 1.50 1.49 Iout(2A/div) 1.48 1.47 IOUT = 10 mA IOUT = 1 A 1.46 1.45 0 2 4 6 8 10 12 Input Voltage (V) 14 16 18 20 100 ms/div G007 Figure 7. VO2=1.5V Output Voltage vs Input Voltage Figure 8. VO1=3.
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TPS54494 www.ti.com SLVSBH1B – JUNE 2012 – REVISED AUGUST 2013 TYPICAL CHARACTERISTICS (continued) 100 100 90 90 80 80 70 70 Efficiency (%) Efficiency (%) One output is enabled unless otherwise noted. VIN = VIN1 or VIN2. VIN = 12 V, TA = 25°C (unless otherwise noted). 60 50 40 30 10 0 0.001 40 0.01 0.1 Output Current (A) 1 10 0 0.00 10 750 Switching Frequency (kHz) 800 80 70 60 50 40 30 VIN = 5 V VIN = 12 V VIN = 18 V 20 10 0.
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TPS54494 SLVSBH1B – JUNE 2012 – REVISED AUGUST 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) One output is enabled unless otherwise noted. VIN = VIN1 or VIN2. VIN = 12 V, TA = 25°C (unless otherwise noted). 900 Switching Frequency (kHz) 800 VIN1, VIN2 = 12 V VO = 3.3 V VO1(10mV/div) 700 600 500 400 SW1(5V/div) 300 200 100 VOUT2 = 1.5 V 0 0.01 0.1 1 Output Current (A) 10 400 nsec/div) G019 Figure 19. VO2=1.5V, SW-frequency vs Output Current Figure 20. VO1=3.
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TPS54494 www.ti.com SLVSBH1B – JUNE 2012 – REVISED AUGUST 2013 DESIGN GUIDE Step By Step Design Procedure To • • • begin the design process, you must know a few application parameters: Input voltage range Output voltage Output current In all formulas x is used to indicate that they are valid for both converters. For the calculations the estimated switching frequency of 700 kHz is used. VINx 12V ± 10% C11 10 mF VO1 3.3 V L11 2.2 mH C31 0.
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TPS54494 SLVSBH1B – JUNE 2012 – REVISED AUGUST 2013 www.ti.com At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal gain of the TPS545494. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls off at a –40 dB per decade rate and the phase drops rapidly.
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TPS54494 www.ti.com SLVSBH1B – JUNE 2012 – REVISED AUGUST 2013 Input Capacitor Selection The TPS54494 requires an input decoupling capacitor and a bulk capacitor is needed depending on the application. A ceramic capacitor of or above 10µF is recommended for the decoupling capacitor. Additionally, 0.1 µF ceramic capacitors from pin 1 and Pin 16 to ground are recommended to improve the stability and reduce the SWx node overshoots.
PAGE 16
TPS54494 SLVSBH1B – JUNE 2012 – REVISED AUGUST 2013 www.ti.com 7. Exposed pad of device must be soldered to PGND. 8. VREG5 capacitor should be placed near the device, and connected to GND. 9. Output capacitors should be connected with a broad pattern to the PGND. 10. Voltage feedback loops should be as short as possible, and preferably with ground shields. 11. Kelvin connections should be brought from the output to the feedback pin of the device. 12.
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TPS54494 www.ti.
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TPS54494 SLVSBH1B – JUNE 2012 – REVISED AUGUST 2013 www.ti.com REVISION HISTORY Changes from Original (June 2012) to Revision A Page • Added 16-pin VQFN package to the Features and Description ........................................................................................... 1 • Added the RSA 16 pin package to the Ordering Information table ...................................................................................... 2 • Added the RSA package to the Thermal Information table .....
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 31-Jul-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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PACKAGE MATERIALS INFORMATION www.ti.com 31-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) TPS54494PWPR HTSSOP PWP 16 2000 330.0 12.4 TPS54494RSAR QFN RSA 16 3000 330.0 TPS54494RSAT QFN RSA 16 250 180.0 6.9 5.6 1.6 8.0 12.0 Q1 12.4 4.25 4.25 1.15 8.0 12.0 Q2 12.4 4.25 4.25 1.15 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 31-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS54494PWPR HTSSOP PWP 16 2000 367.0 367.0 35.0 TPS54494RSAR QFN RSA 16 3000 367.0 367.0 35.0 TPS54494RSAT QFN RSA 16 250 210.0 185.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.